Datasheet XWM8190CDW-V Datasheet (Wolfson)

WM8190

(8 + 6) Bit Output 14-bit CIS/CCD AFE/Digitiser

Advanced Informati on, August 1999, Rev 3.0

DESCRIPTION

The WM8190 is a 14-bit analogue front end/digitiser IC
which processes and digitises t he analogue output signals
from CCD sensors or Contac t Im age Sensors (CIS) at pixel
sample rates of up to 6MSPS.

The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Program mable Gain and
Offset adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is tim e multiplexed into a s ingle high-speed 14-bit
Analogue to Digital Converter. The digital output data is
available in 8, 7 or 4-bit wide multiplexed format, with no
missing codes.

An internal 4-bit DAC is supplied for internal ref erence level
generation. This may be used during CDS to reference CI S
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may als o be supplied.
ADC references are generated internally, ensuring opti mum
performance from t he devi ce.

Using an analogue supply voltage of 5V and a digital
interface supply of either 5V or 3.3V, the W M8190 typically
only consumes 250mW when operating from a single
5V supply.

BLOCK DIAGRAM

VSMP

VRLC/VBIAS

(26)

(5)

MCLK

(7)

FEATURES

•

14-bit ADC

•

No missing codes guaranteed

•

6MSPS conversion rate

•

Low power – 250mW typical

•

5V single supply or 5V/3.3V dual supply operation

•

Single or 3 channel operation

•

Correlated double sampling

•

Programmable gain (8-bit resolution)

•

Programmable offset adjust (8-bit resolution)

•

Programmable clamp voltage

•

8,7 or 4-bit wide multiplexed data output formats

•

Internally generated voltage references

•

28-pin SOIC package

•

Serial control interface

APPLICATIONS

•

Flatbed and sheetfeed scanners

•

USB compatible scanners

•

Multi-function peripherals

•

High-performance CCD sensor interface

AVDD

(21)

DVDD1

(3)

DVDD2

(10)

VRT

(24)

VRX

(25)

VRB

(23)

TIMING CONTROLCL

VSR

S

R

M
U

G

X

RINP (1)

GINP (28)

BINP (27)

RLC

RLC

RLC

RLC
DAC

M
U
X

4

CDS

CDS

CDS

B

R
G
B

M
U
X

8

8

(22)

AGND1

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK
Tel: [phone]
Fax: [phone]
Email: [email protected]
http://www.wolfson.co.uk

8

OFFSET
DAC

OFFSET
DAC

OFFSET
DAC

PGA

+

8

+

PGA

8

PGA

+

8

(2)

AGND2

VREF/BIAS

I/P SIGNAL

POLARITY

ADJUST

I/P SIGNAL

POLARITY

ADJUST

I/P SIGNAL

POLARITY

ADJUST

(8)

DGND

WM8190

(4) OEB

+

(13) OP[0]
(14) OP[1]

DATA

M

+

U
X

ADC

+

CONFIGURABLE

I/O

14-

PORT

BIT

SERIAL

CONTROL

INTERFACE

(15) OP[2]
(16) OP[3]
(17) OP[4]
(18) OP[5]
(19) OP[6]
(20) OP[7]/SDO

(9) SEN
(12) SCK
(11) SDI
(6) RLC/ACYC

Advanced Information data sheets contain

preliminary data on new products in the

preproduction phase of development .

Supplementary data will be published at a

later date.

1999 Wolfson Microelectronics Ltd



.

WM8190

Advanced Informati o n

PIN CONFIGURATION ORDERING INFORMATION

RINP

AGND2

DVDD1

OEB

VSMP

RLC/ACYC

MCLK

SEN

DVDD2

SDI

SCK
OP[0]
OP[1]

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

GINP
BINP
VRLC/VBIAS
VRX
VRT
VRB
AGND1
AVDDDGND
OP[7]/SDO
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]

PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 RINP Analogue input
2 AGND2 Supply
3 DVDD1 Supply

4 OEB Digit al i nput
5 VSMP Digital input
6 RLC/ACYC Digital input

7 MCLK Digital i nput

8 DGND Supply

9 SEN Digital input
10 DVDD2 Suppl y
11 S DI Digital input
12 SCK Digit al i nput

Red channel input video.
Analogue ground (0V).
Digital supply (5V) for logic and clock generator. This m ust be operated at the same

potential as AVDD.
Output Hi-Z control, all digi tal outputs disabled when OEB = 1.
Video sample synchronisation pulse.
RLC (active high) selects reset level clamp on a pixel-by-pixel basis – ti e hi gh i f

used on every pixel. ACYC autocycles between R, G, B inputs.
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or

any multiple of 2 thereafter depending on input sample mode).
Digital ground (0V).
Enables the serial interf ace when high.
Digital supply (5V/3. 3V ), all digital I/O pins.
Serial data input.
Serial clock.

DEVICE TEMP. RANGE PACKAGE

XWM8190CDW/V 0 to 70oC 28-pin SOIC

Digital multiplexed output data bus.
ADC output data (d13:d0) and error flags (F) are avail abl e i n three multiplexed

formats as shown, under the control of register bit MUXOP[1:0].
See ‘Output Formats’ description in Device Description section for further detai l s.

8+6-bit 7+7-bit 4+4+4+2-bit

ABABABC D

13 OP[0] Digital output d6 F F F
14 OP[1] Digital output d7 F d7 d0
15 OP[2] Digital output d8 d0 d8 d1
16 OP[3] Digital output d9 d1 d9 d2
17 OP[4] Digital output d10 d2 d10 d3 d10 d6 d2 F
18 OP[5] Digital output d11 d3 d11 d4 d11 d7 d3 F
19 OP[6] Digital output d12 d4 d12 d5 d12 d8 d4 d0
20 OP[7] Digital output d13 d5 d13 d6 d13 d9 d5 d1

Alternatively, pin OP[7] /SDO may be used to output regis ter read-back data when
OEB = 0 and SEN has been pulsed high. S ee Serial Interface descript i on i n Devi ce
Description section for further details.

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PIN NAME TYPE DESCRIPTION

21 AVDD Supply
22 AGND1 Supply
23 VRB Analogue output

24 VRT Analogue output

25 VRX Analogue output

26 VRLC/VBIAS Analogue I/O

27 BINP Analogue input
28 GINP Analogue input

Analogue supply (5V). This must be operated at the same potential as DVDD1.
Analogue ground (0V).
Lower reference voltage.

This pin must be connec ted to AGND via a decoupling capacit or.
Upper reference voltage.

This pin must be connec ted to AGND via a decoupling capacit or.
Input return bias voltage.

This pin must be connec ted to AGND via a decoupling capacit or.
Selectable analogue output volt age f or RLC or single-ended bias reference.

This pin would typically be connected t o A G ND vi a a decoupling capacitor.
VRLC can be externally driven if programmed Hi -Z.

Blue channel input video.
Green channel input video.

WM8190

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are s tres s rat ings only. P erm anent dam age t o the devi ce m ay be c aus ed by cont inuousl y operating at
or beyond these limits. Device functional operating lim its and guaranteed performance s pecifications are gi ven under Electrical
Characteristics at the test conditions s pec i fied

ESD Sensitive Device. Thi s device i s m anufactured on a CMOS proces s. It is t herefore generi cally susc eptible
to damage from excessi ve stati c voltages . Proper ES D precautions mus t be tak en during handling and st orage
of this device.

As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount
assembly. It is anticipat ed as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum -sealed moisture
barrier bags.

CONDITION MIN MAX

Analogue supply voltage: AV DD
Digital supply voltages: DVDD1 − 2
Digital ground: DGND
Analogue grounds: AGND1 − 2
Digital inputs, digit al outputs and digital I/O pins
Analogue inputs (RINP, GINP , BINP)
Other pins
Operating temperature range: T
Storage temperature
Lead temperature (soldering, 10 s ec)
Lead temperature (soldering, 2 mins)

1. GND denotes the voltage of any ground pin.

Notes:

2. AGND1, AGND2 and DGND pins are intended to be operat ed at the same potential. Differential voltages
between these pins will degrade performance.

A

GND - 0.3V GND + 7V
GND - 0.3V GND + 7V
GND - 0.3V GND + 0.3V
GND - 0.3V GND + 0.3V
GND - 0.3V DVDD2 + 0.3V
GND - 0.3V AVDD + 0.3V
GND - 0.3V AVDD + 0.3V

0°C+70

-65°C +150°C

°

C

+260°C
+183°C

RECOMMENDED OPERATING CONDITIONS

CONDITION SYMBOL MIN TYP MAX UNITS

Operating temperature range
Analogue supply voltage
Digital core supply volt age
Digital I/O supply vol tage

5V I/O

3.3V I/O

T

A

AVDD 4.75 5.0 5.25 V
DVDD1 4.75 5.0 5.25 V
DVDD2 4.75 5.0 5.25 V

DVDD2 2.97 3.3 3.63 V

070°C

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WM8190

Advanced Informati o n

ELECTRICAL CHARACTERISTICS

Test Conditions

AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, A G ND = DGND = 0V , T

PARAMETER SYMBOL TEST

CONDITIONS
Overall System Specification (including 14-bit ADC, PGA, Offset and CDS functions)
NO MISSING CODES GUARANTEED

Full-scale input voltage range
(see Note 1)
Input signal limi t s (see Note 2)
Full-scale transition error

V

IN

Max Gain

Min Gain

Gain = 0dB;

PGA[7:0] = 4B(hex)

Zero-scale transition error

Gain = 0dB;

PGA[7:0] = 4B(hex)
Differential non-linearit y
Integral non-linearity

DNL 0.65 LSB

INL 4 LSB

Channel to channel gain matchi ng

References

Upper reference voltage
Lower reference voltage
Input return bias voltage
Diff. reference voltage (VRT-VRB)

VRT 2.85 V
VRB 1.35 V
VRX 0.65 V
V

RTB

Output resistance VRT, V RB , V RX

VRLC/Reset-Level Clamp (RLC)

RLC switching impedance
VRLC short-circuit current
VRLC output resistance
VRLC Hi-Z leakage current

VRLC = 0 to AVDD 1 µA
RLCDAC resolution
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at

V

RLCSTEP

V

RLCSTEP

V

RLCBOT

code 0(hex), RLCDACRNG = 0
RLCDAC output voltage at

V

RLCBOT

code 0(hex), RLCDACRNG = 1
RLCDAC output voltage at

V

RLCTOP

code F(hex) RLCDACRNG, = 0
RLCDAC output voltage at

V

RLCTOP

code F(hex), RLCDACRNG = 1
VRLC deviation

Offset DAC, Monotonicity Guaranteed

Resolution
Differential non-linearit y
Integral non-linearity

DNL 0.1 0.5 LSB

INL 0.25 1 LSB
Step size
Output voltage

Code 00(hex)
Code FF(hex)

Notes:

1.

Full-scale input voltage

2.

Input signal limits

denotes the maximum amplitude of the input si gnal at the specified gain.

are the limits within which t he full-scale input voltage si gnal must lie.

= 0 to 70°C, MCLK = 12MHz unless otherwise stated.

A

MIN TYP MAX UNIT

-50 +50 mV

0.4

4.08

Vp-p
Vp-p

0 AVDD V

20 mV

20 mV

1%

1.5 V
1 Ω

50 Ω

5mA
2 Ω

4bits

0.24 V/step

0.16 V/step

0.40 V

0.25 V

4.20 V

2.85 V

8bits

2.04 mV/step

-260
+260

mV
mV

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Advanced Informati o n

WM8190

Test Conditions

AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, A G ND = DGND = 0V , T

PARAMETER SYMBOL TEST

CONDITIONS

Programmable Gain Amplifier

Resolution
Gain

Max gain, each channel
Min gain, each channel

G

MAX

G

MIN

Gain error, each channel

DIGITAL SPECIFICATIONS
Digital Inputs

High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance

V

IH

V

IL

I

IH

I

IL

C

I

Digital Outputs

High level output voltage
Low level output voltage
High impedance output current

V

OH

V

OL

I

OZ

IOH = 1mA DVDD2 - 0.5 V
IOL = 1mA 0.5 V

Digital IO Pins

Applied high level input voltage
Applied low level input voltage
High level output voltage
Low level output voltage
Low level input current
High level input current
Input capacitance
High impedance output current

V

IH

V

IL

V

OH

V

OL

I

IL

I

IH

C

I

I

OZ

IOH = 1mA DVDD2 - 0.5 V
IOL = 1mA 0.5 V

Supply Currents

Total supply current − active
Total analogue supply current −

I

AVDD

active
Digital core supply current,

DVDD1 − active
Digital I/O supply current,

DVDD2 − active
Supply current − full power down

mode

= 0 to 70°C, MCLK = 12MHz unless otherwise stated.

A

MIN TYP MAX UNIT

8bits

208

−

]0:7[PGA283

7.4 V/V

0.74 V/V
1%

0.8 ∗ DVDD2 V

0.2 ∗ DVDD2 V
1 µA
1 µA

5pF

1 µA

0.8 ∗ DVDD2 V

0.2 ∗ DVDD2 V

1 µA
1 µA

5pF

1 µA

50 mA
47 mA

2mA

1mA

100 µA

V/V

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WM8190

Advanced Informati o n

INPUT VIDEO SAMPLING

t

PER

t

MCLKH

t

MCLKL

MCLK

t

VSMPSU

t

VSMPH

VSMP

INPUT

t

VSUtVH

t

RSUtRH

VIDEO

Figure 1 Input Video Timing

Test Conditions

AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, A G ND = DGND = 0V , T

= 0 to 70°C, MCLK = 12MHz unless otherwise stated

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

MCLK period
MCLK high period
MCLK low period
VSMP set-up time
VSMP hold time
Video level set-up tim e
Video level hold time
Reset level set-up time
Reset level hold tim e

Notes:

1. t

VSU

and t

denote the set-up time requi red af ter the input video signal has set tled.

RSU

t

PER

t

MCLKH

t

MCLKL

t

VSMPSU

t

VSMPH

t

VSU

t

VH

t

RSU

t

RH

83.3 ns

37.5 ns

37.5 ns
10 ns

5ns

15 ns

5ns

15 ns

5ns

2. Parameters are measured at 50% of the risi ng/falling edge.

OUTPUT DATA TIMIN G

MCLK

OP[7:0]

Figure 2 Output Data Timing

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PD

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Advanced Informati o n

OEB

WM8190

OP[7:0]

Hi-Z

t

PZE

t

PEZ

Hi-Z

Figure 3 Output Data Enable Timing

Test Conditions

AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, A G ND = DGND = 0V , T

= 0 to 70°C, MCLK = 12MHz unless otherwise stated

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Output propagation delay t
Output enable time t
Output disable time t

PD
PZE
PEZ

I

OH

= 1mA, I

= 1mA 75

OL

50
25

SERIAL INTERFACE

SCK

SDI

t

SSU

t

SPER

t

SH

t

SCKLtSCKH

t

SCE

t

SEWtSEC

ns
ns
ns

SEN

t

SERD

t

SCRD

t

SCRDZ

ADC DATA

SDO

MSB LSB

REGISTER DATA

Figure 4 Serial Interface Timing

Test Conditions

AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, A G ND = DGND = 0V , T

= 0 to 70°C, MCLK = 12MHz unless otherwise stated

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP M AX UNITS

SCK period
SCK high
SCK low t
SDI set-up time
SDI hold time
SCK to SEN set-up time
SEN to SCK set-up time
SEN pulse width
SEN low to SDO = Register data
SCK low to SDO = Register data
SCK low to SDO = ADC data

Parameters are meas ured at 50% of the rising/falli ng edge

Note:

t

SPER

t

SCKH

SCKL

t

SSU

t

SH

t

SCE

t

SEC

t

SEW

t

SERD

t

SCRD

t

SCRDZ

83.3 ns

37.5 ns

37.5 ns
10 ns
10 ns
20 ns
20 ns
50 ns

35 ns
35 ns
25 ns

ADC

DATA

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WM8190

Advanced Informati o n

TYPICAL OVERALL SYSTEM PERFORMANCE
DNL VS CODES

2

1.5

1

0.5

0

DNL (LSB)

-0.5

-1

-1.5

-2
0 1024 2048 3072 4096 5120 6144 7168 8192 9216 10240 11264 12288 13312 14336 15360

Figure 5 DNL Vs Output Data Codes

Output Data Code

INL vs CODES

16
14
12
10

8
6
4
2
0

INL (LSB)

-2

-4

-6

-8

-10

-12

-14

-16
0 1024 2048 3072 4096 5120 6144 7168 8192 9216 10240 11264 12288 13312 14336 15360

Output Data Code

Figure 6 INL Vs Output Data Codes

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Advanced Informati o n

DEVICE DESCRIPTION

INTRODUCTION

A block diagram of t he devi ce showing the signal path is presented on P age 1.
The WM8190 samples up to three inputs (RINP, GINP and BINP) simultaneous ly. The device then

processes the sam pled video signal with respect to the video res et level or an internally/externally
generated reference level using either one or t hree processing channels.

Each processing channel consis ts of an Input Sampling block with optional Reset Level Clamping
(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit
Programmable Gain Amplifier (PGA).

The ADC then converts each resulting analogue signal to a 14-bit digital word. The digital output f rom
the ADC is presented on an 8-bit wide bi-direc tional bus, with optional 8+6-bit , 7+7-bit or 4+4+4+2-bi t
multiplexed formats.

On-chip control registers determine t he configuration of the device, including t he offsets and gains
applied to each channel. These regis ters are programmable via a seri al i nt erface.

INPUT SAMPLING

The WM8190 can sample and process one to three inputs t hrough one or three proces sing channel s
as follows:

WM8190

Colour Pixel-by-Pixel:

each pixel and a separate channel processes each input. The signals are then m ultiplexed into the
ADC, which converts all three inputs within the pixel period.

Monochrome:

corresponding channel, and converted by t he ADC. The choic e of i nput and channel c an be c hanged
via the control interface, e.g. on a line-by-line basis if requi red.

Colour Line-by-Line:

the red channel for processing before being converted by the ADC. The input selected can be
switched in turn (RINP → GINP → BINP → RINP…) together with the PGA and Offset DA C control
registers by pulsing the RLC/A CYC pin. This is known as auto-c ycling. Alt ernatively, other sampling
sequences can be generated via the control registers. This mode causes the blue and green
channels to be powered down. Refer to the Line-by-Line Operation s ec tion for more details.

A single chosen input (RINP, GINP, or BINP) is sampled, processed by the

RESET LEVEL CLAMPING (RLC)

To ensure that the signal applied to the W M8190 lies within its input range (0V to AVDD) the CCD
output signal is usuall y level shi ft ed by coupl ing through a c apac itor, C
WM8190 side of this capacitor to a suitable vol tage during the CCD reset period.

A typical input configurat ion is shown in Figure 7. A clam p pulse, CL, is generated from MCLK and
VSMP by the Timing Control B lock. When CL is ac tive the voltage on the WM8190 si de of C
RINP, is forced t o the VRLC/VBIAS volt age (V
voltage at RINP initi ally remains at V
to video level) will couple through C

RLC is compatible wit h both CDS and non-CDS operating m odes, as sele cted by switch 2. Refer to
the CDS/non-CDS Process ing section.

The three inputs (RINP, GINP and BINP) are s imultaneously sampled for

A single chosen input (RINP, GINP , or BINP) is sampled and m ultiplexed into

The RLC circuit clam ps the

IN.

, at

) by switch 1. When the CL pulse turns off, the

VRLC

but any subsequent variation in sensor voltage (from res et

VRLC

to RINP.

IN

IN

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WM8190

Advanced Informati o n

MCLK VSMP

TIMING CONTROL

R

S

S/H

CDS

4-BIT

RLC DAC

VRLCEXT

S/H

V

S

+

+

-

INPUT SAMPLING
BLOCK FOR RED

CHANNEL

FROM CONTROL
INTERFACE

TO OFFSET DAC

FROM CONTROL
INTERFACE

C

IN

RINP

EXTERNAL VRLC

VRLC/

VBIAS

RLC/ACYC

CL

2

1

RLC CDS

Figure 7 Reset Level Clamping and CDS Circuitry

If auto-cycling is not required, RLC can be s elected by pin RLC/ACYC. Figure 8 illustrates control of
RLC for a typical CCD waveform, with CL appl ied during the reset period.

The input signal applied to the RLC pin i s sampl ed on the positive edge of MCLK that occurs during
each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal
CL pulse on the next reset level. The position of CL can be adjusted by using control bits
CDSREF[1:0] (Figure 9).

If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit
RLCINT determines whether clamping is applied.

MCLK

VSMP

RLC/ACYC

(CDSREF = 01)

INPUT VIDEO

Figure 8 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL

The VRLC/VBIAS pin c an be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the V RLC/VBIAS pin can be driven externally by writing to cont rol bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.

CDS/NON-CDS PROCESSING

For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video l evel is proces sed with res pect to t he video res et
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS m ust
be set to 1 (default), this controls switc h 2 (Figure 7) and causes the si gnal reference t o come from
the video reset level. The ti me at which the reset l evel is sampled, by clock R
programming control bi t s CDSREF[1:0], as shown in Figure 9.

1X X 0X X 0

Programmable Delay

CL

RGB RGB

No RLC on this PixelRLC on this Pixel

/CL, is adjustable by

s

RGB

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]

MCLK

VSMP

VS

R

/CL (CDSREF = 00)

S

/CL (CDSREF = 01)

R

S

/CL (CDSREF = 10)

R

S

/CL (CDSREF = 11)

R

S

Figure 9 Reset Sample and Clamp Timing

For CIS type sensor signals, non-CDS process ing is used. I n this cas e, the video l evel is processed
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described
above. The VRLC/VBIAS pin i s s am pled by R
mode.

OFFSET ADJUST AND PROGRAMMABLE GAIN

The output from the CDS bloc k is a di fferenti al signal, which is added to the output of an 8-bit Offset
DAC to compensate f or offsets and then amplified by an 8-bit PGA . The gain and offset for each
channel are independently programmabl e by writi ng t o control bits DAC[7:0] and PGA[7:0].

WM8190

at the same tim e as Vs samples the video le vel in t his

s

In colour line-by-line mode t he gai n and of fset coefficient s for each colour can be multiplexed in order
(Red → Green → Blue → Red…) by pulsing the ACYC/RLC pin, or controlled via the FME,
ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation secti on for more details.

ADC INPUT BLACK LEVEL ADJUST

The output from the PGA must be offset to match the ful l -scale range of the ADC. For negative-going
input signals, a black level (zero differential) output from the PGA shoul d be offset to the top of the
ADC range. For positive going input signal the blac k level should be of fset to t he bottom of the ADC
range. This is achieved by writing to c ontrol bits PGAFS[1: 0] .

OVERALL SIGNAL FLOW SUMMARY

Figure 10 represents the processi ng of the video signal through the WM8190.

INPUT

SAMPLING

BLOCK

CDS = 1

RLC
DAC

+

-

RLCEXT=0

V

RLCSTEP

V

IN

V

RESET

CDS = 0

V

VRLC

RLCEXT=1

OFFSET DAC

BLOCK

V

1

*RLCV[3:0] + V

V

+

+

A = 208/(283-PGA[7:0])

Offset

DAC

PGA

BLOCK

V

X

PGA gain

3

analog

2

260mV*(DAC[7:0]-127.5)/127.5

RLCBOT

x (16383/VFS)

+0 if PGAFS[1:0]=11

+16383 if PGAFS[1:0]=10

+8191 if PGAFS[1:0]=0x

OUTPUT

INVERT

ADC BLOCK

is RINP or GINP or BINP

V

IN

V

RESET

V

VRLC

CDS, RLCEXT,RLCV[3:0], DAC[7:0],
PGA[7:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS=1 for CDS, 0 for non-CDS

BLOCK

D

1

digital

D2 = D1 if INVOP = 0
D2 = 16383-D1 if INVOP = 1

is VIN sampled during reset clamp

is voltage applied to VRLC pin

TO MULTI­PLEXER FOR
8-BIT OUTPUT

D

2

OP[13:0

Figure 10 Overall Signal Flow

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WM8190

Advanced Informati o n

The

INPUT SAMPLING BLOCK

difference between the input video level V
difference between the input video level V

produces an effective input voltage

and the input reset level V

IN

and the voltage on the VRLC/VBIAS pin, V

IN

RESET

. For CDS, this is the

V

1

. For non-CDS this is the

VRLC

optionally set via the RLC DAC.

,

The

OFFSET DAC BLOCK

then adds the amount of f ine offset adjustment required to m ove the

black level of the input s i gnal towards 0V, producing
The

PGA BLOCK

outputting voltage
The

ADC BLOCK

then amplifies the white level of the input signal to maximise the ADC range,

.

V

3

then converts the analogue signal,

The digital output is then inverted, if required, through the

CALCULATING OUTPUT FOR ANY GIVEN INPUT

The following equations describe the proc essing of the video and reset level signals through
the WM8190.

INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING

If CDS = 1, (i.e. CDS operati on) the previously sampled reset l evel, V
input video.

=VIN - V

V

1

If CDS = 0, (non-CDS operation) the simultaneously sampl ed voltage on pin VRLC is subtracted
instead.

=VIN - V

V

1

If RLCEXT = 1, V
If RLCEXT = 0, V

V

VRLC

is an externally applied voltage on pin VRLC/VB IAS.

VRLC

is the output from the internal RLC DAC.

VRLC

=(V

RLCSTEP

................................................................... Eqn. 1

RESET

..................................................................... Eqn. 2

VRLC

∗ RLCV[3:0]) + V

.

V

2

, to a 14-bit unsigned digital output,

V

3

OUTPUT INVERT BLOCK

, is subtracted from the

RESET

................................. Eqn. 3

RLCBOT

.

D

1

to produce

D

2.

V

is the step size of t he RLC DAC and V

RLCSTEP

is the minimum output of the RLC DAC.

RLCBOT

OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST

The resultant signal

V

2

is added to the Offset DA C output.

V

1

=

+ {260mV ∗ (DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4

V

1

PGA NODE: GAIN ADJUST

The signal is then mult i pl i ed by the PGA gain,

=

V

3

∗ 208/(283- PGA[7:0]) ............................................... Eqn. 5

V

2

ADC BLOCK: ANALOGUE-DIGITAL CONVERSION

The analogue signal is then converted to a 14-bit unsigned number, with input range confi gured by
PGAFS[1:0].

[13:0] = INT{ (

D

1

[13:0] = INT{ (

D

1

[13:0] = INT{ (

D

1

where the ADC full-scale range, V

/VFS) ∗ 16383} + 8191 PGAFS[1:0] = 00 or 01 ...... Eqn. 6

V

3

/VFS) ∗ 16383} PGAFS[1:0] = 11 ............... Eqn. 7

V

3

/VFS) ∗ 16383} + 16383 PGAFS[1:0] = 10 ............... Eqn. 8

V

3

= 3V

FS

OUTPUT INVERT BLOCK: POLARITY ADJUST

The polarity of the digital output may be inverted by control bit I NVOP.

[13:0] =

D

2

[13:0] = 16383 –

D

2

[13:0] (INVOP = 0) ....................... Eqn. 9

D

1

[13:0] (INVOP = 1) ....................... Eqn. 10

D

1

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AI Rev 3.0 August 1999

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Advanced Informati o n

OUTPUT FORMATS

WM8190

The digital data output from t he ADC is available t o the user in 8/7/ 4-bit wide multi plexed formats by
setting control bits MUXOP[1:0]. Lat ency of vali d output data with res pect t o VS MP is program mable
by writing to control bits DEL[1:0]. The latency for each m ode is shown in the Operat ing Mode Tim ing
Diagrams secti on.

Figure 11 shows the output data form ats for Modes 1 – 2 and 4 – 6. Figure 12 shows the out put data
formats for Mode 3. Table 1 summarises the output data obtained for each format .

MCLK

8+6 AND 7+7-BIT

OUTPUT

4+4+4+2-BIT

OUTPUT

AB

ABCD

Figure 11 Output Data Formats (Modes 1

8+6 AND 7+7-BIT

−

Figure 12 Output Data Formats (Mode 3)

MCLK

OUTPUT

4+4+4+2-BIT

OUTPUT

2, 4 − 6)

OUTPUT

FORMAT

8+6-bit

multiplexed

7+7-bit 10 OP[7:0]

MUXOP[1:0] OUTPUT

PINS

0X OP[7:0]

A = d13, d12, d11, d10, d9, d8, d7, d6, d5
B = d4, d3, d2, d1, d0, CC, OVRNG

A = d13, d12, d11, d10, d9, d8, d7, CC
B = d6, d5, d4, d3, d2, d1, d0, OV RNG

4+4+4+2-bit

(nibble)

11 OP[7:4]

A = d13, d12, d11, d10
B = d9, d8, d7, d6
C = d5, d4, d3, d2
D = d1, d0, CC, OVRNG

Table 1 Details of Output Data Shown in Figure 11 and Figure 12.

FLAGS

The following flags are output during m ul tiplexed modes:

AB

AB C DAB

OUTPUT

CC can be used in colour modes 1 and 5 t o identify the green channel output, from which t he blue
and red data can be identified.

INPUT CC

RINP
GINP
BINP

Table 2 Input Sampled Flags CC[1:0]

OVRNG indicates that t he current output data was produced by an input signal that exceeded the
input range limit of t he devi ce. 1 = out of range, 0 = within range.

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0
1
0

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WM8190

Advanced Informati o n

CONTROL INTERFACE

The internal control registers are programmable via the serial digital c ontrol interface. The regis ter
contents can be read back via the serial interface on pin OP[ 7] /SDO.

SERIAL INTERFACE: REGISTER WRITE

Figure 13 shows register writing in serial mode. Three pins , SCK, SDI and SEN are used. A six-bit
address (a5, 0, a3, a2, a1, a0) is c locked in through SDI, MSB first, f ollowed by an eight-bit data
word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK.
When the data has been s hifted i nto the devic e, a pulse i s applied to S EN to transf er the data t o the
appropriate internal register. Not e al l val i d regi sters have address bit a4 equal to 0 in write mode.

SCK

SDI

SEN

Figure 13 Serial Interface Register W rite

a5 0 a3a2a1a0b7b6b5b4b3b2b1b0

Address Data Word

SERIAL INTERFACE: REGISTER READ-BACK

Figure 14 shows register read-back in serial mode. Read-bac k is init iated by writing to the s erial bus
as described above but with address bit a4 set to 1, f ollowed by an 8-bit dummy dat a word. W riting
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on t he falling edge
of SCK). Note that pin SDO i s shared with an output pin, OP[7] , therefore OEB should always be
held low when register read-back data is expected on this pin. The next word m ay be read in to SDI
while the previous word is still being output on SDO.

SCK

SDI

SEN

SDO/

OP[7]

a51a3a2a1a0xxxxxxxx

Address Data Word

d7 d6 d5 d4 d3 d2 d1 d0

Output Data Word

OEB

Figure 14 Serial Interface Register Read-back

TIMING REQUIREMENTS

To use this device a master clock (MCLK) of up to 12MHz and a per-pixel synchronisation clock
(VSMP) of up to 6MHz are required. These clocks drive a timing control block, which produces
internal signals to control the sampling of the video s ignal. MCLK to VSMP ratios and m aximum
sample rates for the vari ous modes are shown in Table 5.

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PROGRAMMABLE VSMP DETECT CIRCUIT

The VSMP input is used to determine the sampling point and frequency of the WM8190. Under
normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling
frequency (as shown in the Operating Mode Timing Diagrams) and t he input sam ple will be tak en on
the first rising MCLK edge aft er VSMP has gone low. However, in certain appl ications suc h a signal
may not be readily available. The programmable VSMP detect circuit in the WM8190 allows the
sampling point to be derived f rom any signal of the c orrect frequency, such as a CCD shift regi ster
clock, when applied to the VSMP pi n.

When enabled, by setting the VSMPDET control bit, the circuit detects either a risi ng or falling edge
(determined by POSNNEG cont rol bi t) on the VSMP input pin and generates an int ernal V SMP pulse.
This pulse can optionally be delayed by a number of MCLK periods, speci fied by the VDEL[ 2:0] bits .
Figure 15 shows the internal VSMP pulses that can be generated by this circuit for a typical clock
input signal. The internal VSMP pulse is then applied to the timing control block in place of the
normal VSMP pulse provided from the input pin. The sampling poi nt then occurs on the first rising
MCLK edge after this internal VS MP pul se, as shown in the Operating Mode Timing Diagrams.

WM8190

REFERENCES

INPUT

(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP

(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP

MCLK

PINS

VSMP

POSNNEG = 1

POSNNEG = 0

Figure 15 Internal VSMP Pul ses Generated by Programmable VSMP Detect Circuit

The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins
VRT and VRB, where they must be decoupl ed to ground. Pin VRX is driven by a s imilar buf fer, and
also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin
VRLC/VBIAS

POWER SUPPLY

The WM8190 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface)
supplies.

POWER MANAGEMENT

Power management for the devic e i s performed via the Control Interf ac e. The device can be powered
on or off completely by the EN bit. Al ternat ively, when control bit SE LPD is high, only bl o cks selected
by further control bits (SELDIS[3:0]) are powered down. This allows the user to optimise power
dissipation in certain modes, or to define an interm ediate standby mode t o allow a quicker recovery
into a fully active stat e. I n Line-by-l ine operati on, t he green and blue c hannel PGA s are autom at ic ally
powered down.

All the internal registers maintain their previous ly programmed value in power down modes and the
Control Interface inputs remain active. Table 3 summarises the power down control bit func tions.

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WM8190

Advanced Informati o n

EN SELDPD

00
10

X1

Table 3 Power Down Control

LINE-BY-LINE OPERATION

Certain linear sensors (e.g. Contact I mage Sensors) gi ve colour output on a line-by-line bas is. i.e. a
full line of red pixels followed by a line of green pixels f ollowed by a line of blue pixels. In order to
accommodate t his type of signal the WM8190 can be set into Monochrome mode, with t he input
channel switched by writing to control bits CHA N[1:0] bet ween every line. Alternat ively, the W M8190
can be placed into colour line-by-line mode by setting the LINEBYLINE cont rol bit. When this bit is
set the green and blue processing c hannels are powered down and the device i s forced internally to
only operate in MONO mode (because only one col our i s sampled at a time) t hrough the red channel.
Figure 16 shows the signal path when operating in colour li ne-by-l i ne mode.

RINP

GINP

BINP

RLC

RLC

RLC

RLC
DAC

4

INPUT

MUX

Device completel y powers down.
Device completel y powers up.
Blocks with respective SELDIS[3:0] bit high are disabled.

VSMP MCLKVRLC/VBIAS

TIMING CONTROLCL VSR

S

CDS

R
G
B

R
G
B

OFFSET

MUX

PGA

MUX

8

OFFSET
DAC

14-

PGA

+

8

I/P SIGNAL

POLARITY

ADJUST

BIT

+

ADC

CONFIGURABLE

INTERFACE

WM8190

DATA

PORT

SERIAL

CONTROL

I/O

OP[7:0]

SEN
SCK
SDI
RLC/ACYC

Figure 16 Signal Path When in Line-by-Line Mode

In this mode the input multiplexer and (optionally) t he PGA/Offset register multiplexers c an be auto­cycled by the application of pulses to t he RLC/A CYC input pin by s ett ing the A CYCNRLC regi st er bit.
The multiplexers change on the firs t MCLK rising edge after RLC/ACY C is tak en high. Alt ernatively,
all three multiplexers can be controlled via the serial int erface by writing to regist er bits INTM[1:0] t o
select the desired colour. It is al so possible f or the input m ultiplexer to be c ontrolled separat ely from
the PGA and Offset multiplexers. Table 4 describes all the multiplexer selection modes that are
possible.

FME ACYCNRLC NAME DESCRIPTION

00

01

10

Internal,
no force mux

Auto-cycling,
no force mux

Internal,
force mux

Input mux, offset and gain regi sters determined by
internal register bits INTM1, INTM0.

Input mux, offset and gain regi sters auto-cycled, RINP
→ GINP → BINP → RINP… on RLC/ACYC pulse.

Input mux selected from i nt ernal regi s ter bits FM1, FM0;
Offset and gain registers selected from internal regi s ter

bits INTM1, INTM0.

11

Auto-cycling,
force mux

Input mux selected from i nt ernal regi s ter bits FM1, FM0;
Offset and gain registers auto-cycled, RINP → GINP →

BINP → RINP… on RLC/ACYC pulse.

Table 4 Colour Selection Description in Line-by-Line Mode

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Advanced Informati o n

OPERATING MODES

WM8190

Table 5 summarises the m os t c om m onl y used m odes , t he cl ock waveforms required and t he regis ter
contents required for CDS and non-CDS operat i on.

MODE DESCRIPTION CDS

Colour

1

Pixel-by-Pixel

Monochrome/

2

Colour
Line-by-Line

Fast

3

Monochrome/
Colour
Line-by-Line

Maximum

4

speed
Monochrome/
Colour
Line-by-Line

Slow Colour

5

Pixel-by-Pixel

Slow

6

Monochrome/
Colour
Line-by-Line

Table 5 WM8190 Operating Modes

AVAILABLE

Yes 2MSPS

Yes 2MSPS

Yes 4MSPS

Yes 1.5MSPS

Yes 1.5MSPS

MAX

SAMPLE

RATE

No 6MSPS

SENSOR

INTERFACE

DESCRIPTION

The 3 input channels
are sampled in
parallel. The signal is
then gain and offset
adjusted before being
multiplexed into a
single data stream
and converted by the
ADC, giving an output
data rate of 6MSPS
max.

As mode 1 except:
Only one input
channel at a time
is continuously
sampled.

Identical to mode 2 MCLK max

Identical to mode 2 MCLK max

Identical to mode 1 MCLK max

Identical to mode 2 MCLK max

TIMING

REQUIRE-

MENTS

MCLK max
= 12MHz

MCLK:
VSMP
ratio is 6:1

MCLK max
= 12MHz

MCLK:
VSMP
ratio is 6:1

= 12MHz
MCLK:

VSMP
ratio is 3:1

= 12MHz
MCLK:

VSMP
ratio is 2:1

= 12MHz
MCLK:

VSMP
ratio is
2n:1, n ≥ 4

= 12MHz
MCLK:

VSMP
ratio is
2n:1, n ≥ 4

REGISTER

CONTENTS

WITH CDS

SetReg1:
03(hex)

SetReg1:
07(hex)

Identical to
mode 2 plus
SetReg3:
bits 5:4 must
be set to
0(hex)

CDS not
possible

Identical to
mode 1

Identical to
mode 2

REGISTER

CONTENTS

WITHOUT

CDS

SetReg1:
01(hex)

SetReg1:
05(hex)

Identical to
mode 2

SetReg1:
45(hex)

Identical to
mode 1

Identical to
mode 2

1. In Monochrome mode, SetReg3 bits 7:6 determine which input is to be sam pl ed.

Notes:

2. For Colour Line-by-Line, set control bit LINEBYLINE. For input selec tion, refer to Table 4, Colour Selection
Description in Line-by-Line Mode.

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WM8190

Advanced Informati o n

OPERATING MODE TIMING DIAGRAMS

The following diagrams show 8+6/7+7 mult iplexed output data and MCLK, VSMP and input video
requirements for operation of the most comm only used modes as shown in Table 5. The diagrams
are identical for both CDS and non-CDS operat ion. Outputs from RINP, GINP and BINP are s hown
as R, G and B respectively. X denotes i nval i d data.

16.5 MCLK PERIODS

MCLK

VSMP

INPUT VIDEO

OP[7:0]

(DEL = 00)

OP[7:0]

(DEL = 01)

OP[7:0]

(DEL = 10)

OP[7:0]

(DEL = 11)

RARBGAGBBABBRARBGAGBBABBRARBGAGBBAB

BABBRARBGAGBBABBRARBGAGBBABBRARBGAG

GAGBBABBRARBGAGBBABBRARBGAGBBABBRAR

RARBGAGBBABBRARBGAGBBABBRARBGBGABAB

Figure 17 Mode 1 Operation

MCLK

VSMP

INPUT VIDEO

OP[7:0] (DEL = 00)

OP[7:0] (DEL = 01)

OP[7:0] (DEL = 10)

RAR

X X

X X

RARBGAGBBAB

B

BABBRARBGAG

B

GAGBBABBRAR

B

RARBGAGBBAB

B

B

B

B

B

RAR

BAB

GAG

RAR

B

RARBGAG

B

BAB

B

B

GAGBBAB

B

RAR

B

B

B

B

GAGBBAB

16.5 MCLK PERIODS

X X

RAR

RAR

X X X X

B

RAR

X X

X X

B

B

X X

X

X X X

B

RAR

B

X

X

X X

RAR

B

RAR

X X

X X

X X X X

B

RAR

X X

B

X X

RAR

RAR

X X X X

B

RAR

X X

X X

B

B

X X

X X

RAR

RAR

B

X X

X X

B

RAR

X

OP[7:0] (DEL = 11)

B

Figure 18 Mode 2 Operation

WOLFSON MICROELECTRONICS LTD

X X X

RAR

X X X X

B

RAR

X X X X

B

RAR

X X X X

B

RAR

B

AI Rev 3.0 August 1999

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Advanced Informati o n

MCLK

VSMP

INPUT VIDEO

WM8190

23.5 MCLK PERIODS

OP[7:0]

(DEL = 00)

OP[7:0]

(DEL = 01)

OP[7:0]

(DEL = 10)

OP[7:0]

(DEL = 11)

RBRARBRARBRARBRARBRARBRARBRARBRARBRAR

RBRARBRARBRARBRARBRARBRARBRARBRAR

RBRARBRARBRARBRARBRARBRARBRARBRARBRAR

RBRARBRARBRARBRARBRARBRARBRARBRARBRAR

Figure 19 Mode 3 Operation

MCLK

VSMP

INPUT VIDEO

OP[7:0]

(DEL = 00)

OP[7:0]

(DEL = 01)

OP[7:0]

(DEL = 10)

OP[7:0]

(DEL = 11)

RARBRARBRARBRARBRARBRARBRARBRARBRARBRARBRAR

RARBRARBRARBRARBRARBRARBRARBRARBRARBRARBRAR

RARBRARBRARBRARBRARBRARBRARBRARBRAR

RARBRARBRARBRARBRARBRARBRARBRARBRAR

16.5 MCLK PERIODS

RARBRAR

B

RAR

B

RAR

B

RAR

B

RAR

B

RAR

B

B

B

RAR

RAR

RAR

B

RAR

B

RAR

B

RAR

B

RAR

B

RAR

B

RAR

B

RARBRAR

B

RAR

B

B

B

B

B

B

B

RAR

RAR

RAR

RAR

RAR

RAR

B

B

B

B

B

B

B

B

Figure 20 Mode 4 Operation

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WM8190

Advanced Informati o n

16.5 MCLK PERIODS

MCLK

VSMP

INPUT

VIDEO

OP[7:0]

(DEL = 00)

OP[7:0]

(DEL = 01)

OP[7:0]

(DEL = 10)

OP[7:0]

(DEL = 11)

RARBGAGBBAB

X X

BAB

B

GAGBBAB

RARBGAGBBAB

RARBGAGBBAB

X X

X X

B

X X

B

RARBGAGBBAB

RARBGAGBBAB

X X

B

RARBGAGBBAB

X X

B

Figure 21 Mode 5 Operation (MCLK:VSMP Ratio = 8:1)

16.5 MCLK PERIODS

RARBGAGBBAB

RARBGAGBBAB

X X

B

X X

B

RARBGAGBBAB

X X

B

X X

B

B

RARBGAGBBAB

X X

B

RARBGAGBBAB

RARBGAGBBAB

X X

RARBGAGBBAB

X X

B

RARBGAG

X X

B

B

RAR

X X

B

B

B

MCLK

VSMP

INPUT VIDEO

OP[7:0]

(DEL = 00)

OP[7:0]

(DEL = 01)

OP[7:0]

(DEL = 10)

OP[7:0]

(DEL = 11)

RAR

X X

X X

X X

RAR

B

X X X X X X

B

RAR

X X X X X X

X X

X X

X X X X

B

RAR

X X X X X X X X

X X X X X X X X X X X X

B

RAR

Figure 22 Mode 6 Operation (MCLK:VSMP Ratio = 8:1)

B

RAR

X X

X X

X X X X X X

B

RAR

X X X X

B

RAR

RAR

X X X X X X

B

RAR

X X X X

B

RAR

X X X X

RAR

X X

X X

B

B

B

RAR

B

WOLFSON MICROELECTRONICS LTD

AI Rev 3.0 August 1999

20

Advanced Informati o n

DEVICE CONFIGURATION

REGISTER MAP

The following table describes the location of each cont rol bit used to determ ine the operation of the
WM8190. The register map is programmed by writing the required codes to the appropriate
addresses via the serial interface.

WM8190

DESCRIPTION DEF

<a5:a0>

000001 Setup Reg 1 03 RW MODE4 PGAFS[1] PGAFS[0] SELPD MONO CDS EN
000010 Setup Reg 2 20 RW DEL[1] DEL[0] RLCDACRNG 0 VRLCEXT INVOP MUXOP[1] MUXOP[0]
000011 Setup Reg 3 1F RW CHAN[1] CHAN[0] CDSREF [1] CDSREF [0] RLCV[3] RLCV[2] RLCV[1] RLCV[0]
000100 Software Reset 00 W
000101 Auto-cycle Reset 00 W
000110 Setup Reg 4 00 RW FM[1] FM[0] INTM[1] INTM[0] RLCINT FME ACYCNRLC LINEBYLINE
000111 Revision Number 41 R
001000 Setup Reg 5 00 RW 0 0 0 POSNNEG VDEL[2] VDEL[1] VDEL[0] VSMPDET
001001 Setup Reg 6 00 RW 0 0 0 0 SELDIS[3] SELDIS[2] SELDIS[1] SELDIS[0]
001010 Reserved 00 RW 0 0 0 0 0 0 0 0
001011 Reserved 00 RW 0 0 0 0 0 0 0 0
001100 Reserved 00 RW 0 0 0 0 0 0 0 0
100000 DAC Value (Red) 80 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
100001 DAC Value

(Green)
100010 DAC Value (Blue) 80 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
100011 DAC Value (RGB) 80 W DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
101000 PGA Gain (Red) 00 RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]
101001 PGA Gain

(Green)
101010 PGA Gain (Blue) 00 RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]
101011 PGA Gain (RGB) 00 W PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]

RW

(hex)

80 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]

00 RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]

b7 b6 b5 b4 b3 b2 b1 b0

BITADDRESS

Table 6 Register Map

REGISTER MAP DESCRIPTION

The following table describes the f unction of each of the control bi ts shown in Table 7.

REGISTER BIT

Setup
Register 1

NO

0EN 1
1 CDS 1

2MONO 0
3 SELPD 0

5:4 PGAFS[1:0] 00

6MODE4 0

BIT

NAME(S)

DEFAULT DESCRIPTION

Global power down: 0 = complete power down, 1 = fully active.
Select correlated double sampling mode: 0 = single ended mode,

1 = CDS mode.
Mono/colour select: 0 = col our, 1 = monochrome operation.
Selective power down: 0 = no individual control,

1 = individual blocks can be disabled (controlled by SELDIS[3:0]).
Offsets PGA output to optimise the A DC range f or di fferent polarity sensor

output signals. Zero differential PGA input signal gi ves:
00 = Zero output

(use for bipolar video)
01 = Zero output

10 = Full-scale positive output
(use for negative going video)
11 = Full-scale negative output
(use for positive going video)

Required when operating in MODE4: 0 = other modes, 1 = MODE4.

WOLFSON MICROELECTRONICS LTD

AI Rev 3.0 August 1999

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WM8190

Advanced Informati o n

REGISTER BIT

Setup
Register 2

Setup
Register 3

Software
Reset

Auto-cycle
Reset

NO

1:0 MUXOP[1:0] 00

2INVOP 0

3 VRLCEXT 0

5 RLCDACRNG 1

7:6 DEL[1:0] 00

3:0 RLCV[ 3:0] 1111

5:4 CDSRE F[1:0] 01

7:6 CHAN[1:0] 00

BIT

NAME(S)

DEFAULT DESCRIPTION

Determines the output data format.
00 = 8-bit multiplexed (8+6 bits)

01 = 8-bit multiplexed (8+6 bits)

Digitally inverts the pol ari ty of output data.
0 = negative going video gives negative going output,

1 = negative-going video gives positive going out put data.
When set powers down the RLCDAC, c hangi ng i t s output to Hi-Z, allowing

VRLC/VBIAS to be externally driven.
Sets the output range of the RLCDAC.
0 = RLCDAC ranges from 0 to AV DD (approximately),

1 = RLCDAC ranges from 0 to VRT (approximat el y).
Sets the output lat ency in ADC clock periods.
1 ADC clock period = 2 MCLK periods except in Mode 3 where 1 ADC

clock period = 3 MCLK periods.
00 = Minimum latency

01 = Delay by one ADC clock
period

Controls RLCDAC driving VRLC pin to defi ne s i ngl e ended signal
reference voltage or Reset Level Clamp voltage. See Electrical
Characteristics s ection for ranges.

CDS mode reset timing adjust.
00 = Advance 1 MCLK period

01 = Normal
Monochrome mode channel select.
00 = Red channel select

01 = Green channel select
Any write to Software Reset causes all cells to be res et.

Any write to Auto-cycle Reset causes the auto-cycle counter to reset
to RINP.

10 = 7-bit multiplexed mode (7+7 bit s)
11 = 4-bit multiplexed mode (4+4+4+2
bits)

10 = Delay by two ADC clock periods
11 = Delay by three ADC clock
periods

10 = Retard 1 MCLK period
11 = Retard 2 MCLK periods

10 = Blue channel select
11 = Reserved

WOLFSON MICROELECTRONICS LTD

AI Rev 3.0 August 1999

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Advanced Informati o n

WM8190

REGISTER BIT

Setup
Register 4

Setup
Register 5

Setup
Register 6

Table 7 Register Control Bits

NO

5:4 INTM[1:0] 00

7:6 FM[1:0] 00

3:1 VDEL[2:0] 000

3:0 SE LDI S [3:0] 0000

NAME(S)

0 LINEBYLINE 0

1 ACYCNRLC 0

2FME 0

3RLCINT 0

0 VSMPDET 0

4 POSNNEG 0

BIT

DEFAULT DESCRIPTION

Selects line by line operati on 0 = normal operation,
1 = line by line operation.

When line by line operati on i s selected MONO is forced to 1 and
CHAN[1:0] to 00 internally, ens uri ng that the correct internal t i ming signals
are produced. Green and Blue PGAs are als o di sabled to save power.

When LINEBYLINE = 0 this bit has no ef f ec t.
When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC
input pin and the input mult i pl exer and offset/gain register controls.

0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selecti on of
input and gain/offset multiplexers,
1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin.

See Table 4, Colour Selection Des cription in Line-by-Line Mode for colour
selection mode detail s.

When auto-cycli ng i s enabled, the RLC/ACYC pin cannot be us ed f or
reset level clamping. The RLCINT bit may be used instead.

When LINEBYLINE = 0 this bit has no ef f ec t.
When LINEBYLINE = 1 this bit c ont rols t he input force mux mode:

0 = No force mux, 1 = Force mux mode. Forces the input mux to be
selected by FM[1:0] separatel y from gain and offset m ul tiplexers.

See Table 4 for details.
When LINEBYLINE = 1 and ACYCNRLC = 1 this bit i s used to determine

whether Reset Level Clamping is used.
0 = RLC disabled, 1 = RLC enabled.
Colour selection bits us ed i n i nternal modes.
00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.
See Table 4 for details.
Colour selection bits us ed i n i nput force mux modes.
00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.
See Table 4 for details.
0 = Normal operation, signal on V SMP input pin is applied directly t o

Timing Control block.
1 = Programmable VSMP det ect circuit is enabled. An internal

synchronisation pulse is generated from signal applied to VSMP input pin
and is applied to Timing Cont rol bl oc k.

When VSMPDET = 0 t hese bits have no effect.
When VSMPDET = 1 t hese bits set a programmable delay from the
detected edge of the signal appli ed to the VSMP pin. The internally
generated pulse is delayed by VDEL MCLK periods from the detected
edge.

See Figure 15, Internal VSMP Pul ses Generated for details.
When VSMPDET = 0 t hi s bit has no effect.

When VSMPDET = 1 t hi s bit controls whether positive or negat i ve edges
are detected:

0 = Negative edge on VSMP pin is detect ed and used to generate internal
timing pulse.

1 = Positive edge on VSMP pin is det ected and used to generate internal
timing pulse.

See Figure 15 for further details.
Selective power disable register - activated when SELPD = 1.
Each bit disables respective cell when 1, enabled when 0.
SELDIS[0] = Red CDS, PGA

SELDIS[1] = Green CDS, P GA
SELDIS[2] = Blue CDS, PGA
SELDIS[3] = ADC

WOLFSON MICROELECTRONICS LTD

AI Rev 3.0 August 1999

23

WM8190

Advanced Informati o n

RECOMMENDED EXTERNAL COMPONENTS

DVDD

3

DVDD1

10

DVDD2

C2C1

AVDD

21

AVDD

C3

DGND

AGND

1

Video

Inputs

28
27

26

C9

RINP
GINP
BINP

VRLC/VBIAS

WM8190

AGND

7

Timing

Signals

Interface

Controls

MCLK

5

VSMP

6

RLC/ACYC

12

SCK

11

SDI

9

SEN

4

OEB

DGND

AGND1
AGND2

VRT
VRX
VRB

OP[7]/SDO

OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]

8

22

2

AGND

24
25
23

20
19
18
17
16
15
14
13

C6 C8

C7

AGND

Output

Data

Bus

C4 C5

DVDD

C11C10

++ +

DGND AGND

AVDD

C12

C1-9 should be fitted as close to WM8190 as possible.NOTES:

1.
AGND and DGND should be connected as close to WM8190 as possible.

2.
DVDD should be connected as close to WM8190 as possible.3.

Figure 23 External Components Diagram

COMPONENT

REFERENCE

SUGGESTED

VALUE

C1 100nF
C2 100nF
C3 100nF
C4 10nF
C5 1µF
C6 100nF
C7 100nF
C8 100nF

C9 100nF
C10 10µF
C11 10µF
C12 10µF

Table 8 External Components Descriptions

DESCRIPTION

De-coupling for DVDD1.
De-coupling for DVDD2.
De-coupling for AVDD.
High frequency de-coupling between VRT and VRB.
Low frequency de-coupling between VRT and VRB (non-polarised).
De-coupling for VRB.
De-coupling for VRX.
De-coupling for VRT.
De-coupling for VRLC.
Reservoir capacitor for DV DD.
Reservoir capacitor for DV DD.
Reservoir capacitor for A V DD.

WOLFSON MICROELECTRONICS LTD

AI Rev 3.0 August 1999

24

Advanced Informati o n

PACKAGE DIMENSIONS

WM8190

D: 28 PIN SOICW 7.5mm (0.3") Wide Body, 1.27mm Lead Pitch

e

28

ZONE A

ZONE B

1

A

Dimensions

Symbols

(mm)

B

15

E H

14

D

-C-

0.10 (0.004)

Dimensions

(Inches)

MIN MAX MIN MAX
A
A

1

B
C
D
e
E
h
H
L

α

2.35 2.65 0.0926 0.1043

0.10 0.30 0.0040 0.0118

0.33 0.51 0.0130 0.0200

0.23 0.32 0.0091 0.0125

17.70 18.10 0.6969 0.7125

1.27 BSC 0.0500 BSC

7.40 7.60 0.2914 0.2992

0.25 0.75 0.0100 0.0290

10.00 10.65 0.3940 0.4190

0.40 1.27 0.0160 0.0500

o

0

o

8

o

0

o

8

A1

SEATING PLANE

DM016.B

L

o

h x 45

α

C

REF:

NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-013, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
E. PIN ONE INDICATORS WILL BE LOCATED IN EITHER ZONE A OR ZONE B.

JEDEC.95, MS-013

WOLFSON MICROELECTRONICS LTD

AI Rev 3.0 August 1999

25