Datasheet XM28C020PMHR-25, XM28C020PMHR-20, XM28C020PMHR-15, XM28C020PMHR-12, XM28C020PM-25 Datasheet (XICOR)

XM28C020

2 Megabit Module XM28C020 256K x 8 Bit

5 Volt, Byte Alterable E2PROM

TYPICAL FEATURES

• High Density 2 Megabit (256K x 8) Module

• Access Time of 150ns at –55°C to +125°C

• Base Memory Component: Xicor X28C513

• Pinout conforms to JEDEC Standard for

2 Megabit E2PROM

• Fast Write Cycle Times

—128 Byte Page Write
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 10 Seconds

• Early End of Write Detection

DESCRIPTION

The XM28C020 is a high density 2 Megabit E2PROM
comprised of four X28C513 LCCs mounted on a co-fired
multilayered ceramic substrate. Individual components
are 100% tested prior to assembly in module form and
then 100% tested after assembly.

The XM28C020 is configured 256K x 8 bit. The module
supports a 128-byte page write operation. This com­bined with DATA Polling or Toggle Bit Polling, effectively
provides a 39µs/byte write cycle, enabling the entire
array to be rewritten in 10 seconds.

—DATA Polling
—Toggle Bit Polling

• Software Data Protection

The XM28C020 provides the same high endurance and
data retention as the X28C513.

• Three Temperature Ranges

—Commercial: 0°C to +75°C
—Industrial: –40° to +85°C
—Military: –55° to +125°C

• High Rel Module

—100% MIL-STD-883 Compliant Components

• Endurance: 100,000 Cycles

FUNCTIONAL DIAGRAM PIN CONFIGURATION

X28C513

A0–A

15

I/O0–I/O
OE

WE
CE

A0–A

15

I/O0–I/O

© Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice
3872-1.9 6/18/97 T1/C0/D0 SH

OE
WE
CE

A
A

7

16
17

A0–A
I/O0–I/O

OE
WE
CE

7

X28C513

15

7

X28C513

A0–A

15

I/O0–I/O
OE

WE
CE

X28C513

A0–A

15

I/O0–I/O
OE

WE
CE

1

7

7

3872 FHD F01

A
A
A

I/O
I/O
I/O

V

NC

16
15
12

A
A
A
A
A
A
A
A

SS

7
6
5
4
3
2
1
0
0
1
2

1
2
3
4
5
6
7
8

XM28C020

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

3872 FHD F02

V
WE
A
A
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/0
I/O

CC

17
14
13
8
9
11

10

7
6
5

4

3

XM28C020

PIN DESCRIPTIONS
Addresses (A0–A17)

The Address inputs select an 8-bit memory location
during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced (see Note 4).

Output Enable (OE)

The Output Enable input controls the data output buffers
and is used to initiate read operations.

Data In/Data Out (I/O0–I/O7)

Data is written to or read from the XM28C020 through
the I/O pins.

Write Enable (WE)

The Write Enable input controls the writing of data to the
XM28C020.

PIN NAMES

Symbol Description

A0–A

17

I/O0–I/O

7

Address Inputs
Data Input/Output

WE Write Enable
CE Chip Enable
OE Output Enable

V

CC

V

SS

+5V
Ground

NC No Connect

3872 PGM T01

2

XM28C020

DEVICE OPERATION
Read

Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This 2-line control architecture elimi­nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.

Write

Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The XM28C020 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, which­ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
5ms (see Note 4).

Page Write Operation

The page write feature of the XM28C020 allows the
entire memory to be written in 10 seconds. Page write
allows two to 128 bytes of data to be consecutively
written to the XM28C020 prior to the commencement of
the internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A7 through A17) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.

The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to 127 bytes in the same
manner as the first byte was written. Each successive
byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page

write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.

Write Operation Status Bits

The XM28C020 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.

Figure 1. Status Bit Assignment

5TBDP 43210I/O

RESERVED
TOGGLE BIT
DATA POLLING

3872 FHD F09

DATA Polling (I/O7)

The XM28C020 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the
XM28C020, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will
produce the complement of that data on I/O7 (i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O7 will reflect true
data. Note: If the XM28C020 is in the protected state and
an illegal write operation is attempted, DATA Polling will
not operate.

Toggle Bit (I/O6)

The XM28C020 also provides another method for deter­mining when the internal write cycle is complete. During
the internal programming cycle I/O6 will toggle from “1”
to “0” and “0” to “1” on subsequent attempts to read the
last byte written. When the internal cycle is complete the
toggling will cease and the device will be accessible for
additional read or write operations.

3

XM28C020

DATA POLLING I/O

7

Figure 2. DATA Polling Bus Sequence

LAST

WRITE

WE

CE

OE

V

A0–A

I/O

IH

7

An An An An An An

17

HIGH Z

Figure 3. DATA Polling Software Flow

WRITE DATA

V

OH

V

OL

An

READY

3872 FHD F10

DATA Polling can effectively halve the time for writing to
the XM28C020. The timing diagram in Figure 2 illus­trates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.

WRITES

COMPLETE?

YES

SAVE LAST DATA

AND ADDRESS

READ LAST

ADDRESS

IO

7

COMPARE?

YES

READY

NO

NO

3872 FHD F11

4

XM28C020

THE TOGGLE BIT I/O

6

Figure 4. Toggle Bit Bus Sequence

LAST

WRITE

WE

CE

OE

I/O

6

* Beginning and ending state of I/O6 will vary.

V

*

Figure 5. Toggle Bit Software Flow

LAST WRITE

LOAD ACCUM

FROM ADDR n

OH

HIGH Z

V

OL

*

READY

3872 FHD F12

The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple XM28C020 memories that is frequently up­dated. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow
diagram in Figure 5 illustrates a method for testing the
Toggle Bit.

COMPARE

ACCUM WITH

ADDR n

COMPARE

OK?

YES

READY

NO

3872 FHD F13

5

XM28C020

HARDWARE DATA PROTECTION

The XM28C020 provides three hardware features that
protect nonvolatile data from inadvertent writes.

• Noise Protection—A WE pulse less than 10ns will not
initiate a write cycle.

• Default VCC Sense—All functions are inhibited when
VCC is ≤ 3V.

• Write Inhibit—Holding OE LOW will prevent an inad­vertent write cycle during power-up and power-down.

SOFTWARE DATA PROTECTION

The XM28C020 does provide the Software Data Protec­tion (SDP) feature.

The module is shipped from Xicor with the Software
Data Protection NOT ENABLED; that is, the module will
be in the standard operating mode. In this mode, data
should be protected during power-up/-down operations
through the use of external circuits. The host system will
then have open read and write access of the module
once VCC is stable.

The module can be automatically protected during power­up/-down without the need for external circuits by em­ploying the SDP feature. The internal SDP circuit is
enabled after the first write operation utilizing the SDP
command sequence.

When this feature is employed, it will be easiest to
incorporate in the system software if the module is
viewed as a subsystem composed of four discrete
memory devices with an address decoder (see Func­tional Diagram). In this manner, system memory map­ping will extend onto the module. That is, the discrete

memory ICs and decoder should be considered memory
board components and SDP can be implemented at the
component level as described in the next section.

SOFTWARE COMMAND SEQUENCE

A16 and A17 are used by the decoder to select one of the
four LCCs. Therefore, only one of the four memory
devices can be accessed at one time. In order to protect
the entire module, the command sequence must be
issued separately to each device.

Enabling the software data protection mode requires the
host system to issue a series of three write operations:
each write operation must conform to the data and
address sequence illustrated in Figures 6 and 7.
Because this involves writing to a nonvolatile bit, the
device will become protected after tWC has elapsed.
After this point in time devices will inhibit inadvertent
write operations.

Once in the protected mode, authorized writes may be
performed by issuing the same command sequence that
enables SDP, immediately followed by the address/data
combination desired. The command sequence opens
the page write window enabling the host to write from
one to 128 bytes of data. Once the data has been
written, the device will automatically be returned to the
protected state.

In order to facilitate testing of the devices the SDP mode
can be deactivated. This is accomplished by issuing a
series of six write operations: each write operation must
conform to the data and address sequence illustrated in
Figures 8 and 9. This is a nonvolatile operation, and the
host will have to wait a minimum tWC before attempting
to write new data.

6

XM28C020

SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write

V

CC
0V

DATA

ADDR.

A0–A15*

CE

WE

*A16 & A17 select one of four devices on the module.

AA

5555

Figure 7. Write Sequence for
Software Data Protection

WRITE DATA AA

TO ADDRESS

5555

WRITE DATA 55

TO ADDRESS

2AAA

55

2AAA

A0

5555

≤t

BLC MAX

(VCC)

WRITES

OK

BYTE

OR

PAGE

t

WC

WRITE
PROTECTED

3872 FHD F14

Regardless of whether the device has previously been
protected or not, once the software data protected
algorithm is used and data has been written, the device
will automatically disable further writes unless another
command is issued to cancel it. If no further commands
are issued the device will be write protected during
power-down and after any subsequent power-up.

WRITE DATA A0

TO ADDRESS

5555

WRITE DATA XX

TO ANY

ADDRESS

WRITE LAST

BYTE TO

LAST ADDRESS

AFTER t

RE-ENTERS DATA

PROTECTED STATE

WC

BYTE/PAGE
LOAD ENABLED

3872 FHD F15

7

XM28C020

RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence

V

CC

DATA

ADDRESS

A0–A15*

CE

WE

*A16 & A17 select one of four devices on the module.

AA

5555

55

2AAA

80

5555

Figure 9. Software Sequence to Deactivate
Software Data Protection

WRITE DATA AA

TO ADDRESS

5555

WRITE DATA 55

TO ADDRESS

2AAA

AA

5555

55

2AAA

20

5555

≥t

WC

STANDARD
OPERATING
MODE

3872 FHD F16

In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algo­rithm will reset the internal protection circuit. After tWC,
the device will be in standard operating mode.

WRITE DATA 80

TO ADDRESS

5555

WRITE DATA AA

TO ADDRESS

5555

WRITE DATA 55

TO ADDRESS

2AAA

WRITE DATA 20

TO ADDRESS

5555

3872 FHD F17

SYMBOL TABLE

WAVEFORM

8

INPUTS

Must be
steady

May change
from LOW
to HIGH

May change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

N/A

OUTPUTS

Will be
steady

Will change
from LOW
to HIGH

Will change
from HIGH
to LOW

Changing:
State Not
Known

Center Line
is High
Impedance

XM28C020

SYSTEM CONSIDERATIONS

Because the XM28C020 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation
and eliminate the possibility of contention where mul­tiple I/O pins share the same bus.

To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.

Because the XM28C020 has two power modes, standby
and active, proper decoupling of the memory array is of

prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre­quency ceramic capacitor be used between VCC and
V

at each device. Depending on the size of the array,

SS

the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic

bulk capacitor be place between VCC and V

for every

SS

two modules employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.

9

XM28C020

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias .................. –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with

Respect to V

................................................ –1V to +7V

SS

D.C. Output Current .............................................5mA

Lead Temperature

(Soldering, 10 seconds).............................. 300°C

*COMMENT

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

D.C. OPERATING CHARACTERISTICS

XM28C020 TA = 0°C to +70°C, VCC = +5V ±10%, unless otherwise specified.
XM28C020I TA = –40°C to +85°C, VCC = +5V ±10%, unless otherwise specified.
XM28C020M TA = –55°C to +125°C, VCC = +5V ±10%, unless otherwise specified.

Limits

Symbol Parameter Min. Max. Units Test Conditions

I

CC

VCC Current (Active) 100 mA CE = OE = VIL, WE = VIH,
(TTL Inputs) All I/O’s = Open, 1 Device Active

Address Inputs = TTL Levels
@ f = 5MHz

I

SB1

VCC Current (Standby) 25 mA CE = VIH, OE = V

IL

(TTL Inputs) All I/O’s = Open, Other Inputs = V

I

SB2

VCC Current (Standby) 5 mA CE = VIH, OE = V

IL

(CMOS Inputs) All I/O’s = Open, Other Inputs = V

I

LI

I

LO

V

lL

V

IH

V

OL

V

OH

Input Leakage Current 20 µAVIN = V
Output Leakage Current 20 µAV

OUT

to V

SS

= VSS to VCC, CE = V
Input LOW Voltage –1 0.8 V
Input HIGH Voltage 2 VCC + 1 V
Output LOW Voltage 0.4 V IOL = 2.1mA
Output HIGH Voltage 2.4 V IOH = –400µA

CC

IH

CC

IH

3856 PGM T02.2

POWER-UP TIMING

Symbol Parameter Typ.

(2)

t

PUR

t

PUW

(2)

Power-up to Initiation of Read Operation 100 µs
Power-up to Initiation of Write Operation 5 ms

(1)

Units

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V

Symbol Parameter Max. Units Test Conditions

(2)

C

I/O

(2)

C

IN

Notes: (1) Typical values are for TA = 25°C and nominal supply voltage.

(2) This parameter is periodically sampled and not 100% tested.

Input/Output Capacitance 50 pF V
Input Capacitance 50 pF V

10

I/O

IN

= 0V

= 0V

3872 PGM T03

3872 PGM T04.1

XM28C020

t

CE

t

RC

ADDRESS

CE

OE

WE

DATA VALID

DATA VALID

t

OE

t

LZ

t

OLZ

t

OH

t

AA

t

HZ

t

OHZ

DATA I/O

V

IH

HIGH Z

A.C. CONDITIONS OF TEST

Input Pulse Levels 0V to 3V
Input Rise and

Fall Times 10ns
Input and Output

Timing Levels 1.5V
Output Load 1 TTL Gate and

CL = 100pF

3872 PGM T05.1

MODE SELECTION

CE OE WE Mode I/O Power

L L H Read D
L H L Write D

OUT
IN

Active

Active
H X X Standby and Write Inhibit High Z Standby
X L X Write Inhibit — —
X X H Write Inhibit — —

3872 PGM T06

A.C. CHARACTERISTICS

XM28C020 TA = 0°C to +75°C, VCC = +5V ±10%, unless otherwise specified.
XM28C020I TA = –40°C to +85°C, VCC = +5V ±10%, unless otherwise specified.
XM28C020M TA = –55°C to +125°C, VCC = +5V ±10%, unless otherwise specified.

Read Cycle Limits

XM28C020-15 XM28C020-20 XM28C020-25

Symbol Parameter Min. Max. Min. Max. Min. Max. Units

t

RC

t

CE

t

AA

t

OE

t

LZ

t

OLZ

t

HZ

t

OHZ

t

OH

Read Cycle Time 150 200 250 ns
Chip Enable Access Time 150 200 250 ns
Address Access Time 150 200 250 ns
Output Enable Access Time 70 80 100 ns

(3)

CE Low to Active Output 0 0 0 ns

(3)

OE Low to Active Output 0 0 0 ns

(4)

CE High to High Z Output 100 100 100 ns

(4)

OE High to High Z Output 100 100 100 ns
Output Hold From Address Change 0 0 0 ns

3872 PGM T07.1

Read Cycle

Note: (3) tLZ and t

(4) tHZ and t

no longer driven.

are shown for reference only, they are periodically characterized and are not 100% tested.

OLZ

are measured from the point when CE or OE return high (whichever occurs first) to the time when the outputs are

OHZ

11

3872 FHD F03

XM28C020

Write Cycle Limits

WE Controlled Write CE Controlled Write

Symbol Parameter Min. Max. Min. Max. Units

t

WC

t

AS

t

AH

t

CS

t

CH

t

CW

t

OES

t

OEH

t

WP

t

WPH

t

DV

t

DS

t

DH

t

DW

t

BLC

Write Cycle Time 10 10 ms
Address Setup Time 0 0 ns
Address Hold Time 125 125 ns
Write Setup Time 25 0 ns
Write Hold Time 0 25 ns

CE Pulse Width 125 100 ns
OE High Setup Time 10 10 ns
OE High Hold Time 10 35 ns
WE Pulse Width 100 125 ns
WE High Recovery 100 100 ns

Data Valid 1 1 µs
Data Setup 50 50 ns
Data Hold 10 35 ns
Delay to Next Write 10 10 µs
Byte Load Cycle 0.3 100 0.3 100 µs

WE Controlled Write Cycle

(4)

3872 PGM T08.1

t

WC

ADDRESS

t

AS

t

CS

CE

OE

WE

DATA IN

DATA OUT

Note: (4) Due to the inclusion of the decoder IC on board the module the WE and CE write controlled timings will vary. When utilizing the

CE controlled write operation all the hold timings must be extended by the worst case propagation delay of the decoder. For a
WE controlled write operation CE must be a minimum 125ns to accommodate the additional setup time required.

t

OES

t

DV

t

AH

t

WP

t

OEH

DATA VALID

t

DS

HIGH Z

t

DH

t

CH

t

WPH

3872 FHD F04

12

XM28C020

CE Controlled Write Cycle

ADDRESS

CE

t

OES

t

AS

t

AH

t

CW

t

WC

t

WPH

OE

WE

DATA IN

DATA OUT

Page Write Cycle

OE

CE

WE

t

WP

t

CS

t

DV

t

WPH

t

BLC

t

DS

HIGH Z

t

OEH

DATA VALID

t

t

CH

DH

3872 FHD F05

*ADDRESS

I/O

BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2

*For each successive write within the page write operation, A7–A17 should be the same or
writes to an unknown address could occur.

13

LAST BYTE

t

WC

3872 FHD F06

XM28C020

DATA Polling Timing Diagram

ADDRESS

CE

WE

OE

I/O

7

An

Toggle Bit Timing Diagram

CE

An An

t

OEH

DIN=X D

=X D

OUT

t

WC

t

OES

OUT

t

DW

=X

3872 FHD F07

WE

t

OEH

OE

I/O

6

* Starting and ending state of I/O6 will vary, depending upon actual tWC.

HIGH Z

*

t

WC

t

OES

t

DW

*

3872 FHD F08

14

XM28C020

PACKAGING INFORMATION

PIN 1

32-PIN DUAL-IN-LINE PACKAGE

CERAMIC LEADLESS CHIP CARRIERS

ON SIDE BRAZED CERAMIC SUBSTRATE

1.600 ± .016

(40.64 ± .40)

.018 ± .002

(.46 ± .05)

1.500 ± .008
(38.10 ± .38)

TOL. NON. ACCUM.

+ .002

.010

– .001

+ .05

(.25 )

– .03

.600 ± .010

(15.24 ± .25)

(7.49)

.010

MIN.

(.25)

.100 ± .005
(2.54 ± .13)

.295

MAX.

.014

(3.56)

TYP.

MIN.

NOTES:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY

15

3926 FHD F12

XM28C020

ORDERING INFORMATION
2 MEGABIT E2 MODULES

XM28C020 X X –X

Device

Access Time

12 = 120ns
15 = 150ns
20 = 200ns
25 = 250ns

Temperature Range

Blank = 0°C to +70°C
I = –40°C to +85°C
M = –55°C to +125°C
MHR = –55°C to +125°C

(High Rel. Processing)

Blank = 32-Lead Ceramic Module
P = 66 Pin PUMA Module (64K x 32 Bit)

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.

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