Datasheet X40014V8-B, X40014V8-A, X40014S8I-C, X40014S8I-B, X40014S8I-A Datasheet (XICOR)

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Page 1

New Features

• Monitor Voltages: 5V to 0.9V

• Independent Core Voltage Monitor

Preliminary Datasheet

X40010/X40011/X40014/X40015

Dual Voltage Monitor with Integrated CPU Supervisor

FEATURES

• Dual voltage detection and reset assertion —Standard reset threshold settings

See Selection table on page 2.

—Adjust low voltage reset threshold voltages

using special programming sequence

—Reset signal valid to V

= 1V

—Monitor three voltages or detect power fail

• Independent Core Voltage Monitor (V2MON)

• Fault detection register

• Selectable power on reset timeout (0.05s,

0.2s, 0.4s, 0.8s)

• Selectable watchdog timer interval (25ms, 200ms,

1.4s, off)

• Low power CMOS —25µA typical standby current, watchdog on —6µA typical standby current, watchdog off

• 400kHz 2-wire interface

• 2.7V to 5.5V power supply operation

• Available packages —8-lead SOIC, TSSOP

APPLICATIONS

• Communication Equipment —Routers, Hubs, Switches —Disk Arrays, Network Storage

• Industrial Systems —Process Control —Intelligent Instrumentation

• Computer Systems —Computers —Network Servers

DESCRIPTION

The X40010/11/14/15 combines power-on reset control, watchdog timer, supply voltage supervision, and secondary voltage supervision, in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

Applying voltage to V

activates the power on reset

circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscillator to stabilize before the processor can e x ecute code.

Low V

detection circuitry protects the user’s system

from low voltage conditions, resetting the system when V

falls below the minimum V

RESET is active until V

returns to proper operating

point. RESET/

TRIP1

level and stabilizes. A second voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available, however, Xicor’s unique circuits allows the

BLOCK DIAGRAM

SDA

SCL

(V1MON)

V2MON

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Data

Command

Decode T est

& Control

Logic

Threshold

Reset Logic

User Programmable

TRIP1

User Programmable

TRIP2

Fault Detection

Status

V2MON V

*X40010/11 = V2MON*

X40014/15 = V

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Watchdog Timer

and

Reset Logic

Power on,

Low V oltage

Reset

Generation

WDO

RESET

X40010/14

RESET

X40011/15

V2FAIL

Characteristics subject to change without notice.

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Page 2

X40010/X40011/X40014/X40015 – Preliminary

threshold for either voltage monitor to be reprogrammed to meet special needs or to ﬁne-tune the

The device features a 2-wire interface and software

protocol allowing operation on an I

bus.

threshold for applications requiring higher precision. The Watchdog Timer provides an independent protec-

tion mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power .

Dual Voltage Monitors

Device Expected System Voltages Vtrip1(V) Vtrip2(V) POR (system)

X40010/11

-A

-B

-C

X40014/15

-A

-B

-C

*Voltage monitor requires V

5V; 3V or 3.3V

5V; 3V

3V; 3.3V; 1.8V

3V; 3.3V; 1.5V

3V; 1.5V

3V or 3.3V; 1.1 or 1.2V

to operation. Others are independent of V

2.0–4.75*

4.55–4.65*

4.35–4.45*

2.85–2.95*

2.0–4.75*

2.85–2.95*

2.55–2.65*

2.85–2.95*

1.70–4.75

2.85–2.95

2.55–2.65

1.65–1.75

0.90–3.50*

1.25–1.35*

0.95–1.05*

RESET = X40010 RESET

RESET = X40014 RESET

= X40011

= X40015

PIN CONFIGURATION

X40010/14, X40011/15

8-Pin TSSOP

WDO

V2F

V2MON

AIL

1 2 3 4

SCL

SDA

RESET/RESET

V2FAIL

V2MON

RESET/RESET

PIN DESCRIPTION

X40010/14, X40011/15

8-Pin SOIC

1 2 3 4

WDO

7 6

SCL

SDA

Name FunctionSOIC TSSOP

1 3 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V

. There is no power up reset delay circuitry on this pin.

TRIP2

voltage, V2FAIL goes

TRIP2

2 4 V2MON

goes HIGH when V2MON exceeds V

V2 Voltage Monitor Input. When the V2MON input is less than the V

LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to V when not used.The V2MON comparator is supplied by V2MON (X40010/11) or by V (X40014/15).

3 5 RESET

RESET

RESET Output. (X40011/15) This is an active LOW, open drain output which goes active when-

ever V

falls below V

. It will remain active until V

TRIP1

rises above V

TRIP1

and for the t

thereafter.

RESET Output. (X40010/14) This is an active HIGH CMOS output which goes active whenever

falls below V

. It will remain active until V

TRIP1

rises above V

TRIP1

and for the t

after.

46V

Ground

TRIP2

or V

Input

PURST

and

PURST

there-

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X40010/X40011/X40014/X40015 – Preliminary

PIN DESCRIPTION

(Continued)

Name FunctionSOIC TSSOP

5 7 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an

open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to

LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this tran-

going active. 6 8 SCL 7 1 WDO

sition within the watchdog time out period results in WDO

Serial Clock. The Serial Clock controls the serial bus timing for data input and output. WDO Output. WDO is an active LOW, open drain output which goes active whenever the

watchdog timer goes active.

82V

PRINCIPLES OF OPERATION

Power On Reset

Application of power to the X40010/11/14/15 activates a Power On Reset Circuit that pulls the RESET/RESET pins active. This signal pro vides sev eral beneﬁts.

– It prevents the system microprocessor from starting to

operate with insufﬁcient voltage.

– It prevents the processor from operating prior to stabili-

zation of the oscillator.

– It allows time for an FPGA to download its conﬁgur ation

prior to initialization of the circuit.

Supply Voltage

impending power failure. For the X40010/11 the V2FAIL signal remains active until the V

drops below 1V (V

falling). It also remains active until V2MON returns and exceeds V

by 0.2V. This voltage sense circuitry

TRIP2

monitors the power supply connected to the V2MON pin. If V

= 0, V2MON can still be monitored.

For the X40014/15 devices, the V2FAIL signal remains actice until V V2MON returns and exceeds V is powered by V

drops below 1Vx and remains active until

. If V

= 0, V2MON cannot be moni-

. This sense circuitry

TRIP2

tored.

Figure 1. Two Uses of Multiple Voltage Monitoring

– It prevents communication to the EEPR OM, g reatly

reducing the likelihood of data corruption on power up.

When V t

PURST

exceeds the device V

threshold value for

TRIP1

(selectable) the circuit releases the RESET (X40011) and RESET (X40010) pin allowing the system to begin operation.

Low Voltage V

During operation, the X40010/11/14/15 monitors the V level and asserts RESET/RESET below a preset minimum V

(V1 Monitoring)

if supply voltage falls . The RESET/RESET

TRIP1

signal prevents the microprocessor from operating in a

X40011-A

6–10V

Resistors selected so 3V appears on V2MON when unregulated

Reg

RESET

V2MON (2.9V)

V2FAIL

supply reaches 6V.

V2MON

power fail or brownout condition. The V1FAIL signal remains active until the voltage drops below 1V. It also remains active until V

PURST

returns and exceeds V

TRIP1

for

Low Voltage V2 Monitoring

The X40010/11/14/15 also monitors a second voltage level and asserts V2FAIL if the voltage falls below a preset minimum V

. The V2FAIL signal is either

TRIP2

Unreg. Supply

3.3V Reg

1.2V Reg

X40014-C

V2MON

RESET

V2FAIL

ORed with RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notiﬁcation of an

Notice: No external components required to monitor two v oltages.

System Reset

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Page 4

X40010/X40011/X40014/X40015 – Preliminary

Figure 2. V

WDO

SCL

SDA

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL also toggles from HIGH to LOW (this is a start bit) followed by a stop condition prior to the expiration of the watchdog time out period to prevent a WDO signal going active. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits by writing to the X40010/ 11/14/15 control register (also refer to page 19).

Figure 3. Watchdog Restart

SCL

SDA

V1 AND V2 THRESHOLD PROGRAM PROCEDURE (OPTIONAL)

The X40010/11/14/15is shipped with standard V1 and V2 threshold (V will not change over normal operating and storage conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the X40010/11/14/15trip

Set/Reset Conditions

TRIPX

A0h

.6µs

TRIP1,

TRIP2

1.3µs

(X = 1, 2)

Timer Start

VCC/V2MON

) voltages. These values

70 70

00h

points may be adjusted. The procedure is described below , and uses the application of a high voltage control signal.

Setting a V

Voltage (x=1, 2)

TRIPx

There are two procedures used to set the threshold voltages (V

), depending if the threshold voltage to

TRIPx

be stored is higher or lower than the present value. For example, if the present V V into the V

is 3.2 V, the new voltage can be stored directly

TRIPx

cell. If however, the new setting is to be

TRIPx

is 2.9 V and the new

TRIPx

lower than the present setting, then it is necessary to “reset” the V

Setting a Higher V

To set a V

voltage before setting the ne w v alue.

TRIPx

Voltage (x=1, 2)

TRIPx

threshold to a new voltage which is

TRIPx

higher than the present threshold, the user must apply the desired V

threshold voltage to the corre-

TRIPx

sponding input pin Vcc(V1MON), or V2MON. The Vcc(V1MON) and V2MON must be tied together during this sequence. Then, a programming voltage (Vp) m ust be applied to the WDO

pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 01h for V

and 09h for V

TRIP1

order to program V

TRIPx

, and a 00h Data Byte in

TRIP2

. The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to complete the operation.

Note: This operation does not corrupt the memory array.

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X40010/X40011/X40014/X40015 – Preliminary

Setting a Lower V

In order to set V present value, then V ing to the procedure described below. Once V has been “reset”, then V

Voltage (x=1, 2)

TRIPx

to a lower voltage than the

TRIPx

must ﬁrst be “reset” accord-

TRIPx

can be set to the desired

TRIPx

voltage using the procedure described in “Setting a Higher V

Resetting the V

To reset a V

TRIPx

V oltage”.

Voltage

TRIPx

voltage, apply the programming voltage (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h for V Data Byte in order to reset V

and 0Bh for V

TRIP1

, followed by 00h for the

TRIP2

. The STOP bit fol-

TRIPx

lowing a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to complete the operation.

After being reset, the value of V

becomes a nomi-

TRIPx

nal value of 1.7V or lesser . Note: This operation does not corrupt the memory

array.

The Control Register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modiﬁed by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. Prior to writing to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Registers" on page 7.

The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40010/ 11/14/15 will not acknowledge any data bytes written after the ﬁrst byte is entered.

The state of the Control Register can be read at any time by performing a random read at address 01Fh, using the special preamble. Only one byte is read by each register read operation. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation.

76543210

PUP1 WD1 WD0 BP 0 RWEL WEL PUP0

CONTROL REGISTER

The Control Register provides the user a mechanism for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are nonvolatile and do not change when pow er is remov ed.

Figure 4. Sample V

TRIP1

Adj.

Reset Circuit

TRIP

V2FAIL

TRIP2

Adj.

RESET

4.7K

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to “1” prior to a write to the Control Register.

Adjust

1 3 2 4

SOIC

X4001x

8 7 6 5

Run

SCL SDA

µC

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X40010/X40011/X40014/X40015 – Preliminary

Figure 5. V

Set/Reset Sequence (X = 1, 2)

TRIPX

applied =

New V

Old VX applied + | Error |

TRIPX

Present Value

TRIPX

Set Higher

Set Higher V

Apply V > Desired V

Programming

Desired

TRIPX

YES

Execute

Reset Sequence

Execute

Sequence

TRIPX

Execute

Sequence

and Voltage

Decrease

TRIPX

Vx = V

Note: X = 1, 2 Let: MDE = Maximum Desired Error

New VX applied =

Old V

applied - | Error |

Execute Reset V

Sequence

, VxMON

MDE

Desired Value

–

MDE

Error = Actual - Desired

TRIPX

Acceptable

Error Range

Output Switches?

Error < MDE

–

Actual

Desired

DONE

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeros to the other bits of the control register.

YES

TRIPX -

TRIPX

| Error | < | MDE |

Error > MDE

Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeros to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition.

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X40010/X40011/X40014/X40015 – Preliminary

PUP1, PUP0: Power Up Bits (Nonvolatile)

The Power Up bits, PUP1 and PUP0, determine the

time delay. The nominal power up times are

PURST

shown in the following tab le .

PUP1 PUP0 Power on Reset Delay (t

0 0 50ms 0 1 200ms (factory setting) 1 0 400ms 1 1 800ms

PURST

)

WD1, WD0: Watchdog Timer Bits (Nonvolatile)

The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below.

WD1 WD0 Watchdog Time Out Period

0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory setting)

Writing to the Control Registers

Changing any of the nonvolatile bits of the control and trickle registers requires the following steps:

– Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Oper ation preceded by a start and ended with a stop).

– Write a 06H to the Control Register to set the

Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop).

– Write a one byte value to the Control Register that

has all the control bits set to the desired state. The Control register can be represented as qxys 001r in binary, where xy are the WD bits, s isthe BP bit and qr are the power up bits. This operation proceeded by a start and ended with a stop bit. Since this is a

nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset b y this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK.

– A read operation occurring between any of the

previous operations will not interrupt the register write operation.

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block.

To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set.

FAULT DETECTION REGISTER

The Fault Detection Register (FDR) provides the user the status of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and three Low V oltage Fail bits are volatile.

76543210

LV1F LV2F 0 WDF 0 0 0 0

The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modiﬁed by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation.

There is no need to set the WEL or RWEL in the control register to access this fault detection register .

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X40010/X40011/X40014/X40015 – Preliminary

Figure 6. Valid Data Changes on the SDA Bus

SCL

SDA

Data Stable Data Change Data Stable

At power-up, the Fault Detection Register is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring take place. In the event of any one of the monitored sources failed. The corresponding bits in the register will change from a “1” to a “0” to indicate the failure. At this moment, the system should perform a read to the register and noted the cause of the reset. After reading the register the system should reset the register back to all “1” again. The state of the Fault Detection Register can be read at any time by performing a random read at address 0FFh, using the special preamble.

The FDR can be read by performing a random read at OFFh address of the register at any time. Only one byte of data is read by the register read operation.

WDF, Watchdog Timer Fail Bit (Volatile)

The WDF bit will set to “0” when the WDO goes active.

LV1F, Low VCC Reset Fail Bit (Volatile)

The LV1F bit will be set to “0” when VCC (V1MON) falls below V

TRIP1

LV2F, Low V2MON Reset Fail Bit (Volatile)

The LV2F bit will be set to “0” when V2MON falls below V

TRIP2

SERIAL INTERFACE

Interface Conventions

The device supports a bidirectional bus oriented protocol. The protocol deﬁnes any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications .

Serial Clock and Data

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 6.

Serial Start Condition

All commands are preceded by the start condition, which is a HIGH to LOW transition of SD A when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 6.

Serial Stop Condition

All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus . See Figure 6.

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X40010/X40011/X40014/X40015 – Preliminary

Figure 7. Valid Start and Stop Conditions

SCL

SDA

Start Stop

Serial Acknowledge

Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. See Figure 8.

The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identiﬁer and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for the Slave Address Byte when the Device Identiﬁer and/or Select bits are incorrect.

In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state.

Serial Write Operations

Byte Write

For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 9.

A write to a protected block of memory will suppress the acknowledge bit.

Figure 8. Acknowledge Response From Receiver

SCL from

Master

Data Output

from T ransmitter

Data Output

from Receiver

Start Acknowledge

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X40010/X40011/X40014/X40015 – Preliminary

Read Operation

Prior to issuing the Slave Address Byte with the R/W

bit set to one, the master must ﬁrst perform a “dummy” write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immedi-

Figure 9. Read Sequence

Signals from

the Master

SDA Bus

Signals from

the Slave

r t

101001

Slave

Address

A C K

Byte

Address

11111111

Stops and Write Modes

Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be eff ected.

Acknowledge Polling

The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. See Figure

12.

ately issues another start condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. See Figure 12 for the address, acknowledge, and data transfer sequence.

Slave

Address

r t

A C K

A C

Data

t o p

Serial Read Operations

Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads.

Current Address Read

Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power up, the address of the address counter is undeﬁned, requiring a read or write operation for initialization.

Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. See Figure 13 for the address, acknowledge, and data tr ansf er sequence.

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X40010/X40011/X40014/X40015 – Preliminary

Figure 10. Acknowledge Polling Sequence

Byte Load Completed

by Issuing STOP.

Enter ACK Polling

Issue START

Issue Slave Address Byte (Read or Write)

ACK

Returned?

YES

High Voltage Cycle

Complete. Continue

Command Sequence?

YES

Continue Normal

Read or Write

Command Sequence

PROCEED

Issue STOP

issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immediately issues another start condition and the Slave Address Byte with the R/W

bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. See Figure 14 for the address, acknowledge, and data tr ansfer sequence .

A similar operation called “Set Current Address” where the device will perform this operation if a stop is issued instead of the second start shown in Figure 13. The device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next Current Address Read operation will read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data.

Sequential Read

Sequential reads can be initiated as either a current address read or random address read. The ﬁrst Data Byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition.

It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.

Random Read

Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must ﬁrst perform a “dummy” write operation. The master

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The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. At the end of the address space the counter “rolls over” to address 0000H and the device continues to output data for each acknowledge received. See Figure 15 for the acknowledge and data tr ansf er sequence.

Characteristics subject to change without notice. 11 of 25

Page 12

X40010/X40011/X40014/X40015 – Preliminary

SERIAL DEVICE ADDRESSING

Memory Address Map

CR, Control Register, CR7: CR0 Address: 1FF

hex

FDR, Fault DetectionRegister, FDR7: FDR0 Address: 0FF

hex

Slave Address Byte

Following a start condition, the master must output a Slave Address Byte. This b yte consists of se ver al parts:

– a device type identiﬁer that is always ‘101x’. Where

x=0 is for Array, x=1 is for Control Register or Fault

Detection Register. – next two bits are ‘0’. – next bit that becomes the MSB of the address.

Figure 12. Current Address Read Sequence

Signals from

the Master

SDA Bus

r t

Slave

Address

1010 00

Figure 11. X40010/11/14/15 Addressing

Slave Byte

Control Register Fault Detection Register

1011 10110000

Word Address

111111111111111

t o p

R/W

Signals from

the Slave

Figure 13. Random Address Read Sequence

Signals from

the Master

SDA Bus

Signals from

the Slave

REV 1.3.4 7/12/02

r t

101 00

Slave

Address

A C K

Byte

Address

A C K

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Data

Slave

Address

r t

Characteristics subject to change without notice. 12 of 25

Data

t o p

Page 13

X40010/X40011/X40014/X40015 – Preliminary

– One bit of the slave command byte is a R/W

bit. The R/W bit of the Slave Address Byte deﬁnes the operation to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation.

Word Address

The word address is either supplied by the master or obtained from an internal counter. The internal counter is undeﬁned on a power up condition.

Operational Notes

The device powers-up in the f ollo wing state: – The device is in the low power standby state.

– The WEL bit is set to ‘0’. In this state it is not possible

to write to the device.

– SDA pin is the input mode. – RESET/RESET Signal is active for t

PURST

Figure 14. Sequential Read Sequence

Data Protection

The following circuitry has been included to prevent inadvertent writes:

– The WEL bit must be set to allow write operations. – The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile write cycle.

– A three step sequence is required before writing into

the Control Register to change Watchdog Timer or Block Lock settings.

Signals from

the Master

SDA Bus

Signals from

the Slave

Slave

Address

A C K

Data

(1)

Data

(2)

A C K

Data (n-1)

(n is any integer greater than 1)

A C K

Data

(n)

o p

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Characteristics subject to change without notice. 13 of 25

Page 14

X40010/X40011/X40014/X40015 – Preliminary

ABSOLUTE MAXIMUM RATINGS

Temperature under bias................... –65°C to +135°C

Storage temperature........................ –65°C to +150°C

V oltage on an y pin with

respect to VSS......................................–1.0V to +7V

D .C . output current ...............................................5mA

Lead temperature (soldering, 10 seconds)........ 300°C

COMMENT

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this speciﬁcation) is not implied. Exposure to absolute maximum rating conditions for extended periods ma y aff ect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature Min. Max.

Commercial 0°C 70°C

Industrial –40°C +85°C

Version

X40010/11

-A or -B

X40010/11-

C, X40014/15

*See Ordering Info

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise speciﬁed)

Symbol Parameter Min. Typ.

(1)

I I

SB1

SB2

CC1 CC2

HYS

Active Supply Current (VCC) Read 1.5 mA VIL = VCC x 0.1

(1)

Active Supply Current (VCC) Read 3.0 mA

(1)(6)

Standby Current (VCC) AC (WDT off) 6 10 µA VIL = VCC x 0.1

(2)(6)

Standby Current (VCC) DC (WDT on) 25 30 µA V

Input Leakage Current (SCL) 10 µA VIL = GND to V Output Leakage Current (SDA,

V2FAIL

(3)

Input LOW Voltage (SDA, SCL) -0.5 V

(3)

Input HIGH Voltage (SDA, SCL) V

(6)

Schmitt Trigger Input Hysteresis

• Fixed input level

•

, WDO, RESET)

related level

x 0.7 V

0.2

.05 x V

Output LOW Voltage (SDA, RESET/ RESET

, V2FAIL, WDO)

Output (RESET) HIGH Voltage VCC – 0.8

– 0.4

(4)

CC CC

Chip Supply

Voltage

Monitored*

Voltages

2.7V to 5.5V 2.6V to 5V

2.7V to 5.5V 1V to 3.6V

Max. Unit Test Conditions

= VCC x 0.9,

= 400kHz

SCL

x 0.9

, f

= 400kHz

SDA

= V

SCL

= V

= GND to V

10 µA V

VIH = f

SCL

SDA

Others = GND or V

SDA

Device is in Standby x 0.3 V + 0.5 V

V V

0.4 V I

= 3.0mA (2.7–5.5V)

= 1.8mA (2.7–3.6V)

= -1.0mA (2.7–5.5V)

= -0.4mA (2.7–3.6V)

(2)

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Characteristics subject to change without notice. 14 of 25

Page 15

X40010/X40011/X40014/X40015 – Preliminary

D.C. OPERATING CHARACTERISTICS (Continued)

(Over the recommended operating conditions unless otherwise speciﬁed)

Symbol Parameter Min. Typ.

VCC Supply

(5)

TRIP1

Trip Point Voltage Range 2.0 4.75 V

4.55 4.6 4.65 V X40010/11-A

4.35 4.4 4.45 V X40010/11-B

2.85 2.9 2.95 V X40010/11-C,

2.55 2.6 2.65 V X40014/15-B

(6)

RPD2

to V2FAIL 5µS

TRIP2

Second Supply Monitor

V2MON Current 15 µA

(5)

V2MON Trip Point Voltage Range 1.7

TRIP2

0.9

2.85 2.9 2.95 V X40010/11-A

2.55 2.6 2.65 V X40010/11-B

1.65 1.7 1.75 V X40010/11-C

1.25 1.3 1.35 V X40014/15-A&B

0.95 1.0 1.05 V X40014/15-C

(4)

Max. Unit Test Conditions

X40014/15-A&C

4.75

3.5

VVX40010/11

X40014/15

Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave

Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.

(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that ini-

tiates a high voltage cycle; or 9 cloc k cycles after an y start that is not follow ed b y the correct Device Select Bits in the Slave Address

Byte. (3) VIL Min. and VIH Max. are f or ref erence only and are not tested. (4) At 25°C, VCC = 5V. (5) See Ordering Information for standard programming lev els. For custom programmed le vels , contact f actory. (6) Based on characterization data.

EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2)

∆V V

ref

VxMON

REF

–

RPDX

Output Pin

= 5µs worst case

∆V = 100mV

CAPACITANCE

Symbol Parameter Max. Unit Test Conditions

OUT

(1)

Output Capacitance (SDA, RESET, RESET, V2FAIL,

)

WDO Input Capacitance (SCL) 6 pF VIN = 0V

8pFV

OUT

= 0V

Note: (1) This parameter is not 100% tested.

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Characteristics subject to change without notice. 15 of 25

Page 16

X40010/X40011/X40014/X40015 – Preliminary

EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR

= 5V

SDA

2.06KΩ

RESET

30pF

WDO

OUT

4.6KΩ

V2FAIL

30pF

V2MON

4.6KΩ

30pF

A.C. TEST CONDITIONS

Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns

Input and output timing levels

x 0.5

Output load Standard output load

SYMBOL TABLE

WAVEFORM INPUTS OUTPUTS

Must be steady

May change from LOW

May change from HIGH to LOW

Don’t Care: Changes Allowed

N/A Center Line

Will be steady

Will change from LOW to HIGH

Will change from HIGH to LOW

Changing: State Not Known

is High Impedance

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Characteristics subject to change without notice. 16 of 25

Page 17

X40010/X40011/X40014/X40015 – Preliminary

A.C. CHARACTERISTICS

400kHz

Symbol Parameter

SCL

BUF

LOW

HIGH

SU:STA

HD:STA

SU:DAT

HD:DAT

SU:STO

Cb Capacitive load for each bus line 400 pF

SCL Clock Frequency 0 400 kHz Pulse width Suppression Time at inputs 50 ns SCL LOW to SDA Data Out Valid 0.1 0.9 µs Time the bus free before start of new transmission 1.3 µs Clock LOW Time 1.3 µs Clock HIGH Time 0.6 µs Start Condition Setup Time 0.6 µs Start Condition Hold Time 0.6 µs Data In Setup Time 100 ns Data In Hold Time 0 µs Stop Condition Setup Time 0.6 µs Data Output Hold Time 50 ns SDA and SCL Rise Time 20 +.1Cb SDA and SCL Fall Time 20 +.1Cb

(1) (1)

300 ns 300 ns

UnitMin. Max.

Note: (1) Cb = total capacitance of one bus line in pF.

TIMING DIAGRAMS

Bus Timing

SCL

SDA IN

SDA OUT

SU:STA

HD:STA

SU:DAT

HIGH

LOW

HD:DAT

SU:STO

BUF

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Characteristics subject to change without notice. 17 of 25

Page 18

X40010/X40011/X40014/X40015 – Preliminary

Write Cycle Timing

SCL

SDA

8th Bit of Last Byte

ACK

Stop

Condition

Start

Condition

Nonvolatile Write Cycle Timing

Symbol Parameter Min. Typ.

(1)

Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.

It is the minimum cycle time to be allowed for any non v olatile write by the user, unless Acknowledge Polling is used.

Write Cycle Time 5 10 ms

(1)

Max. Unit

Power Fail Timings

TRIPX

V2MON

[]

LOWLINE or

V2F

[]

AIL or

V3FAIL

RPDL

RPDX

RVALID

RPDL

RPDX

RPDL

RPDX

X = 2, 3

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Characteristics subject to change without notice. 18 of 25

Page 19

X40010/X40011/X40014/X40015 – Preliminary

RESET/RESET

Timings

RESET

TRIP1

PURST

RPD1

RVALID

PURST

LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS

Symbol Parameters Min. Typ.

(2)

RPD1

RPDX

PURST

to RESET/RESET (Power down only) 5 µs

TRIP1

(2)

to V2FAIL 5µs

TRIP2

Power On Reset delay: PUP1=0, PUP0=0

RVALID

WDO

PUP1=0, PUP0=1 (factory setting) PUP1=1, PUP0=0 PUP1=1, PUP0=1

F R

V2MON, Fall Time 20 mV/µs

CC,

V2MON, Rise Time 20 mV/µs

CC,

Reset Valid V

Watchdog Timer Period:

200 400 800

WD1=0, WD0=0 WD1=0, WD0=1

200 WD1=1, WD0=0 WD1=1, WD0=1 (factory setting)

RST1

Watchdog Reset Time Out Delay

100 200 300 ms WD1=0, WD0=0 WD1=0, WD0=1

RST2

RSP

Watchdog Reset Time Out Delay WD1=1, WD0=0 12.5 25 37.5 ms Watchdog timer restart pulse width 1 µs

1.4 25

OFF

(1)

Max. Unit

(2) (2) (2)

(2)

ms ms ms ms

s ms ms

Notes: (1) VCC = 5V at 25°C.

(2) Values based on characterization data only.

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Characteristics subject to change without notice. 19 of 25

Page 20

X40010/X40011/X40014/X40015 – Preliminary

Watchdog Time Out For 2-Wire Interface

TRIPX

SCL

SDA

WDO

Minimum Sequence to Reset WDT

SCL

SDA

Set/Reset Conditions

Start

Clockin (0 or 1)

Start

RSP

< t

WDO

Start

WDT Restart

RST

WDO

RST

SCL

SDA

TSU

WDO

Start

VPS

A0h

TRIPX

)

01h* 09h*

VCC/V2MON

sets V

TRIP1

sets V

TRIP2

* all others reserved

70 7

00h

resets V

03h* 0Bh*

resets V

TRIP1

TRIP2

THD

VPH

VPO

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Characteristics subject to change without notice. 20 of 25

Page 21

X40010/X40011/X40014/X40015 – Preliminary

TRIP1

, V

, Programming Specifications: VCC = 2.0–5.5V; Temperature = 25°C

TRIP2

Parameter Description Min. Max. Unit

VPS

VPH

TSU

THD

VPO

TRAN1

TRAN2

TRAN2A

VPS

WDO Program Voltage Setup time 10 µs WDO Program Voltage Hold time 10 µs V

Level Setup time 10 µs

TRIPX

Level Hold (stable) time 10 µs

TRIPX

Program Cycle 10 ms

TRIPX

Program Voltage Off time before next cycle 1 ms Programming Voltage 15 18 V V

Set Voltage Range 2.0 4.75 V

TRIP1

Set Voltage Range – X40010/11 1.7 4.75 V

TRIP2

Set to Voltage Range – X40014/15 0.9 3.5 V

TRIP2

Set Voltage variation after programming (-40 to +85°C). -25 +25 mV

TRIPX

WDO Program Voltage Setup time 10 µs

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Characteristics subject to change without notice. 21 of 25

Page 22

X40010/X40011/X40014/X40015 – Preliminary

PACKAGING INFORMATION

8-Lead Plastic, SOIC, Package Code S8

Pin 1 Index

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

Pin 1

X 45°

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

0.150 (3.80)

0.158 (4.00)

0.004 (0.19)

0.010 (0.25)

0.228 (5.80)

0.244 (6.20)

0.053 (1.35)

0.069 (1.75)

0.050" Typical

0° - 8°

REV 1.3.4 7/12/02

0.0075 (0.19)

0.010 (0.25)

0.016 (0.410)

0.037 (0.937)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

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0.250"

Characteristics subject to change without notice. 22 of 25

0.050" Typical

0.030"

Typical

8 PlacesFOOTPRINT

Page 23

X40010/X40011/X40014/X40015 – Preliminary

PACKAGING INFORMATION

8-Lead Plastic, TSSOP, Package Code V8

.025 (.65) BSC

0° – 8°

.019 (.50) .029 (.75)

Detail A (20X)

.114 (2.9) .122 (3.1)

.0075 (.19) .0118 (.30)

.010 (.25)

.169 (4.3) .177 (4.5)

.002 (.05) .006 (.15)

Gage Plane Seating Plane

.252 (6.4) BSC

.047 (1.20)

(4.16)

(7.72)

See Detail “A”

REV 1.3.4 7/12/02

(1.78)

.031 (.80)

.041 (1.05)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

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(0.42)

All Measurements Are Typical

Characteristics subject to change without notice. 23 of 25

(0.65)

Page 24

X40010/X40011/X40014/X40015 – Preliminary

ORDERING INFORMATION

Operating

Range

2.9-5.5 4.6V±50mV 2.9V±50mV 8L SOIC 0oC - 70oC X40010S8-A X40011S8-A

2.6-5.5 4.4V±50mV 2.6V±50mV 8L SOIC 0

1.7-3.6 2.9V±50mV 1.7V±50mV 8L SOIC 0

1.3-3.6 2.9V±50mV 1.3V±50mV 8L SOIC 0

1.3-3.6 2.6V±50mV 1.3V±50mV 8L SOIC 0

1.0-3.6 2.9V±50mV 1.0V±50mV 8L SOIC 0

TRIP1

Range V

Range Package

TRIP2

Temperature

-40

8L TSSOP 0

-40

8L TSSOP 0

-40

8L TSSOP 0

-40

8L TSSOP 0

-40

8L TSSOP 0

-40

8L TSSOP 0

-40

Part Number

Range

C - 85oC X40010S8I-A X40011S8I-A

C - 70oC X40010V8-A X40011V8-A

C - 85oC X40010V8I-A X40011V8I-A

C - 70oC X40010S8-B X40011S8-B

C - 85oC X40010S8I-B X40011S8I-B

C - 70oC X40010V8-B X40011V8-B

C - 85oC X40010V8I-B X40011V8I-B

C - 70oC X40010S8-C X40011S8-C

C - 85oC X40010S8I-C X40011S8I-C

C - 70oC X40010V8-C X40011V8-C

C - 85oC X40010V8I-C X40011V8I-C

C - 70oC X40014S8-A X40015S8-A

C - 85oC X40014S8I-A X40015S8I-A

C - 70oC X40014V8-A X40015V8-A

C - 85oC X40014V8I-A X40015V8I-A

C - 70oC X40014S8-B X40015S8-B

C - 85oC X40014S8I-B X40015S8I-B

C - 70oC X40014V8-B X40015V8-B

C - 85oC X40014V8I-B X40015V8I-B

C - 70oC X40014S8-C X40015S8-C

C - 85oC X40014S8I-C X40015S8I-C

C - 70oC X40014V8-C X40015V8-C

C - 85oC X40014V8I-C X40015V8I-C

with RESET

Part Number

with RESET

PART MARK INFORMATION

REV 1.3.4 7/12/02

8-Lead Package

X4001XX

YYWWXX

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0/1/4/5

Package - S/V A, B, or C

I – Industrial

Blank – Commercial

WW – Workweek YY – Year

Characteristics subject to change without notice. 24 of 25

Page 25

X40010/X40011/X40014/X40015 – Preliminary

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemniﬁcation provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warr anty of merchantability or ﬁtness for any purpose. Xicor, Inc. reserves the right to discontinue production and change speciﬁcations and prices at any time and without notice.

Xicor, Inc. assumes no responsibility f or the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

COPYRIGHTS AND TRADEMARKS

Xicor, Inc., the Xicor logo, E

KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are

E used for identification purposes only, and are trademarks or registered trademarks of their respective holders.

U.S. PA TENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. F oreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life , system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prev ent such an occurrence.

Xicor’s products are not authorized for use in critical components in lif e support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signiﬁcant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiv eness.

REV 1.3.4 7/12/02

POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,

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Characteristics subject to change without notice. 25 of 25