Page 1
Surface Mount P-Channel Enhancement
Lead(Pb)-Free
P b
Mode POWER MOSFET
1 GATE
Features:
*Super High Dense Cell Design For Low RDS(ON)
R
<90m Ω@VGS=-10V
DS(ON)
*Simple Drive Requirement
*Lower On-resistance
*Fast Switching Characteristic
*TO-252 Package
SOURCE
3
2
DRAIN
WTD9575
DRAIN CURRENT
-15 AMPERES
DRAIN SOURCE VOLTAGE
-60 VOLTAGE
1. GATE
2.4 DRAIN
3. SOURCE
D-PAK / (TO-252)
4
1
2
3
Maximum Ratings(T
=25 C Unless Otherwise Specified)
A
Rating Symbol Value
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current, (V
, (V
Pulsed Drain Current
1
Total Power Dissipation(T
Maximum Thermal Resistace Junction-case
Maximum
Operating Junction
Thermal Resistace Junction-ambient
and Storage Temperature Range
@10V, TC=25˚C)
GS
@10V, TC=100˚C)
GS
=25˚C)
C
V
DS
V
GS
I
D
I
DM
P
D
R
θJC
R
θJA
TJ,Tstg
-60
±25
-15
-9.5
-45
36
3.5
110
-55~+150
Unit
V
A
W
˚C/W
˚C/W
˚C
Device Marking
WTD9575=9575
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01-Aug-05
WTD9575
Electrical Characteristics(T
Characteristic Symbol Min Typ Max Unit
Static
Drain-Source Breakdown Voltage
VGS=0,ID=-250μA
Gate-Source Threshold Voltage
VDS=VGS,ID=-250μA
Gate-Source Leakage current
VGS=±25V
Drain-Source Leakage Current(Tj=25˚C)
VDS=-60V,VGS=0
Drain-Source
VDS=-48V,VGS=0
Drain-Source On-Resistance
VGS=-10V,ID=-12A
VGS=-4.5V,ID=-9A
Leakage Current(Tj=70˚C)
= 25℃ Unless otherwise noted)
A
BV
V
DSS
GS(Th)
I
GSS
I
DSS
R
DS(on)
-60 - -
-1.0 - -3.0
- -
- - -1
- - -25
-
-
-
-
V
±100
90
120
nA
μA
mΩ
Forward Transconductance
VDS=-10V,ID=-9A
Dynamic
Input Capacitance
VGS=0V,VDS=-25V,f=1.0MHz
Output Capacitance
VGS=0V,VDS=-25V,f=1.0MHz
Reverse Transfer Capacitance
VGS=0V,VDS=-25V,f=1.0MHz
gfs - 14 - S
C
iss
C
oss
C
rss
- 1660 2660
- 160 -
- 100 -
pF
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Page 3
3/6
01-Aug-05
WTD9575
Switching
Turn-on Delay Time
VDS=-30V,VGS=-10V,ID=-9A,RD=3.3Ω,RG=3.3Ω
2
t
d(on)
- 10 -
Rise Time
VDS=-30V,VGS=-10V,ID=-9A,RD=3.3Ω,RG=3.3Ω
Turn-off Delay Time
VDS=-30V,VGS=-10V,ID=-9A,RD=3.3Ω,RG=3.3Ω
Fall Time
VDS=-30V,VGS=-10V,ID=-9A,RD=3.3Ω,RG=3.3Ω
Total Gate Charge
2
VDS=-48V,VGS=-4.5V,ID=-9A
Gate-Source Charge
VDS=-48V,VGS=-4.5V,ID=-9A
Gate-Source Change
VDS=-48V,VGS=-4.5V,ID=-9A
t
t
d(off)
t
Q
Q
Q
gd
r
- 19 ns
- 46 -
f
g
gs
- 53 -
- 17 27
- 5 -
nC
- 6 -
Source-Drain Diode Characteristics
Forward On Voltage
VGS=0V,IS=-9A
Reverse Recovery Time
VGS=0V,IS=-9A,dl/dt=100A/µs
Reverse Recovery Charge
VGS=0V,IS=-9A,dl/dt=100A/µs
Note: 1. Pulse width limited by safe operating area.
2. Pulse width ≤ 300μs, duty cycle ≤ 2%.
2
V
SD
T
rr
Q
rr
- - -1.2 V
- 56 - ns
- 159 - nC
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WEITRON
Page 4
WTD9575
55
50
45
)A( TNERRUC NIARD,
40
35
30
25
20
15
D
I-
10
5
0
0 2 4 6 8 10
°
T
C
=25
C
-V
,DRAIN-TO-SOURCE VOLTAGE(V)
DS
FIG.1 Typical Output Characteristics
1400
1200
1000
)Ωm(
800
)
n
o(
s
D
R
600
400
ID = -9A
TC = 25˚C
-10V
-6.0V
-5.0V
-4.5V
VG=-3.0V
40
35
T
=150˚C
)A( tnerruC niarD,
30
25
20
15
D
I
10
2.0
1.8
1.6
)no(sD
1.4
C
5
0
0 2 4 6 8 10 12
V
,Drain-to-source Voltage(V)
DS
Typical Output Characteristics
Fig.2
ID = -12A
VG = -10V
R dezil
1.2
amro
1.0
N
0.8
0.6
-10V
-6.0V
-5.0V
-4.5V
VG=-3.0V
200
1 4 7 10
-V
,Gate-to-source Voltage(V)
GS
Fig.3 On-Resistance v.s. Gate Voltage
15.0
12.5
10.0
Tj = 150˚C
7.5
)A(
5.0
S
I-
2.5
0.0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
-V
,Source-to-Drain Voltage(V)
DS
Tj = 25˚C
Fig.5 Forward Characteristics of
Reverse Diode
0.4
-50 0 50 100 150
Tj ,Junction Temperature(˚C)
Fig.4 Normalized OnResistance
2.5
2.0
)
V(
)
h
t(
S
1.5
G
V-
1.0
0.5
-50 0 50 100 150
Tj ,Junction Temperature(˚C)
Fig.6 Gate Threshold Voltage v.s.
Junction
Temperature
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Page 5
WTD9575
5/6
01-Aug-05
12
(V)
10
ge
a
olt
V
8
e
6
4
, Gate to Sourc
SG
V-
2
0
0 10 20 30 40
QG , Total Gate Charge(nC)
Fig 7. Gate Charge Characteristics
100
10
)A(
D
I-
1
TC = 25˚C
Single Pulse
0.1
0.1 1 10 100 1000
-V
, Drain-to-Source Voltage(V)
DS
Fig 9. Maximum Safe Operation Area
ID = -9A
VDS = -48V
100us
1ms
10ms
100ms
DC
10000
1000
f = 1.0MHz
Ciss
Fp(C )
Coss
100
10
1 5 9 13 17 21 25 29
Crss
-VDS, Drain-to-Source Voltage(V)
Fig 8. Typical Capacitance Characteristics
1
)
cj
Duty factor = 0.5
θ
R(esnopseR lamrehT de
0.2
0.1
0.1
0.05
z
il
a
m
ro
N
0.02
0.01
Single pulse
0.01
0.00001 0.0001 0.001 0.01 0.1 1
P
DM
t
T
Duty factor = t / T
Peak Tj=P
DM
x R
θ jc
+ T
c
t, Pulse Width(s)
Fig 10. Effective Transient Thermal Impedance
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V
DS
90%
10%
V
GS
11. Switching Time Circuit
Fig
WEITRON
t
d(on)
VG
Q
G
-4.5V
Q
GS
t
r
t
d(off)tf
Fig.12 Gate Charge
Q
GD
Charge
Q
Waveform
Page 6
WTD9575
6/6
01-Aug-05
D-PAK / (TO-252) Outline Dimension
E
A
4
1 2 3
D
B
M
C
G
H
J
K
L
Dim
A
B
C
D
E
G
H
J
K
L
M
D-PAK
Min
6.40
9.00
0.50
-
2.20
0.45
1.00
5.40
0.30
0.70
0.90
Unit:mm
Max
6.80
10.00
0.80
2.30
2.50
0.55
1.60
5.80
0.64
1.70
1.50
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