Datasheet WM2627IDT, WM2627CDT Datasheet (Wolfson)

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WM2627

Quad 8-Bit Serial Input Voltage Output DAC

Production Data, April 2001, Rev 1.0

FEATURES

• Four 8-bit voltage output DACs

• Dual 2.7V to 5.5V supply (separate digital and analogue

supplies)

• DNL ±0.03 LSB, INL ±0.3 LSB typical

• Low power consumption:

- 3mW, slow mode - 3V supply

- 9mW, fast mode - 3V supply

• DSP and microprocessor compatible serial in terface

• Programmable settling time of 2.5µs or 8.5µs typical

APPLICATIONS

• Battery powered test instruments

• Digital offset and gain adjustment

• Battery operated/remote industrial controls

• Machine and motion control devices

• Wireless telephone and communication systems

• Arbitrary waveform generation

• Robotics

ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE

WM2627CDT 0° to 70°C 16-pin TSSOP

WM2627IDT -40° to 85°C 16-pin TSSOP

DESCRIPTION

The WM2627 is a quadruple 8-bit voltage output, res istor s tring, digital-to-analogue converter. Each DAC can be individually powered down under software control. A hardware controlled mode is provided that powers down all DACs. Power down reduces current consum ption to 1 µA.

The device has been designed to interface effi ciently t o industry standard microprocess ors and DSPs. It is program med with a 16-bit serial word comprisi ng of a DAC address, individual DAC control bits and an 8-bit value.

The WM2627 has provision for t wo supplies: one supply for the serial interface (DVDD, DGND), and one for the DACs, reference buffers and output buffers (AVDD, AGND). This enables a typical application where the device can be control led via a microprocessor operat ing on a 3V supply, with the DACs operating on a 5V supply. Alternat ively, the s upplies c an be tied together in a single supply application.

Excellent performance is delivered with a typical DNL of ±0.03 LSB. The settling ti me of t he DAC is program m able to allow t he designer to optimize speed versus power dissipation. The output stage is buffered by a x2 gain near rail-to-rail amplif ier, which features a Class AB output stage. DACs A and B can have a different reference voltage t o DACs C and D.

The device is available in a 16-pin TSSOP package. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported.

BLOCK DIAGRAM TYPICAL PERFORMANCE

REFINAB (15) REFINCD (10)

WM2627

DIN (4)

16-BIT SHIFT

FS (7)

AND

CONTROL

SCLK (5)

LOGIC

NCS (6)

POWER-ON

RESET

(9)

(8)

AGND

DGND

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176

DAC A

data

10-BIT DATA AND CONTROL

HOLDING

LATCH

AVDD

(16)

REFERENCE

INPUT BUFF ER

8-BIT DAC

LATCH

2-BIT

CONTROL

LATCH

DAC B

DAC C

DAC D

(3)

NLDAC

DVDD

(1)

POWERDOWN/

CONTROL

SPEED

NPD

(2)

DAC OUTPUT BUFFER

(14) OUTA

(13) OUTB

(12) OUTC

(11) OUTD

Differential Non-Linearity (LSBs)

0.04

0.03

0.02

0.01

-0.01

-0.02

-0.03

-0.04

AVDD = DVDD = 5V, VREF = 2.048V, Slow Mode

0 32 64 96 128 160 192 224 256

DIGITAL CODE

Production Data Datasheets contain final

specifications current on publication date.

Supply of products conforms to Wol fson Microelectronics’ Terms and Condit i ons.

Email: [email protected] www.wolfsonmicro.com

2001 Wolfson Microelectronics Ltd.

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WM2627 Production Data

PIN CONFIGURATION

DVDD

NPD

NLDAC

DIN

SCLK

NCS

DGND

1 2 3 4 5 6 7

16 15 14 13 12 11 10

AVDD REFINAB OUTA OUTB OUTC OUTD REFINCD

AGND

PIN DESCRIPTION

PIN NO NAME TYPE DESCRIPTION

1 2

4 5 6 7 8

9 10 11 12 13 14 15 16

DVDD Supply Digital supply.

NPD Digital input Power down. Powers down all DACs overridi ng t heir individual power

down settings and all output stages. This pin is active l ow.

NLDAC Digital input Load DAC. Digital input active low. NLDAC must be taken low to update

the DAC latch from t he hol di ng l atches.

DIN Digital input Serial data input.

SCLK Digital input Serial cloc k input.

NCS Digital input Chip sel e ct. This pin is acti ve low.

FS Digital input Frame synchronis ation for serial input data. DGND Ground Digital ground. AGND Ground Analogue ground.

REFINCD Analogue i nput Voltage reference input for DACs C and D.

OUTD Analogue output DAC D output. OUTC Analogue output DAC C output. OUTB Analogue output DAC B output. OUTA Analogue output DAC A output.

REFINAB Analogue input Voltage reference input for DACs A and B.

AVDD Supply Analogue supply.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 April 2001

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WM2627 Production Data

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are s tres s rat ings only. P erm anent damage to the device may be c aused by c onti nuously operat ing at or beyond these limits. Device functional operating lim its and guaranteed performance s pecifications are gi ven under Electrical Characteristics at the test conditions s pecified.

ESD Sensitive Device. Thi s device i s m anufactured on a CMOS process . It i s t herefore generi cally suscept ible to damage from excessi ve stati c voltages . Proper ES D precautions mus t be tak en during handling and st orage of this device.

CONDITION MIN MAX

Supply voltages, AVDD t o A G ND, DVDD to DGND Supply voltage differences , AVDD to DVDD Digital input voltage Reference input voltage Operating temperature range, T

WM2627C WM2627I

Storage temperature Soldering lead temperature, 1. 6mm (1/16 inch) from package body for

-2.8V 2.8V

-0.3V DVDD + 0.3V

-0.3V AVDD + 0.3V 0°C

-40°C

-65°C 150°C

70°C 85°C

260°C

10 seconds

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS M IN TYP MAX UNIT

Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to

AVDD, DVDD 2.7 5.5 V

REF

DVDD = 2.7V to 5.5V 2 V DVDD = 2.7V to 5.5V 0.8 V

See Note 0 AVDD - 1.5 V

REFINAB, REFI NCD Load resistance Load capacitance

Serial clock rate Operating free-air temperature

R C

SCLK

L L

210 kΩ

100 pF

20 MHz

WM2627CDT 0 70 °C

WM2627IDT -40 85 °C

Note: Reference voltages greater than A V DD/2 will cause output saturation for large DAC c odes.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 April 2001

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WM2627 Production Data

ELECTRICAL CHARACTERISTICS

Test Conditions:

= 10kΩ, CL = 100pF. AVDD = DVDD = 5V ± 10%, V

recommended operating free-ai r temperature range (unless noted otherwise).

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications

Resolution Integral non-linearity Differential non-linearity Zero code error Gain error Power supply rejection ratio

INL See Note 1 ±0.3 ±0.5 LSB DNL See Note 2 ±0.03 ±0.5 LSB ZCE See Note 3 ±10 mV

GE See Note 4 ±0.6 % FSR

PSRR See Note 5 -68 dB Zero code error temperature coeffi cient Gain error temperature coefficient

DAC Output Specifications

Output voltage range Output load regulation

Power Supplies

Active supply current

Power down supply current

Dynamic DAC Specifications

Slew rate

Settling time

Glitch energy Signal to noise ratio

Signal to noise and distort i on rat i o

Total harmonic distort i on

Spurious free dynamic range

SNR fs = 400ksps, f

SINAD fs = 400ksps, f

THD fs

SFDR fs

= 2.048V and AVDD = DVDD = 3V ± 10%, V

REF

= 1.024V over

REF

8bits

See Note 6 10 ppm/°C See Note 6 10 ppm/°C

= 10kΩ 0 AVDD-0.1 V

2kΩ to 10kΩ load

0.1 0.25 % of FS

See Note 7

No load, V

= DVDD, V

AVDD = 5V,

= 2.048V Slow

REF

AVDD = 5V,

= 2.048V Fast

REF

AVDD = 3V,

= 1.024V Slow

REF

AVDD = 3V,

= 1.024V Fast

REF

= 0V

1.4 2.2

3.5 5.5

1.0 1.5

3.0 4.5

See Note 8

No load, all digital inputs

1 µA

0V or DVDD

Fast

Slow

1.0

5.0

See Note 9

To ±0.1LSB

Slow

Fast

8.5

2.5

See Note 10

Code 127 to 128 10 nV-s

OUT

= 1kHz,

57 dB

BW = 20kHz See Note 11

OUT

= 1kHz,

49 dB

BW = 20kHz See Note 11

= 400ksps, f

OUT

= 1kHz,

-50 dB

BW = 20kHz See Note 11

= 400ksps, f

OUT

= 1kHz,

60 dB

BW = 20kHz See Note 11

voltage

V/µs V/µs

µs µs

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 April 2001

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WM2627 Production Data

Test Conditions:

= 10kΩ, CL = 100pF. AVDD = DVDD = 5V ± 10%, V

recommended operating free-ai r temperature range (unless noted otherwise).

PARAMETER SYMBOL TEST CONDITIONS MI N TYP MAX UNIT Reference

Reference input resistanc e Reference input capacitanc e

REFIN REFIN

Reference feedthrough

Reference input bandwidth

Digital Inputs

High level input current Low level input current Input capacitance

Notes:

1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors ).

2. Differential non-linearity (DNL) is the difference between the meas ured and i deal 1LSB amplitude change of any adj acent two codes. A guarantee of monotonicity means the output voltage changes in the sam e direction (or remains cons tant) as a change in digital input code.

3. Zero code error is the voltage output when the DAC input code i s zero.

4. Gain error is the deviation from the ideal full scale output excludi ng t he effects of zero code error.

5. Power supply rejection ratio is measured by varying AVDD from 4.5V t o 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error.

6. Zero code error and Gain error temperature coefficients are norm al i sed to full scale voltage.

7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full sc al e out put voltage with a 10kΩ load.

8. I

is measured while continuous l y writing code 512 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current will increase.

9. Slew rate results are for the lower value of the rising and falling edge slew rates.

10. Settling time is the time taken for the signal t o settle to within 0.1LSB of the final measured value for both rising and falling edges. Limits are ensured by desi gn and characterisation, but are not production tested.

11. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f

= 2.048V and AVDD = DVDD = 3V ± 10%, V

REF

= 1.024V over

REF

10 MΩ

5pF

= 1VPP at 1kHz

REF

-75 dB

+ 1.024V dc, DAC code 0

= 0.2VPP + 1.024V dc

REF

DAC code 128

Slow

Fast

0.5 1

Input voltage = DVDD ±1 µA

Input voltage = 0V ±1 µA

3pF

generated with a sampling frequency f s

OUT

MHz MHz

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 April 2001

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WM2627 Production Data

SERIAL INTERFACE

WLtWH

SCLK

DIN

123451516

SUDtHD

D0D1D12D13D14D15

SUCSFS

NCS

WHFS

SUFSCLK

Figure 1 Timing Diagram

Test Conditions:

= 10kΩ, CL = 100pF. AVDD = DVDD = 5V ± 10%, V

= 2.048V and AVDD = DVDD = 3V ± 10%, V

REF

= 1.024V over

REF

recommended operating free-ai r t e mperature range (unless noted otherwise)

SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

SUCSFS

SUFSCLK

SUC16FS

Setup time NCS low before negative FS edge. Setup time FS low before firs t negative SCLK edge. Setup time, sixteenth negat i ve S CLK edge af ter FS

low on which D0 is sampled before rising edge of FS. Setup time, sixteenth positive SCLK edge (first

10 ns

8ns 10 ns 10 ns

positive after D0 sam pl ed) before NCS rising edge.

SUC16CS

If FS is used instead of the sixteenth positive edge to update the DAC, then the setup t i me is between the FS rising edge and the NCS rising edge.

WHCLK

WLCLK

SUDCLK

HDCLK

WHFS

Pulse duration, SCLK high. Pulse duration, SCLK low. Setup time, data ready before SCLK falling edge. Hold time, data held valid after SCLK falling edge. Pulse duration, FS high.

25 ns 25 ns

8ns

5ns 20 ns

SUC16CS

SUC16FS

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 April 2001

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WM2627 Production Data

TYPICAL PERFORMANCE GRAPHS

0.2

0.15

0.05

-0.05

-0.1

Integral Non-Lin earity (LSBs)

-0.15

-0.2

Figure 2 Integral Non-Linearity

0.4

AVDD = DVDD = 3V, V

0.35

0.3

0.25

0.2

OUTPUT VOLTAGE - V

0.15

0.1

0.05

012345678910

AVDD = DVDD = 5V, VREF = 2.048V, Slow Mode

0.1

0 32 64 96 128 160 192 224 256

DIGITAL CODE

= 1V, Input Code = 0

REF

ISINK - mA

Slow Fast

0.4

AVDD = DVDD = 5V, V

0.35

0.3

0.25

0.2

0.15

OUTPUT VOLTAGE - V

0.1

0.05

012345678910

= 2V, Input Code = 0

REF

ISINK - mA

Slow Fast

Figure 3 Sink Current AVDD = DVDD = 3V Figure 4 Sink Current AVDD = DVDD = 5V

2.054

AVDD = DVDD = 3V, V

2.052

2.05

2.048

2.046

2.044

2.042

OUTPUT VOLTAGE - V

2.04

2.038

2.036

2.034

2.032

012345678910

= 1V, Input Code = 1023

REF

ISOURCE - mA

Slow Fast

4.092

AVDD = DVDD = 5V, V

4.09

4.088

4.086

4.084

4.082

4.08

OUTPUT VOLTAGE - V

4.078

4.076

4.074

4.072

4.07 012345678910

= 2V, Input Code = 1023

REF

ISOURCE - mA

Slow Fast

Figure 5 Source Current AVDD = DVDD = 3V Fig u re 6 Sink Current AVDD = DVDD = 5V

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 April 2001

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WM2627 Production Data

DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor s tring network buffered with an op amp to convert 8-bit digital data to analogue voltage levels (see Bloc k Diagram ). The output volt age is det erm ined by the ref erence input voltage and the input code according to the following relationship:

CODE

()

REFIN=

Table 1 Binary Code Table (0V to 2V

out

1111 1111

1000 0001

1000 0000

0111 1111

0000 0001

0000 0000 0V

256

INPUT OUTPUT

()

255

()

REFV

256

129

()

REFV

256

128

REFREF VV =

256

127

()

REFV

256

()

REFV

256

Output), Gain = 2

REF

POWER ON RESET

An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circ uit protec tion and c an reli ably drive a 2k Ω load with a 100pF load capacitance.

EXTERNAL REFERENCE

The reference voltage input is buffered which makes the DAC input res istance independent of code. REFINAB and REFINCD pins have an input resistanc e of 10MΩ and an i nput capac itance of typically 5pF. The reference voltage determines the DAC full-scale output.

HARDWARE CONFIGURATION OPTIONS

DEVICE POWER DOWN

The device can be powered-down by pulling pin NPD (Pin 2) high. This powers down all DACs overriding their individual power down settings. This will reduce power consumption to typically 10nA. When the power down function is released the device revert s to the DAC code set prior to power down.

SIMULTANEOUS DAC UPDATE

The NLDAC pin (Pin 3) can be held high to prevent seri al word writes from updat ing the DAC lat ches . By writing new values to multiple DACs then pulling NLDAC low, all new DAC codes are loaded into the DAC latches simultaneously.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 April 2001

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WM2627 Production Data

SERIAL INTERFACE

To start transferring data, the devic e first has to be enabled with NCS set to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred, the next risi ng edge on SCLK or FS causes t he content of the shift regis ter t o be m oved to t he DAC holdi ng l atc h. If NLDAC is l ow, t he DA C l atc h will also be updated immedi at el y.

The serial interface of the devi ce can be used in two basic modes :

• four wire (with chip select)

• three wire (without chip select)

Using chip select (f our wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or m ic rocontroller). If t here is no need to have m ore t han one devi ce on the serial bus, then NCS c an be tied low.

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is:

max = MHz20

SCLK

The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling time to 8 bits limits the update rate for large input step transitions.

minWCLminWCH

SOFTWARE CONFIGURATION OPTIONS

The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D2 contains the 8-bit data word. D15-D12 hold the programmabl e opt i ons.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A1 A0 PWR SPD New DAC value (8 bits) 0 0 0 0

Table 2 Register Map

DAC ADDRESSING

A particular DAC (A, B, C, D) within the device is sel ected by A1 and A0 within the input word.

A1 A0 DAC ADDRESS

0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D

PROGRAMMABLE SETTLING TIME (SPD – BIT D12)

Settling time is a software selectable 2.5µs or 8.5µs, typical to within ±0.1LSB of final value. This is controlled by the value of SPD – Bi t D12 and an associated DA C address. A ONE defines a settling time of 2.5µs, a ZERO defines a settling time of 8.5µs for that DAC.

PROGRAMMABLE POWER DOWN

The power down function is controlled by PW R - Bit D13 and an assoc iated DAC address. A ZERO configures that DAC as active, a ONE configures t hat DAC into power down mode.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 April 2001

Page 10

WM2627 Production Data

APPLICATIONS INFORMATION

LINEARITY, OFFSET, AND GAIN ERROR

Amplifiers operating from a single supply can have positive or negative voltage offsets. With a positive offset, the output voltage changes on the first code transition. However, if the offset is negative, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. This is because with t he most negative supply rai l being ground, any attempt t o drive the output amplifier below ground will clamp the output at 0 V. The output voltage then remains at zero until the input code is s ufficiently high to overcom e the negative offs et voltage, result ing in the transfer function shown in Figure 7.

Output

Voltage

0 V

Negative

Offset

Figure 7 Effect of Negative Offset

This offset error, not the lineari ty error, produces the breakpoint. The transfer f unction would follow the dotted line if the output buf fer could drive below the ground rail.

DAC linearity is meas ured between zero-input code (all input bit s at 0) and full-sc ale code (all input s at 1), disregarding offset and full-scale errors. However, due to the break point in t he transfer f unction, single supply operation does not al low for adjustment when the offset is negati ve. In s uch cas es, t he linearity is therefore measured between full-scale and t he lowest code that produces a positive (nonzero) output voltage.

DAC code

POWER SUPPLY DECOUPLING AND GROUNDING

Printed circuit boards with separate analogue and digital ground planes deliver the best system performance. The two ground planes should be connected together at the low impedance power supply source. Ground currents should be managed so as to minimise voltage drops across the ground planes.

A 0.1µF decoupling capacitor should be connected between the positive supply and ground pi ns of the DAC, with short leads as close as possible t o the device. Us e of ferrite beads may further i solate the system analogue suppl y from the digital supply.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 April 2001

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WM2627 Production Data

PACKAGE DIMENSIONS

DT: 16 PIN TSSOP (5.0 x 4.4 x 1.0 mm)

916

E1 E

0.1

-C-

SEATING PLANE

GAUGE PLANE

DM013.B

0.25

Dimensions

Symbols

(mm)

MIN NOM M AX A A

b c D e E E

----- ----- 1.20

0.05 ----- 0.15

0.80 1.00 1.05

0.19 ----- 0.30

0.09 ----- 0.20

4.90 5.00 5.10

0.65 BSC

6.4 BSC

4.30 4.40 4.50

0.45 0.60 0.75

----- 8

REF: JEDEC.95, MO-153

NOTES: A. ALL LINEAR D IMENSIONS ARE IN MIL LIMETER S . B. THIS DRAWING IS SUBJECT TO CHANGE W ITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 April 2001