Datasheet WM2623ID, WM2623CD Datasheet (Wolfson)

WM2623

Low Power 8-bit Serial Input DAC

Production Data, October 2000, Rev 1.0

FEATURES

• 8-bit voltage output DAC

• Single supply from 2.7V to 5.5V

• Very low power consumption (3V supply):

- 900µW, slow mode

- 2.1mW, fast mode

- 3µW, standby mode

• DNL ±0.2 LSB, INL ±0.5 LSB (max)

• Monotonic over Temperature

• DSP compatible serial interface

• Programmable settling time of 3µs or 9µs typical

• High impedance reference input buffer

APPLICATIONS

• Digital Servo Control Loops

• Industri al P rocess Control

• Battery powered instruments and controls

• M achine and motion control devices

• Digital offset and gain adjustment

ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE

WM2623CD 0° to 70°C 8-pin SOIC

WM2623ID -40° to 85°C 8-pi n SOIC

DESCRIPTION

The WM2623 is an 8-bit volt age output, res istor s tring digi tal-to­analogue converter. It can operate with supply voltages
between 2.7V and 5.5V and can be powered down under
software control. Power down reduces current cons umption to
less than 1 µA.

The device has been designed for glueless interface t o industry
standard microprocessors and DSPs, including the TMS320
family. The W M2623 is programmed with a 16-bit serial word
including 4 control bits and 8 data bits.

Excellent performance is delivered with a typical DNL of

0.2LSBs. Monotonicity is guaranteed over the operating
temperature range. The settling time of the DAC is
programmable to allow for optimis ation of speed versus power
dissipation. The output stage is buffered by a rail-to-rail amplifier
with a gain of two, which features a Class A B output stage.

The reference voltage input features a high impedance buffer
which eliminates the need to keep the reference source
impedance low.

The WM2623 is available in an 8-pin SOIC package.
Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature range variants are availabl e.

BLOCK DIAGRAM TYPICAL PERFORMANCE

VDD

(8)

REFERENC E

8-BIT

DAC

LATCH

2-BIT

CONTROL

LATCH

INPUT BUFFER

X1

POWERDOWN/

SPEED

CONTROL

DAC
OUTPUT
BUFFER

X2

WM2623

REF(6)

DIN (1)

SCLK (2)

CSB (3)

FS (4)

16-BIT
SHIFT

REGISTER

AND

CONTROL

LOGIC

POWER-ON

RESET

(5)

GND

data

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK
Tel: [phone]
Fax: [phone]
Email: [email protected]
http://www.wolfson.co.uk

(7) OUT

0.1

AVDD = DVDD = 5V, V

0.08

0.06

0.04

0.02

0

DNL (LSBs)

-0.02

-0.04

-0.06

-0.08

-0.1
0 32 64 96 128 160 192 224 256

= 2.048V, Speed = Fast Mode, Load = 10kOhm/100pF

REF

DIGITAL CODE

Production Data Datasheets contain final

specifications current on publication date.

Supply of products conforms to Wolfson
Microelectronics’ Term s and Conditions.

2000 Wolfson Microelectronics Ltd.

WM2623 Production Data PIN CONFIGURATION

DIN

SCLK

NCS

FS

1
2
3
4

VDD

8

OUT

7

REF

6

GND

5

PIN DESCRIPTION

PIN NO NAME TYPE DESCRIPTION

1
2
3
4
5
6
7
8

DIN Digital input Serial data input

SCLK Digital input Serial clock input

NCS Digital input Chip select. This pin is active low.

FS Digital input Frame synchronisation for serial input dat a
GND Supply Ground
REF Analogue input Voltage reference input
OUT Analogue output DAC analogue output
VDD Supply Positi ve power supply

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are s tres s rat ings only. P erm anent damage to the device may be caus ed by cont inuous ly operati ng at
or beyond these limits. Device functional operating lim its and guaranteed performance s pecifications are gi ven under Electrical
Characteristics at the test conditions specified.

ESD Sensitive Device. Thi s device i s m anufactured on a CMOS process . It i s t herefore generi cally suscept ible
to damage from excessi ve stati c voltages . Proper ES D precautions mus t be tak en during handling and st orage
of this device.

CONDITION MIN MAX

Supply voltage, VDD to GND
Digital input voltage
Reference input voltage
Operating temperature range, T

A

WM2623CD
WM2623ID

Storage temperature
Lead temperature 1.6mm (1/16 inch) from package body f o r 10 seconds

-0.3V VDD + 0.3V

-0.3V VDD + 0.3V
0°C

-40°C

-65°C 150°C

7V

70°C
85°C

260°C

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Supply voltage
High-level digital input voltage

Low-level digital input voltage
Reference voltage to REF pin
Load resistance
Load capacitance

Serial clock frequency

Operating free-air temperature

Note:

Reference input voltages greater than VDD/2 will cause clipping for large DAC codes.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 October 2000

VDD 2.7 5.5 V

V
V

V

R
C

f

SCLK

T

IH
IL

REF

L
L

A

VDD = 2.7V to 5.5V 2 V
VDD = 2.7V to 5.5V 0.8 V

See Note

AGND VDD - 1.5 V

210 kΩ

100 pF

20 MHz

WM2623CD 0 70 °C

WM2623ID -40 85 °C

2

Production Data WM2623

ELECTRICAL CHARACTERISTICS

Test Conditions:

R

= 10kΩ, CL = 100pF. VDD = 5V ±10%, V

L

air temperature range (unless not ed otherwise).

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Static DAC Specifications

Resolution
Integral non-linearity
Differential non-linearity
Zero code error
Gain error
D.C. power supply rejection ratio
Zero code error temperature coeffi cient
Gain error temperature coefficient

DAC Output Specifications

Output voltage range
Output load regulation

Power Supplies

Active supply current

Power down supply current

Dynamic DAC Specifications

Slew rate

Settling time

Glitch energy
Signal to noise ratio
Signal to noise and distort i on rat i o
Total harmonic distort i on
Spurious free dynamic range

Reference

Reference input resistanc e
Reference input capacitanc e
Reference feedthrough

Reference input bandwidth

= 2.048V and VDD = 3V ±10%, V

REF

= 1.024V over recommended operati ng free-

REF

8bits

INL See Note 1 ±0.3 ±0.5 LSB
DNL See Note 2 ±0.07 ±0.2 LSB
ZCE See Note 3 ±10 mV

GE See Note 4 ±0.6 % FSR

PSRR See Note 5

í

See Note 6 10 ppm/°C
See Note 6 10 ppm/°C

0 VDD - 0.1 V

2kΩ to 10kΩ load

0.1 0.25 % FS

See Note 7
No load, DAC value = 128,
all digital inputs 0V or VDD

I

DD

VDD = 5V, V

REF

= 2.048V

0.4 0.6 mA

Slow Mode

VDD = 5V, V

REF

= 2.048V

0.9 1.35 mA

Fast Mode

VDD = 3V, V

= 1.024V,

REF

0.3 0.45 mA

Slow Mode

VDD = 3V, V

= 1.024V,

REF

0.7 1.1 mA

Fast Mode (See Note 8)

1 µA

SR DAC output 10%-90%

Slow
Fast

0.9

3.6

See Note 9

t

s

DAC output 10%-90%

Slow
Fast

9
3

20

5.5

See Note 10

DAC Code 127 to 128 10 nV-s

SNR 57 dB

SNRD 49 dB

THD

SPFDR

R

REFIN

C

REFIN

= 400kSPS,

f

s

f

= 1.1kHz,

OUT

BW = 20kHz
See Note 11

V

= 1VPP at 1kHz

REF

í

60 dB

10 MΩ

5pF

-75 dB

+ 1.024V dc, DAC code 0

V

= 0.2VPP + 1.024V dc

REF

DAC code 128

Slow
Fast

0.525

1.3

dB

V/µs
V/µs

µs
µs

dB

MHz
MHz

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 October 2000

3

WM2623 Production Data

Test Conditions:

R

= 10kΩ, CL = 100pF. VDD = 5V ±10%, V

L

air temperature range (unless not ed otherwise).

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital Inputs

High level input current
Low level input current
Input capacitance

Notes:

1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding t he
effects of zero code and f ul l scale errors).

2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplit ude change of any adjac ent t wo
codes. A guarantee of monotonicity means the output voltage al ways changes in the same direc tion (or remains cons tant) as
the digital input code.

3. Zero code error is the voltage output when the DAC input code i s zero.

4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.

5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5. 5V and measuring the proportion of this signal
imposed on the zero code error and the gain error.

6. Zero code error and Gain error temperature coefficients are norm al i sed to full scale voltage.

7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is
expressed as a percentage of the full s cale output voltage with a 10kΩ load.

8. I

is measured while continuous ly writing code 128 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will

DD

increase.

9. Slew rate results are for the lower value of the rising and falling edge slew rates

10. Settling time is the tim e taken for the signal to settle t o within 0.5LSB of the final measured value for bot h rising and falling
edges. Limits are ens ured by design and characterisation, but are not production tested.

11. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f
frequency fs

.

= 2.048V and VDD = 3V ±10%, V

REF

I

IH

I

IL

C

I

Input voltage = VDD 1 µA

Input voltage = 0V

= 1.024V over recommended operati ng free-

REF

í

3pF

generated with a sampling

OUT

µA

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 October 2000

4

Production Data WM2623

SERIAL INTERFACE

t

WLtWH

SCLK

DIN

123451516

t

SUDtHD

D0D1D12D13D14D15

t

SUCSFS

NCS

t

WHFS

t

SUFSCLK

FS

Figure 1 Timing Diagram

Test Conditions:

R

= 10kΩ, CL = 100pF. VDD = 5V ±10%, V

L

= 2.048V and VDD = 3V ±10%, V

REF

= 1.024V over recommended operati ng

REF

free-air temperature range (unless noted otherwise).

SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

t

SUCSFS

t

SUFS

t

SUC16FS

Setup time NCS low before falli ng FS edge.
Setup time FS low before firs t falling SCLK edge.
Setup time, 16th falling SCLK edge after FS low on

which data bit D0 is sampled bef ore ri sing edge of FS.

10 ns

8ns

10 ns

Setup time, 16th rising SCLK edge (first af t e r dat a bi t

t

SUC16CS

D0 sampled) before NCS rising edge. If FS is used
instead of the 16

th

rising edge to update the DAC, this

10 ns
setup time is between the FS ri sing edge and the NCS
rising edge.

t

WH

t

WL

t

SUD

t

HD

t

WHFS

Pulse duration, SCLK high.
Pulse duration, SCLK low.
Setup time, data ready before SCLK falling edge.
Hold time, data held valid after SCLK falling edge.
Pulse duration, FS high.

25 ns

25 ns

8ns
5ns

20 ns

t

SUC16CS

t

SUC16FS

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 October 2000

5

WM2623 Production Data TYPICAL PERFORMANCE GRAPHS

0.12

AVDD = DVDD = 5V, VREF = 2.048V, Speed = Fast Mode, Load = 10kOhm/100pF

0.08

0.04

0

INL (LSBs)

-0.04

-0.08

-0.12
0 32 64 96 128 160 192 224 256

Figure 2 Integral Non-Linearity

DIGITAL CODE

0.4

VDD = 3V, V

0.35

0.3

0.25

0.2

0.15

OUTPUT VOLTAGE - V

0.1

0.05

0

012345678910

= 1V, Input Code = 0

REF

ISINK - mA

Slow Fast

0.4

VDD = 5V, V

0.35

0.3

0.25

0.2

0.15

OUTPUT VOLTAGE - V

0.1

0.05

0

012345678910

= 2V, Input Code = 0

REF

ISINK - mA

Figure 3 Sink Current VDD = 3V Figure 4 Sink Current VDD = 5V

OUTPUT VOLTAGE - V

2.055

2.045

2.035

2.06

2.05

2.04

VDD = 3V, V

= 1V, Input Code = 4095

REF

OUTPUT VOLTAGE - V

4.095

4.09

4.085

4.08

4.075

4.1

VDD = 5V, V

= 2V, Input Code = 4095

REF

Slow Fast

2.03

2.025
012345678910

ISOURCE - mA

Slow Fast

4.07

4.065
012345678910

ISOURCE - mA

Slow Fast

Figure 5 Source Current VDD = 3V Figure 6 Source Current VDD = 5V

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 October 2000

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Production Data WM2623

DEVICE DESCRIPTION

GENERAL FUNCTION

The WM2623 is an 8-bit, vol tage output DAC operating from a s ingle supply. The device uses a
resistor string network buffered with an op amp to convert 8-bit di gital data to analogue voltage
levels (see Block Diagram ). The output voltage is determ ined by the reference input volt age and
the input code according to t he f ol l owing relat i onship:

2

V

out

INPUT OUTPUT

1111 1111

::

1000 0001

1000 0000

0111 1111

::

0000 0001

0000 0000 0V

Table 1 Binary Code Table (0V to 2V

CODE

V

()

REFIN=

256

2

255

2

()

REFV

256

129

2

()

REFV

256

128

()

256

127

2

()

REFV

256

2

()

REFV

256

Output), Gain = 2

REF7

REFREF VV =

1

POWER ON RESET

An internal power-on-reset circuit resets the DAC register to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with s hort circuit protect ion and can reliably drive a
2kΩ load with a 100pF load capacitance.

EXTERNAL REFERENCE

The reference voltage input is buffered which makes the DAC input resistance independent of
code. The REF pin has an input resis tanc e of 10MΩ and an input capacitance of typic ally 5pF. The
reference voltage determines the DAC full-scale output.

SERIAL INTERFACE

Before writing any data to the W M2623, the device must firs t be enabled by setting CSB to low.
Then, a falling edge of FS starts shif ting t he data bit-per-bit (s tart ing with the MSB) into the internal
register on the falling edges of SCLK. After 16 bit s have been transferred, t he next rising edge on
SCLK or FS causes the content of the shift regist er to be moved to the DAC latc h which updates
the voltage output to the new level.

The serial interface of the devi ce can be used in two basic modes:

• four wire (with chip select)

• three wire (without c hi p select)

Using the chip select pin CSB (four wire mode), it is possible to have more than one device
connected to the serial port of the data source (DSP or microc ontroller). I f there is no need to have
more than one device on the serial bus, CSB can be tied low.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 October 2000

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WM2623 Production Data

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial cloc k rate is:

f

Since a data word contains 16 bits, the sample rate is limited to

f

However, the DAC settling time to 8 bits accurac y limits the response tim e of the analogue output
for large input step transit i ons.

SCLK

s

max

max

=

=

16

1

tt

+

WLWH

minmin

1

()

tt

+

WLWH

minmin

SOFTWARE CONFIGURATION OPTIONS

Table 2 shows the compositi on of a 16 bit data word. D11-D4 contains the 8-bit data word, and
D14-D13 hold the programmable options. Bits D15, D12, and D3 through D0 should be set to
ZERO.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 SPD PWR 0 New DAC value (8 bits) 0 0 0 0

Table 2 Register Map

PROGRAMMABLE SETTLING TIME

SPD (Bit 14) allows for software control of the converter s peed. A ONE selects the fast mode,
where typical settling tim e to within ±0.5LSB of the final value i s 3µs. a ZERO puts the device into
the slow mode, where typical settl i ng time is 9µs.

PROGRAMMABLE POWER DOWN

The power down function is controlled by PWR (Bit 13). A ZERO configures the devi ce as active,
or fully powered up, a ONE configures the devic e into power down mode. When the power down
function is released the device reverts to the DAC code set prior to power down.

MHz

20

=

MHz

25.1

=

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 October 2000

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Production Data WM2623

APPLICATIONS INFORMATION

LINEARITY, OFFSET, AND GAIN ERROR

Amplifiers operating from a single supply can have positive or negative voltage offsets. With a
positive offset, t he output voltage changes on the first code transition. However, if the offset is
negative, the output voltage may not change with the firs t c ode, depending on t he m agnit ude of t he
offset voltage. This is because with t he most negative supply rail being ground, any attempt to
drive the output amplifier below ground will clamp the output at 0 V. The output voltage then
remains at zero until the input code is suf ficiently high to overcome the negative offset voltage,
resulting in the transfer f unction shown in Figure 7. <file negative_offset.emf, below>

Output

Voltage

0 V

Negative

Offset

Figure 7 Effect of Negative Offset

This offset error, not t he linearity error, produces t he breakpoint. The t ransfer funct ion would fol low
the dotted line if the output buf fer could drive below the ground rail.

DAC linearity is measured between zero-input code (all input bits at 0) and full-scale code (all
inputs at 1), disregarding off set and ful l sc ale errors . However, due t o t he breakpoint in the trans fer
function, single supply operati on does not all ow for adjustm ent when the offs et is negat ive. In s uch
cases, the linearity is theref ore measured between full-scal e and the lowest code that produces a
positive (non-zero) output voltage.

DAC code

POWER SUPPLY DECOUPLING AND GROUNDING

Printed circuit boards with s eparate analogue and digital ground planes deliver the best s ystem
performance. The two ground planes should be connected together at the low im pedance power
supply source. Ground currents should be managed so as to minim ise voltage drops across the
ground planes.

A 0.1µF decoupling capacitor should be connected between the posit ive supply and ground pins of
the DAC, with short leads as c lose as possible to the device. Use of ferrite beads may further
isolate the system analogue supply from the digit al supply.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 October 2000

9

WM2623 Production Data PACKAGE DIMENSIONS

D: 8 PIN SOIC 3.9mm Wide Body

e

D

A1

A

B

58

41

E H

-C-

h x 45

α

DM009.B

L

o

Symbols

0.10 (0.004)

Dimensions

(mm)

SEATING PLANE

Dimensions

(Inches)

MINMAXMINMAX
A
A

1

B
C
D
e
E
h
H
L

α

1.35 1.75 0.0532 0.0688

0.10 0.25 0.0040 0.0098

0.33 0.51 0.0130 0.0200

0.19 0.25 0.0075 0.0098

4.80 5.00 0.1890 0.1968

1.27 BSC 0.050 BSC

3.80 4.00 0.1497 0.1574

0.25 0.50 0.0099 0.0196

5.80 6.20 0.2284 0.2440

0.40 1.27 0.0160 0.0500

o

0

o

8

o

0

o

8

REF: JEDEC.95, MS-012

NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

C

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 October 2000

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