Datasheet WM2331CDT-V, WM2331IDT-V Datasheet (Wolfson)

WM2331

10-bit 30MSPS ADC with PGA and Clamp

Production Data, April 2001, Rev 1.4

DESCRIPTION

The WM2331 is a high speed, 10-bit pipeline analogue-to­digital converter (ADC) with on-chip programmable gain
amplifier (PGA) and clamp circuit, and internal voltage
references. Conversion is controlled by a single clock i nput.

The device has a high bandwidth differential sample and
hold input, which gives excellent common-mode noise
immunity and low distort ion. Alternatively, it can be driven
in single ended fashion with an optional voltage c lamp for
DC restoration that can take its reference from an on-chip
10-bit DAC or an external source.

The WM2331 provides internal reference voltages for
setting the ADC full-scale range without the requi rement for
external circuitry. However, it can also accept external
references for applications where com mon or hi gh-precisi on
references are required.

A bidirectional 10-bit parallel interface is used both to
control the device and to read ADC conversion data. ADC
data can be output in unsigned binary or two’s c omplement
format. An out-of-range out put pin indicates when the input
signal is outside the converter’s range.

The WM2331 operates with independent analogue and
digital supplies of 3V to 5.5V and is supplied in a 28-pin
TSSOP package.

FEATURES

• 10-bit resolution ADC

• 30MSPS conversion rate

• Programmable Gain Amplifier (PGA)

• Built in clamp f unction (DC restore) with 10-bit DAC

• Adjustable internal voltage references

• Wide Input Bandwidth - 150MHz

• Unsigned Binary or Two’s complement output format

• Programmable via parallel i nterface

• Independent analogue and digital supplies , 3V to 5.5V

• Low power - 92mW typical at 3.0V supplies

• Powerdown mode to 3mW typi cal

• 28-pin TSSOP package

APPLICATIONS

• Composite Video Digit i sation

• Digital Copiers

• Digital Video Cameras

• Set Top Box (STB)

• IF and Baseband Digitisat i on

• Medical Imaging

• High Speed Data Acquisiti on

BLOCK DIAGRAM

CLAMP CLAMPIN

ON-CHIP

AGNDAVDD

M
U
X

CLAMP

AMPLIFIER

AIN

S/H

REFTS

REFBS

REFSENSE

VREF

MODE

PGA

REFERENCE
GENERATOR

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edi nburgh, EH8 9NX, UK
Tel: [phone]
Fax: [phone]
Email: [email protected]
www.wolfsonmicro.com

CLAMP

LEVEL

DAC

ADC

Core

REFBF REFTF

CONTROL

REGISTERS

INPUT/

OUTPUT

BUFFERS

TIMING

CONTROL

WM2331

WR

DIO[9:0]

OVR

OEB

CLK

DVDD
DGND

Production Data datasheets contain final

specifications current on publication date.

Supply of products conforms to Wol fson
Microelectronics’ Term s and Conditions.

 2001 Wolfson Microelectronics Ltd.

WM2331 Production Data

PIN CONFIGURATION ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE

AGND
DVDD

DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7 CLAMP
DIO8

DIO9

OVR OEB

DGND

1
2
3
4
5
6
7
8
9
10
11
12
13

AVDD

28

AIN

27

VREF

26

REFBS

25

REFBF

24

MODE

23

REFTF

22

REFTS

21

CLAMPIN

20
19

REFSENSE

18

WR

17
16

CLK

1514

WM2331CDT/V 0 t o +70oC 28-pin TSSOP

WM2331IDT/V -40 to +85oC

28-pin TSSOP

PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 AGND Ground
2 DVDD Supply
3 DIO0 Digital Input/Output
4 DIO1 Digital Input/Output
5 DIO2 Digital Input/Output
6 DIO3 Digital Input/Output
7 DIO4 Digital Input/Output
8 DIO5 Digital Input/Output

9 DIO6 Digital Input/Output
10 DIO7 Digital Input/Output
11 DIO8 Digital Input/Output
12 DIO9 Digital Input/Output
13 OVR Digital Output
14 DGND Ground
15 CLK Analogue Input
16 OEB Digital Input

17 WR Digital Input
18 REFSENSE Analogue Input
19 CLAMP Digital Input
20 CLAMPIN Analogue Input
21 REFTS Analogue Input/Output
22 REFTF Analogue Input /Output
23 MODE Analogue Input
24 REFBF Analogue Input/Output
25 REFB S Analogue Input/ Output
26 VREF Analogue Input/Output
27 AIN Analogue Input
28 AVDD Supply

Negative Analogue Supply
Positive Digital S uppl y
Digital input/output bit 0 (LSB)
Digital input/output bit 1
Digital input/output bit 2
Digital input/output bit 3
Digital input/output bit 4
Digital input/output bit 5
Digital input/output bit 6
Digital input/output bit 7
Digital input/output bit 8
Digital input/output bit 9 (MS B )
Overrange output (tri-state)
Negative Digital Supply
Clock input

Output enable bar – low to enable DIO[9:0] and OVR
Write strobe
VREF mode control
Clamp control – high to enable c l amp amplifier
Clamp reference input
Top reference sense
Top reference force
Input mode select
Bottom reference force
Bottom reference sense
Reference voltage
Analog Input
Positive Analogue Supply

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

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Production Data WM2331

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are s tres s rat ings only. P erm anent damage to the device may be c aused by c onti nuously operat ing at
or beyond these limits. Device functional operating lim its and guaranteed performance s pecifications are gi ven under Electrical
Characteristics at the test conditions s pecified.

ESD Sensitive Device. Thi s device i s m anufactured on a CMOS process . It i s t herefore generi cally suscept ible
to damage from excessi ve stati c voltages . Proper ES D precautions mus t be tak en during handling and st orage
of this device.

As per JEDEC specif ic ations A112 and A 113, t his product requires s pec ifi c s torage c onditi ons pri or to s urfac e m ount ass em bly. I t
has been classified as having a Moisture Sensitivity Level of 2 and as s uch will be supplied in vacuum-sealed moisture barrier
bags.

CONDITION MIN MAX

Digital supply voltage, DV DD to DGND
Analogue supply voltage, AVDD to AGND
Supply voltage difference, A VDD to DVDD
Ground difference, AGND to DGND
Voltage range digital inputs (DI O [ 9:0], WR, CLAMP, OEB)
Voltage range analogue inputs (REFTS, REFBS, RE FTF, REFBF, AIN,

VREF, REFSENSE, CLK, MODE)
Operating temperature range, T

Storage temperature
Lead temperature (1.6mm from package body for 10 seconds)

A

WM2331CDT
WM2331IDT

-0.3V +6.5V

-0.3V +6.5V

-6.5V +6.5V

-0.3V +0.3V
DGND - 0.3V DVDD + 0.3V
AGND - 0.3V AVDD + 0. 3V

0°C+70°C

-40°C+85°C

-65°C +150°C
+300°C

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN NOM MAX UNIT

Digital supply range
Analogue supply range
Ground
Clock frequency
Clock duty cycle
Operating Free Air Temperature

DVDD 3.0 3.0 5.5 V
AVDD 3.0 3.0 5.5 V

DGND,AGND 0 V

f

CLK

T

A

WM2331C
WM2331I

530MHz

45 50 55 %

070°C

-40 85 °C

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WM2331 Production Data
ELECTRICAL CHARACTERISTICS

Test Conditions:

AVDD = DVDD = 3.0V, f
T

= T

to T

A

MIN

, unless otherwise stated.

MAX

= 30MHz, 50% duty cycle, MODE = AVDD, RE FTS = 2.5V, REFBS = 0.5V, P G A gai n = 1.0,

CLK

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DC Accuracy

Integral nonlinearity
Differential nonlinearity
Offset error
Gain error
Missing codes

INL ±1.0 ±2.0 LSB

DNL ±0.3 ±1.0 LSB

0.4 2.0 % of FS

1.4 3.5 % of FS

No missing codes guarant eed

Analogue Input Signal to AIN pin

MODE = AGND REFBS REFTS

Input signal range for unity PGA
gain (see Note 1)

MODE = AVDD / 2,

V

fixed

CMCS

V

CMCS

VREF/2

-

V

CMCS

VREF/2

+

V

MODE = AVDD REFBS REFTS
AIN voltage limits
Switched input capacitance
Analogue input bandwidth
DC leakage current

-3dB amplitude 150 MHz

± Full-scale input ±100 µA

AGND AVDD V

1.2 pF

Conversion Characteristics

Conversion frequency
Pipeline delay
Aperture delay

Aperture jitter

f

CLK

t

530MHz

3

A

4.0 ns

cycles of

CLK

2.0 ps rms

Dynamic Performance

Effective number of bi ts

Spurious free dynamic range

Total harmonic distort i on

Signal to noise ratio

Signal to noise and distorti on
ratio

ENOB

SFDR

THD

SNR

SNDR

fIN = 3.5MHz 8.2 9.0

f

= 15MHz 7.7

IN

fIN = 3.5MHz 55 60

f

= 15MHz 48

IN

fIN = 3.5MHz -58 -54.7

f

= 15MHz -47

IN

fIN = 3.5MHz 51.2 56

f

= 15MHz 53

IN

fIN = 3.5MHz 51.1 56

f

= 15MHz 48

IN

bits

dB

dB

dB

dB

PGA

Gain range (linear scale)
Gain step size (linear scal e)
Gain error from nominal

0.5 4 V/V

0.5 V/V
3%

Clamp

Clamp DAC resolution
Clamp DAC output voltage
Clamp DAC DNL
Clamp DAC DNL
External clamp reference on

REFBF REFTF V

-1 1 LSB

0.1 AVDD - 0.1 V

10 bits

±1 LSB

CLAMPIN
Clamp output voltage error

-40 40 mV

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Production Data WM2331

Test Conditions:

AVDD = DVDD = 3.0V, f
T

= T

to T

A

MIN

, unless otherwise stated.

MAX

= 30MHz, 50% duty cycle, MODE = AVDD, RE FTS = 2.5V, REFBS = 0.5V, P G A gai n = 1.0,

CLK

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Analogue Reference Inputs / Outputs in Top/Bottom Mode (MODE=AVDD)

Bottom reference voltage
applied to REFBS

Top reference voltage applied to
REFTS

Differential reference input
(REFTS – REFBS)

Reference input common mode
(REFTS + REFBS) / 2
Switched input capacitance on

REFBS
Switched input capacitance on

REFTS
REFBF output voltage

REFTF output voltage

V

V

TB

CMTB

0 AVDD - 1 V

1 AVDD V

12V

0.5 AVDD - 0.5 V

0.6 pF

0.6 pF

(AVDD -

V

)/2

TB

(AVDD +

V

)/2

TB

V

V

Analogue Reference Inputs / Outputs in Centre-Span Mode (MODE=AVDD/2)

Reference voltage derived or
applied to VREF

REFBF output voltage

REFTF output voltage
Non-AIN side of differenti al i nput

applied to REFTS and REFBS

V

CMCS

(Note 2) 0.5 AVDD - 0.5 V

12V

(AVDD -

VREF)/2
(AVDD +

VREF)/2

V

V

Analogue Reference Inputs / Outputs in Full External Reference Mode (MODE=AGND) (Note 3)

Differential reference volt age
applied (REFTF – REFBF)

Reference input common mode
(REFTF + REFBF) / 2
Reference input resistanc e

AVDD = 3.0V 1.3 1.5 1.7 V
AVDD = 5.0V 2.0 2.5 3.0 V

12V

680 Ω

VREF Input / Output specifications

Internal 1V reference to VREF
Internal 2V reference to VREF
External reference applied to

VREF pin in centre-span m ode
Input impedance in cent re-span

mode

REFSENSE = VREF 0.95 1.0 1.05 V

REFSENSE = AGND 1.9 2.0 2.1 V

REFSENSE = AVDD,

MODE = AVDD / 2

REFSENSE = AVDD,

MODE = AVDD / 2

12V

18 kΩ

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

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WM2331 Production Data

Test Conditions:

AVDD = DVDD = 3.0V, f
T

= T

to T

A

MIN

, unless otherwise stated.

MAX

= 30MHz, 50% duty cycle, MODE = AVDD, RE FTS = 2.5V, REFBS = 0.5V, P G A gai n = 1.0,

CLK

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Power Supplies

Analogue supply current

Digital supply current
Standby power consumption

(digital and analogue combined)

MODE = AGND,

REFSENSE = AVDD

I

AVDD

MODE = AVDD/2,

REFSENSE = VREF

MODE = AVDD,

REFSENSE = AVDD

I

DVDD

(STBY) 3 5 mW

I

VDD

CL = 10pF 6 mA

31 45 mA

37 mA

36 mA

Digital Logic Levels (CMOS Levels)

Input LOW level
Input HIGH level
Output LOW
Output HIGH

V

IL

V

IH

V

OL

V

OH

(Note 2) 0.2 x VDD V
(Note 2) 0.8 x VDD V

IOL = -50µA0.2V

IOH = 50µA VDD – 0.2 V

Notes

1. V

can be applied as a single voltage source to REFTS and REFBS with these two pins connected together.

CMCS

Alternatively the com mon mode of the input c an be set by applying different voltage s ources to these two pins, in
which case the common mode voltage is effectively the average of these two voltages, V

= (REFTS + REFBS)/2.

CMCS

2. Digital input and output levels refer to the supply used for the input /output buffer on the relevant pin. CLK and MODE
refer to the AVDD supply, al l other digital input/output ref ers to the DVDD supply.

3. In full external reference mode the REFTF and REFTS pins should be shorted together, and the REFBF and REFB S
pins should be shorted together. P l ease refer to device operation examples i n t he devi ce description secti on of the
datasheet.

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Production Data WM2331

OEB

t

t

OEW

WRP

t

WOE

WR

t

DH

hi - Z

t

DEN

Output

DIO[9:0]

Output

Note: All timing measurements are based on 50% of edge transition

Figure 1 Write Timing

t

DZ

hi - Z

t

DS

Input

t

CL

Sample 2

Pipeline Delay

Sample 3

Sample 4

Sample 5

t

D

Sample 1 Sample 2

Analogue Input

at AIN

CLK

Digital Output

Sample 1

t

CLK

t

CH

Note: All timing measurements are based on 50% of edge transition

Figure 2 Output Timing

Test Conditions:

AVDD = DVDD = 3.0V, f
T

= T

to T

A

MIN

, unless otherwise stated.

MAX

= 30MHz, 50% duty cycle, MODE = AVDD, RE FTS = 2.5V, REFBS = 0.5V, P G A gai n = 1.0,

CLK

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Clock

Clock period
Clock high time
Clock low time

t

t
t

CLK

CH
CL

33 ns
15 16.5 ns
15 16.5 ns

Timing

Pipeline delay
Clock to data valid
Output disable to hi-Z output
Output enable to data valid
Output disable to write enable
Write disable to output enable
Write pulse width
Input data setup tim e
Input data hold time

t

t

DEN

t

OEW

t

WOE

t

WRP

t
t

t

D

DZ

020ns

020ns
12 ns
12 ns
15 ns

DS
DH

5ns

5ns

3 CLK cycles

25 ns

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

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WM2331 Production Data
TYPICAL SYSTEM PERFORMANCE

1

AVDD = DVDD = 3V, fS = 30 MSPS

0

-1
0 128 256 384 512 640 768 896 1024

DIGITAL CODE

Figure 3 Differential Non-Linearity

AVDD = DVDD = 3V, fS = 30MSPS

Differential Non-Linearity (LSBs)

0.75

0.5

0.25

-0.25

-0.5

-0.75

3

2

1

0

-1

Integral Non-Linearity (LSBs)

-2

-3
0 128 256 384 512 640 768 896 1024

DIGITAL CODE

Figure 4 Integral Non-Linearity

0

-20

-40

-60

-80

FFT (dB)

-100

-120

-140
03691215

AVDD = DVDD = 3V, fIN = 3.58MHz, -1dB FS

Frequency (MHz)

Figure 5 Fast Fourier Transform (FFT)

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

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Production Data WM2331

DEVICE DESCRIPTION

INTRODUCTION

The WM2331 is a high speed analogue-to-digital converter (ADC) with on-chip analogue pre­processing and reference generation, designed for appl ications such as com posite vi deo digit isati on,
digital copiers and and high speed data acquisition. The chip archi t ecture consists of:

• High bandwidth sample and hold input, which can operate in differential or single-
ended mode

• Programmable gain am pl i f i er (PGA)

• Voltage clamp for DC restoration that can take its reference from an on-chip 10-bit

DAC or an external source

• 10-bit, 30MSPS pipeline analogue-to-digital converter (ADC) core

• On-chip reference generator and reference buffer (external references can also be

used for applications where com mon or high precision references are requi red)

• Bidirectional 10-bit parallel interface to read ADC conversion data and control the
device. ADC data can be output i n unsigned binary or two’s complement format. An
out-of-range output pin indicates when the input signal is outside the c onverter’s range

ANALOGUE SIGNAL PATH

The WM2331 analogue signal path c onsi st s of a DC clamp with a 10-bit clamp l evel DAC (dis cus sed
under ‘DC Clam p’, below), a high-bandwidth sample and hold uni t followed by a programmabl e gain
amplifier (PGA) and a fast 10-bit pipelined analogue to digital converter (ADC core).

REFTF

AIN

REFTS

REFBS

Figure 6 Analogue Input Signal Flow

Figure 6 shows the signal flow through the sample and hold unit and the PGA to the ADC core,
where the process of analogue to digital conversion is performed against the ADC reference
voltages, REFTF and REFBF (their generation from internal or external reference sources is
described later).

+1

-1/2

-1/2

SAMPLE

AND

HOLD

VP+

VP-

PGA

VQ+

ADC

CORE

VQ-

REFBF

SAMPLE AND HOLD

The analogue input voltage V
coupled with DC restoration using the WM2331 clamp ci rcuit.

The differential sample and hol d processes V
and REFBS pins, and produces a differential output V

VVV −=

MINP

For single-ended input signals, VM is a constant voltage; usually the AIN mid-scale i nput voltage.
However, in differential mode (see ‘ADC Reference Modes’, below), REFTS and REFBS can be
connected together to operate with AIN as a complement ary pai r of di fferential inputs.

is applied to the AIN pin, either DC coupled, AC coupled, or AC

IN

with respect to the voltages appli ed to the REFTS

IN

= VP+ - VP- given by:

P

REFBSREFTS

where

V

=

M

+

2

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

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WM2331 Production Data

PROGRAMMABLE-GAIN AMPLIFIER

VP is amplified by the P GA and fed into the ADC as a differential voltage VQ = VQ+ - V

()

VVGainVGainV −×=×=

MINPQ

The PGA gain defaults to 1.0 at power-up, but can be programmed from 0. 5 t o 4.0 in steps of 0.5.

ANALOGUE-TO-DIGITAL CONVERTER

Regardless of the reference conf iguration, VQ is digitised against A DC Reference Voltages REFTF
and REFBF, full scale values of V

=

V

QFS

+

−

2

REFBFREFTF

being given by:

Q

and

V

QFS



−=



−



Q-

REFBFREFTF

−

2






Attempts to convert VQ voltages outside the range of V
by driving the OVR output pin hi gh. If V
than V

QFS+

SIGNAL CHAIN SUMMARY

Combining the above equations and referri ng back to the input, the positive and negative full-scale
voltages at the AIN pin are:

Therefore the input signal span is gi ven by:

In order to match the ADC input range to the input signal amplit ude, REFTF and REFBF should be
set such that:

ADC REFERENCE MODES

The WM2331 supports three basic m odes of ref erence generat ion, selec ted by t he volt age applied t o
the MODE pin. These are summarised and explained in Table 1.

, the output code is 1023.

VV

+=

MINFS

+

VV

INFSINFS

×

2

=−

−+

REFBFREFTF

−

Gain

Gain

is less than V

Q

REFBFREFTF

−

INFSINFS

−+

to V

QFS-

, the ADC output code is 0. If VQ is greater

QFS-

and

GainVVREFBFREFTF

×−=−

)(

are signalled to the application

QFS+

REFBFREFTF

VV

−=

MINFS

−

−

Gain

×

2

In differential, Centre Span and Top/Bottom m odes, the internally generated ADC references are
intened solely for WM2331 internal use and REFTF and REFBF must not be used as voltage
references for any other device in t he appl i cation.

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Production Data WM2331

MODE

MODE FUNCTION COMMENTS

PIN

AGND Full external

AVDD/2 Differential

REFTF+=

REFTF−=

AVDD Top/Bottom

REFTF−+=

REFBF−−=

Table 1 WM2331 Reference Generation Modes

FULL EXTERNAL REFERENCE MODE (MODE = AGND)

When MODE is connected to AGND, the WM2331 operates in f ull external reference mode. The
internal reference buffer is powered down and bypassed, so that the ADC core takes the user­supplied reference voltages at pins REFTS and REFBS (REFTS and REFBS are internally
connected to REFTF and REFBF). The m ean of REFTF and RE FBF m us t be equal t o AVDD/ 2. Only
single-ended input is possi bl e i n t hi s mode.

REFTSREFTF =

On-chip reference generator and reference buffer are

not used.

REFBSREFBF =

V

can be internally or externally generated.

VAVDD

REF

2

VAVDD

REF

2

()

REFBSREFTSAVDD

2

()

REFBSREFTSAVDD

REF

REFTS and REFBS are joined together and connected

either to the negative end of the input signal (true

differential mode) or to the AIN mid-scale vol t age

(centre-span mode).

On-chip reference generator is not us ed. Reference

buffer centers external reference volt ages around

AVDD/2.

2

REFTF

AIN

REFTS

REFBS

+1

-1/2

-1/2

SAMPLE

AND

HOLD

INTERNAL

REFERENCE

BUFFER

PGA

ADC

CORE

REFBF

Figure 7 ADC Reference Generation in Full External Mode

The full external mode of operation is us eful when the application requires m ore accurate or lower
drift reference voltages than the W M2331 can provide, or when devices need to share common
reference voltages for best ADC m atching. It also off ers the possibility of us ing REFTS and REFBS
as sense lines to drive the REFTF and REFBF lines (Kelvin mode) to eliminate any volt age drops
from remote references within the system (see Figure 9). In Kelvi n configurations, take care when
choosing the external op-amps to ensure that they can drive large capacitive loads without
oscillating.

Although the on-chip reference generator i s not used by t he WM2331 in full external m ode, it s out put
is available on the VREF pin and can be us ed by other parts of the syst em. Note that in addi tion to
the internal connections from REFTS to REFTF and REFBS to REFB F, external wire connections
must also be made as shown in Figure 8 to minimis e resistance (except in Kelvin m ode).

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

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WM2331 Production Data

+FS

AVDD/2

-FS

DC SOURCE =
AVDD/2 + [(+FS) - (-FS)] * GA IN/2

DC SOURCE =
AVDD/2 - [(+FS) - (-FS)] * GAIN/2

0.1µF

0.1µF

REFBS

REFTF

0.1µF10µF

AIN

REFTS

REFBF

AVDD

REFSENSE

MODE

Figure 8 Full External Reference Mode (Reference Generator Disabled)

AVDD

REFSENSE

MODE

0.1µF

-

REFT =
AVDD/2 + [(+FS) - (-FS)] * GAIN/2

REFB =
AVDD/2 - [(+FS) - (-FS)] * GAIN/2

+

0.1µF

-

+

+FS

AVDD/2

-FS

0.1µF

0.1µF

AIN

REFTS

REFBS

REFTF

0.1µF

10µF

REFBF

Figure 9 Full External Mode with Kel vi n connecti ons (Reference Generator Di sabled)

DIFFERENTIAL MODE (MODE = AVDD/2)

The WM2331 operates in differential mode when the voltage at the MODE pin is AVDD/2 (mid­supply). The ADC reference voltages REFTF and REFBF are generated by the internal reference
buffer from V
on-chip reference generator or driven by an external source, as discus sed under ‘On-chip Ref erence
Voltage Generation’, below. REFTF and REFBF are centred around AVDD/2 by the internal
reference buffer and the voltage difference between them equals V

AIN

REFTS

REFBS

VREF

AGND

Figure 10 ADC Reference Generation in Differential Mode

This mode is suitabl e for handling differentially presented inputs , which are applied to the AIN and
REFTS/REFBS pins. A spec ial case of differential mode is centre span mode, in which the user
applies a single-ended signal to A IN and applies the m id-scal e input voltage (V
REFBS pins.

. Depending on the connection of the RE FSENSE pin, V

REF

= AVDD + VREF

+1

-1/2

-1/2

SAMPLE

AND

HOLD

INTERNAL

REFERENCE

BUFFER

REFTF

PGA

CORE

REFBF

ADC

2

= AVDD - VREF

2

REF

may be supplied by the

REF

.

) to the REFTS and

M

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

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Production Data WM2331

+FS

-FS

AIN

MODE

REFTS

AVDD/2

REFSENSE

0.1µF

REFBS

REFTF

VREF

0.1µF

0.1µF10µF
REFBF

Figure 11 Differential Mode, 1V Reference Span

AVDD/2

MODE

DC SOURCE =VM

+

VM

-

0.1µF

+FS

VM

-FS

AIN

REFTS

REFBS

REFTF

0.1µF

0.1µF10µF
REFBF

REFSENSE

Figure 12 Centre Span Mode, 2V Reference Span

TOP/BOTTOM MODE (MODE = AGND)

Top/Bottom mode is enabled by connecting the MODE pin to AVDD. In this mode, the ADC
Reference voltages REFTF and REFBF are generated by the internal reference buffer from the
externally supplied voltages REFTS and REFBS. Only single-ended input is possible in
TOP/BOTTOM Mode.

REFTF =
AVDD + (REFTS - REFBS)

AIN
REFTS
REFBS

Figure 13 ADC Reference Generation in Top/Bottom Mode

The voltage difference between REFTS and REFBS should equal the peak-to-peak input signal
amplitude times the PGA gain (see ‘Analogue Signal Path’, above). A smaller voltage difference
would give rise to out-of-range conditions, whereas a larger one would not fully utilise the ADC
resolution. The average of REFTS and REFB S must be the AIN mi d-scale voltage, V

+1

-1/2

-1/2

SAMPLE

AND

HOLD

INTERNAL

REFERENCE

BUFFER

PGA

ADC

CORE

REFBF =
AVDD - (REFTS - REFBS)

.

M

Typically, REFSENSE is tied to AVDD t o disable the on-chip reference generator, but the user can
also choose to use its out put to drive either REFTS or REFBS.

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WM2331 Production Data

+FS

-FS

DC SOURCE =
VM + [(FS+) - (FS-)]* GAIN/2

DC SOURCE =
VM - [(FS+) - (FS-)]* GAIN/2

0.1µF

0.1µF

AIN

REFTS

REFBS

REFTF

0.1µF10µF

REFBF

MODE

REFSENSE

Figure 14 Top/Bottom Mode (Reference Generator Disabled)

ON-CHIP REFERENCE VOLTAGE GENERATOR

The On-chip Reference Generator (ORG) can provide a referenc e voltage on the VREF pin that is
independent of temperature and suppl y voltage. External connecti ons to the REFSENS E pin control
the ORG’s output to VREF, as shown in Table 2.

REFSENSE CONNECTION ORG OUTPUT TO VREF

VREF pin 1 Volt

AGND 2 Volts

External divider junction (1 + RA/RB) Volts – see Figure 15

AVDD None (VREF becomes input pin)

Table 2 Controlling the On-chip Reference Generator

AVDD

Connecting REFSENSE to AVDD powers t he ORG down, saving power when the ORG function is
not required.

In differential mode (MODE = AVDD/2), the voltage on VREF det ermines the ADC reference voltages
as follows:

VAVDD

REFTF+=

REFBF−=

REF

2

VAVDD

REF

2

VREFBFREFTF =−

REF

When the ORG is enabled, the VREF pin should be decoupled to t he circuit board’s anal ogue ground
plane close to the W M2331 AGND pin via a 1µF tantalum c apacitor and a 0.1µF ceramic capac itor.
The ORG can source currents up to 1m A into external grounded loads when it is not used by the
WM2331. Typical buff er l oad regul ation is about 0.5Ω.

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Production Data WM2331

INTERNAL

REFERENCE

BUFFER

MODE =

AVDD/2

DC CLAMP

VBG

+

–

+

–

V

= 1 + (RA/RB)

REF

R

A

0.1µF

1µF
tantalum

REFSENSE

R

B

AGND

Figure 15 ORG Operating with External Divider (for Intermediate Reference Voltages)

10-bit

DAC

CONTROL

REGISTER

S/H

Vin

CLAMPIN

CLAMP

C

IN

R

+

Vclamp

-

AIN

IN

SW1

Figure 16 Schematic of Clamp Circuitry

The WM2331 provides a clam p function for restoring the DC reference level of AC coupled input
signals. Figure 17 shows an example of usi ng the clamp to restore the black level of a composite
video input AC coupled to AIN. While the clamp pin is held high, the clamp amplifier forces the
voltage at AIN to equal the clamp reference voltage, sett ing the DC vol tage at AI N for t he video blac k
level.

Line sync

Black

level

VIDEO AT AIN

CLAMP

Figure 17 Example Waveforms for Line-Clam p i ng to a V ideo Input Black Level

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WM2331 Production Data

After power up, the clamp referenc e volt age is the volt age suppl ied on t he CLA MPIN pin. However, it
can also be generated by the on-chip 10-bit clamp level DAC by s uitably program ming the W M2331
clamp and control regis t ers (see Digital Control Regist ers, below).

Clamp design for mini mum acquisiti on time and droop is discus sed in Applications Inf ormation.

CLAMP DAC OUTPUT VOLTAGE RANGE AND LIMITS

Important: W hen using the internal clamp DA C in Top/Bottom or Cent re Span Mode, the user must
ensure that the desired DC clamp level at AIN lies within the voltage range REFBF to REFTF. This is
because the clamp DAC voltage is c onstrained to lie within this range REFBF to REFTF. Specific ally:

V

DAC

DAC codes can range from 0 t o 1023. Figure 18 shows the clamp DAC output voltage versus the
DAC code.

VREFTF

VREFBF

Figure 18 Clamp DAC Output Voltage versus DAC Register Code Value

If the desired DC level at AIN does not lie within the range REFTF to REFBF, then either:

• the CLAMPIN pin can be used inst ead to provide a suitable reference voltage or

• it may be possible t o re-design the application to m ove the AIN input range into the

POWER MANAGEMENT

In power-sensitive applications (such as battery-powered systems) where the WM2331 ADC i s not
required to convert continuousl y, power can be saved between conversion intervals by placing the
WM2331 into Power Down mode. This i s achieved by set ting bit 3 (PDW N) of the cont rol register to

1. In Power Down mode, the device typically cons umes less than 3mW of power. Power down mode
is exited by resetting control regis ter bit 3 to 0. On power up from long periods of power down, the
WM2331 typically requires 5ms of wake up time before val i d conversion results are available.

= REFBF + (REFTF

VDAC

VREFBF + 0.006(VREFTF-VREFBF)

0

í5()%)

VREFBF + 0.987(VREFTF-VREFBF)

× (0.006 + 0.988×(DAC code)/1024)

1023

DAC

code

CLAMP DAC voltage range. This is achieved in both Top/Bottom and Centre Span
Modes by shifting both REFTS and REFB S up or down by the voltage through which
the AIN input range is to be moved.

In systems where the ADC must run conti nuously, but where the clamp is not required, t he supply
current can be reduced by approximately 1.2m A by setting the control regis ter bit 6 (CLDI S), which
disables the clam p circuit. Similarl y, when REFSENSE is tied to AVDD, t he reference generator is
disabled and supply current reduced by approxim ately 1.2mA.

OUTPUT FORMAT AND DIGITAL I/O

While the OEB pin is held low, ADC convers ion results are output at the data I/ O pins DI O0 (LSB) to
DIO9 (MSB). The default output data format is unsigned bi nary (output codes 0 to 1023). This c an be
switched to two’s complement format (output codes -512 to 511) by setting control register bit 5
(TWOC) to 1.

WRITING TO THE INTERNAL REGISTERS THROUGH THE DIGITAL I/O BUS

Pulling the OEB pin high disables the data and out-of-range indicator (OVR) pins’ output drivers,
setting the driver outputs t o a high impedance state. This al lows control register data to be loaded
into the WM2331 by presenti ng it on the DI O0 to DIO9 pins and pulsing t he W R pin high to l atch the
data into the chosen control or DAC register.

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Production Data WM2331

Figure 19 shows an example register write cycle where the clamp DAC code is set to 199 (hex) by
writing to clamp registers 1 and 2 (see ‘Digital Control Registers ’, below). Pins DIO0 to DIO7 are
driven to the clamp DAC code l ower byte (0F hex) and pins DIO8 and DIO9 are both driven to 0 to
select clamp regis ter 1 as the data destination. The clamp low-byte data is then loaded into this
register by pulsing W R high. The top 2 bits of t he DAC word are then loaded by driving 01(hex) on
pins DIO0 to DIO7 and by driving pin DIO8 to 1 and pi n DIO9 to 0 to select clamp regi ster 2 as the
data destination. WR is pulsed a second ti me to latch this s econd control word into clamp regis ter 2.

NOE

WR

DIO[9:0]

Figure 19 Example Register Write Cycle to Clamp DAC Register

OUTPUT

DIGITAL CONTROL REGISTERS

The WM2331 contains t wo clamp regist ers and a control register f or user program ming. Binary dat a
can be written into these registers using pins DIO0 to DIO9 and the WR and OEB pins (see the
previous section). In input mode, DIO9 and DIO8 are address bits and the remaining DIO pins are
data bits.

ADDRESS

DIO[9:8]

00
01
10
11

Table 3 Register Map

DESCRIPTION DEFAULT

(HEX)

Clamp Reg. 1
Clamp Reg. 2
Control Reg.
Reserved

00 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
00 RW DAC[9] DAC[8]
01 RW CLDIS TWOC CLINT PDWN PGA[2] PGA[1] PGA[0]

READ/

WRITE

OUTPUTINPUT 099 INPUT 101

Load 99 hex into

register 0

DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0

Load 01 hex into

register 1

DATA BITS DIO[7:0]

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WM2331 Production Data

REGISTER BIT NO BIT NAME(S) DEF AULT DESCRIPTION

Clamp Register 1
DIO[9:8] = 00

Clamp Register 2
DIO[9:8] = 01

Control Register
DIO[9:8] = 10

Table 4 Register Contents

7:0 DAC[7:0] 0

7:2
1:0 DAC[9:8] 01

2:0 PGA[2:0] 001

3PDWN 0

4CLINT 0

5TWOC 0

6CLDIS 0

7

Clamp DAC voltage
(DAC[0] = LSB.)
DAC[9:0] = 00h: Clamp volt age = REFBF
DAC[9:0] = 3Fh: Clamp volt age = RE FTF
Unused
Clamp DAC voltage
(DAC[9] = MSB)
PGA gain:
000 = 0.5
001 = 1.0
010 = 1.5
011 = 2.0
100 = 2.5
101 = 3.0
110 = 3.5
111 = 4.0

Power down
0 = WM2331 powered up
1 = WM2331 powered down
Clamp voltage internal/ex t ernal
0 = external analogue clamp volt age f rom CLAMPIN pin.
1 = from on-chip DAC (see Clamp Register)
Output format
0 = unsigned binary
1 = two’s complement
Clamp Amplifi e r Di sable (for power saving)
0 = Enable
1 = Disable
Unused

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Production Data WM2331

APPLICATIONS INFORMATION

DRIVING THE CLOCK INPUT

Obtaining good performance from the WM2331 requires care when driving the clock input.
Different sections of the Sam ple-and-Hold and ADC operate while the clock is low or high. The user

should ensure that the clock duty cycle rem ains near 50% to ens ure that all int ernal circuit s have as
much time as possible in which to operate.

The CLK pin should also be driven from a low jitter source for best dynamic performance. To
maintain low jitter at t he CLK input , any c loc k buf fers external t o t he WM2331 should have f ast ri sing
edges. Use a fast logic family such as A C or ACT to drive the CLK pin, and consi der powering any
clock buffers s eparately f rom any other l ogic on the PCB to prevent digit al s upply nois e appearing on
the buffered clock edges as jitter.

As the CLK input threshold is nominally around AVDD/2, any clock buffers need to have an
appropriate supply voltage to drive above and below this l evel .

DRIVING THE SAMPLE AND HOLD INPUTS

DRIVING THE AIN PIN

Figure 20 shows an equivalent circuit f or the W M2331 AIN pin. The load present ed to t he system at
the AIN pin comprises the switched input sampling capacitor, C
capacitances, C

and CP2.

P1

, and various stray

Sample

AVDD

1.2pF

C

Sample

AIN

AGND

8pF

CLK

C

P1

CP2 = 1.2pF

CLK

+

V

-

LAST

Figure 20 Equivalent Circuit for Analogue Input Pin AIN

The input current pulses required to c harge C

can be time averaged and the switched capac itor

Sample

circuit modelled as an equivalent resistor

IN

where CS is the sum of C

fCR×

CLKS

and CP2 (see Figure 21). This model can be used to estim ate the

Sample

1

=

2

input loading versus source res i stance for high impedance sources.

AVDD

R

= 1 / CS f

AIN

CP1 = 8pF

IN2

I

IN

CLK

+

VM = (REFTS + REFBS) /2

-

AGND

Figure 21 Equivalent Circuit for the AIN Switched Capacitor Input

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WM2331 Production Data

AIN INPUT DAMPING

The charging current pulses into AIN can make the signal source jump or ring, especially if the
source is slightly induc tive at high f requencies. Ins erting a sm all series res istor of 20Ω or less in the
input path can damp source ringing (see Figure 22). The resistor can be made l arger than 20Ω if
reduced input bandwidth or distortion performance is acceptable.

AIN

< 20R

V

S

Figure 22 Damping Source Ringing Using a Small Resistor

DRIVING THE SAMPLE & HOLD REFERENCE INPUTS

The sample and hold reference inputs (connected to pins REFTS and REFBS) present s witched­capacitor loads sim ilar to t he AIN pin, but with sm aller capac itors (see Figure 23 below). Note that in
Top/Bottom mode, the internal referenc e buffer is als o driven from REFTS and REFBS and the tot al
load on these pins is therefore the parallel combination of the sample and hold circuit and the
reference buffer.

AVDD

REFTS

or

REFBS

AGND

Internal

Reference

Buffer

C

P1

Mode = AVDD

CLK

CP2 = 0.6pF7pF

CLK

+

V

LAST

-

0.6pF

C

Sample

Figure 23 Equivalent Circuit of REFTS and REFBS Sample & Hold Inputs

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Production Data WM2331

DRIVING THE INTERNAL REFERENCE BUFFER

DRIVING THE VREF PIN (DIFFERENTIAL MODE)

Figure 24 shows the equivalent load on the VREF pi n when driving the internal reference buf fer via
this pin (MODE = AVDD/2 and REFSE NS E = AVDD).

AVDD

R

14K

IN

REFSENSE=AVDD,
Mode = AVDD/2

VREF

AGND

+

(AVDD+VREF) / 4

-

Figure 24 Equivalent Circuit of VREF

The input current I

I

REF

REF

3

=

is given by

AVDDV

−

REF

R

×

4

IN

Tolerance on this current is ±30 % or greater. The user should ensure that VREF is driven from a

low noise, low drift source, well-decoupled t o anal ogue ground and capable of driving I

REF

.

DRIVING THE INTERNAL REFERENCE BUFFER (TOP/BOTTOM MODE)

Figure 25 shows the loading on the REFTS and REFBS pins in Top/Bottom mode due to the int ernal
reference buffer. Note that t he sample and hold circuit must als o be driven via these pins, which
adds additional load (see Driving the S ample & Hold Reference Inputs , above).

AVDD

REFTS

or

REFBS

AGND

AVDD + (REFTS + REFBS) / 4

R

14K

IN

Mode = AVDD

+

-

Figure 25 Equivalent Circuit of Inputs to Internal Reference Buffer

The input currents are given by:

REFBSAVDDREFTS

−−

R

×

IN

REFTSAVDDREFBS

−−

R

×

4

IN

and

3

I

=

INTS

3

I

=

INBS

4

These currents must be provided by the sources on REFTS and REFBS in addition to the
requirements of driving the s ample and hold.

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

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WM2331 Production Data

DRIVING REFTF AND REFBF (FULL EXTERNAL REFERENCE MODE)

AVDD

REFTF

REFBF

Figure 26 Equivalent Circuit of REFTF and REFBF Inputs

DESIGNING THE DC CLAMP

Figure 16 (in Device Description) s hows the basi c operat ion of t he cl am p c irc uit with the analog input
AIN coupled via an RC circuit . The clamp voltage output level may be established by an analog
voltage on the CLAMPIN pin or by programming the on-chip clamp DAC.

INITIAL CLAMP ACQUISITION TIME

Initial acquisition tim e is defined as the tim e required to reach the target c lamp voltage at A IN when
the clamp switch SW 1 is closed for the first time (clamp re-acquisi tion during normal operation is
discussed in Steady-state Clamp Voltage Error, below). This time is given by

AGND

AVDD

AGND

ININACQ

680R

××=



V



RCT ln




To REFBS
(for Kelvin
connection)

To REFTS
(for Kelvin
connection)



C





V

E



where Vc is the difference between the DC level of t he input VIN and the target clamp output voltage,

. VE is the difference between the ideal V c and the actual Vc obtained during the acqui sition

V

Clamp

time. The maximum tolerable error depends on the applicati on requi rements.
For example, consider clam ping an incom ing video si gnal that has a black l evel near 0.3V t o a bl ack

level of 1.3V at the WM2331 input. The voltage V
thus 1.3 - 0.3 = 1V. If a 10m V or less clam p voltage error V
the source resistanc e Rin is 20Ω

DQGWKHFRXSOLQJFDSDFLWRU&LQLV )WKHQWKHWRWDOFODPSSXOVH

required across the input coupli ng capacitor is

C

will give acceptable system operation,

E

duration required to reach this error is :

T

= 1µF × 20Ω × ln(1/0.01) = 92µs (approx.)

ACQ

Note that during continuous operati on, the clamping time would typically be much shorter, as the
voltage difference wolud be small er (dependi ng on droop, see next section.

Initial acquisit i on can be performed in two ways:

• Pulsing the CLAMP pin as in normal operation. Provided that cl amp droop (see below)
is negligible, initial acquisition is complete when the total c lamped (CLAMP = HIGH)
time equals T

ACQ

.

• Pulling the CLAMP pin high for the required acquisition time before starting normal
operation. This method is faster.

CLAMP DROOP

The charging currents drawn by the Sample-and-Hold switched capacitor input can charge or
discharge C
during the time between clamp pul ses. This effect i s called clamp droop.

Voltage droop is a function of the AIN i nput current t o the W M2331, I
intervals, t

, causing the DC voltage at A IN to drift towards VM (the average of REFTS and REFBS)

IN

, and the time between clam p

:

D

IN

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

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Production Data WM2331





I

IN



V ×

DROOP



≈



C



t

(approx.)

D



IN



Worst case droop between clamping intervals occurs for maximum input bias current. Maximum
input current is I

For example, at 30 MSPS I
Sample and Hold Reference Input s, above, to calculat e I
30% because of processing variations and voltage dependencies. Designs should allow for this
variation. If the time t
level droop between clamp pulses is

V
= 1.25LSB at PGA gain=1, 2V A DC references

If this droop is greater than can be tolerated in the application, then increase C
and hence reduce the voltage change between clamp pulses.

If a high leakage capacitor i s used for coupling the input source to the A IN pin then the droop may be
significantly worse than cal culated above. Avoid using electrol ytic and tantalum c oupling capacitors
as these have higher leakage currents than non-polarised capacitor t ypes. Elect rolytic and tantalum
capacitors also tend to have higher parasit ic inductance, which can cause problems at hi gh input
frequencies.

, which occurs when the input level is at its maximum or minimum.

INFS

is approximately 40µA for a 2V input range at A IN (see ‘Driving the

DROOP

INFS

EHWZHHQFODPSLQJLQWHUYDOVLV VDQG&INLV )WKHQWKHPD[LPXPFODPS

D

= 40µ

$ )× V P9DSSUR[

). Note that I

IN

may vary from this by ±

INFS

to slow the droop

IN

STEADY-STATE CLAMP VOLTAGE ERROR

During the clamp pulse (CLAMP = HIGH), the DC voltage on AIN is refreshed from the clamp
voltage. Provided that droop is not excessive, clampi ng fully reverses the effect of droop. However,
using very short clamp pulses with l ong intervals between pulses (t
voltage difference, V

Figure 27 shows the approximate voltage waveform at A IN resulting from a a large clamp droop
during t

and clamp voltage re-acquis i t i on duri ng the clamp pulse time, tC.

D

, between the DC voltage at AIN and Vcl amp.

COS

) can result in a steady-st ate

D

Vclamp

V

AIN

VM

Figure 27 Approximate Waveforms at AIN During Droop and Clamping

The voltage change at AIN during acquisition has been approxim ated as a linear charging ramp by
assuming that alm ost all of V
reasonable approximation when V
during clamp acquisit i on i s then

V

=∆

AIN

The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state.
Equating the droop voltage to the cl amp acquisition voltage change gives

V××=

COS

tc td

appears across RIN, giving a charging current V

COS

COS

tV

×

DCOS

CR

×

ININ

tIR

t

C

V

COS

V

DROOP

∆

= V

AIN

(this is a

is large enough to be of concern). The volt age change at AIN

DININ

COS/RIN

Thus for low offset voltage, k eep RIN low, design for low droop and ensure that the ratio tD/tC is not
unreasonably large.

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

23

WM2331 Production Data

REFERENCE DECOUPLING

VREF PIN

When the on-chip referenc e generator is enabled, the VREF pin s hould be decoupled to the circuit
board’s analogue ground plane close to the W M2331 AGND pin via a 1µF tantalum capac itor and a

0.1µF ceramic capacitor.

REFTF AND REFBF PINS

In any mode of operation, the REFTF and REFBF pins should be decoupled as shown in Figure 28
below. Use short board traces between the WM2331 and the capacitors to minimise parasitic
inductance.

0.1µF

0.1µF

Figure 28 Recommended Decoupling for the ADC Reference Pins REFTF and REFBF

REFTF

0.1µF10µF

REFBF

WM2331

SUPPLY DECOUPLING

The analogue (AVDD, AGND) and digital (DVDD, DGND) power supplie s to the W M2331 should be
separately decoupled for best performance. Each supply needs at least a 10µF electrolytic or
tantalum capacitor (as a c harge reservoir) and a 100nF ceramic type capaci tor placed as close as
possible to the respect i ve pins (to suppress spik es and supply noise).

DIGITAL OUTPUT LOADING AND CIRCUIT BOARD LAYOUT

The WM2331 outputs are capabl e of dri vi ng rai l -t o-rai l with up to 20pF of load per pin at 30MHz clock
and 3V digital supply. Minimising the load on the outputs will improve WM2331 signal-to-noise
performance by reducing the switching noise coupling from the WM2331 output buffers to the internal
analogue circuits. The output load capacitanc e can be minimised by buffering the W M2331 digital
outputs with a low input capacitanc e buffer plac ed as c lose to the output pins as phys icall y poss ible,
and by using the shortest possible tracks between the WM2331 and this buffer.

Noise levels at the output buf fers, which may affect the analogue circuits within W M2331, increase
with the digital supply voltage. W here pos sible, c onsider usi ng the lowest DVDD that the appl ication
can tolerate.

Use good layout practices when designing the application PCB to ensure that any off-chip return
currents from the WM2331 digit al out puts (and any other digi tal c irc uit s on t he PCB) do not return vi a
the supplies to any sensitive analogue circuits. The WM2331 s hould be soldered direct ly to the PCB
for best performance. Socketing the device will degrade performance by adding parasitic socket
inductance and capacitanc e to all pins.

USER TIPS FOR OBTAINING BEST PERFORMANCE FROM THE WM2331

• Choose differential input mode for best distortion performance.

• Choose a 2V ADC input span for best noi se performance.

• Choose a 1V ADC input span for best di stortion performance.

• Drive the clock input CLK f rom a low-jitter, fast logi c stage, with a well-decoupled

power supply and short PCB traces.

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

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Production Data WM2331

PACKAGE DIMENSIONS

DT: 28 PIN TSSOP (9.7 x 4.4 x 1.0 mm)

b

D

A A2

A1

DM022.A

e

1528

E1 E

141

0.1

-C-

C

SEATING PLANE

GAUGE
PLANE

θ

0.25

c

L

Dimensions

Symbols

(mm)

MIN NOM MAX
A
A

1

A

2

b
c
D
e
E
E

1

L

θ

REF:

NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIM ETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, N O T TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MO-153, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

----- ----- 1.20

0.05 ----- 0.15

0.80 1.00 1.05

0.19 ----- 0.30

0.09 ----- 0.20

9.60 9.70 9.80

0.65 BSC

6.4 BSC

4.30 4.40 4.50

0.45 0.60 0.75

o

0

----- 8

o

JEDEC.9 5 , M O -1 5 3

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

25