Datasheet W24100S-70LL, W24100S-70L, W24100Q-70L, W24100Q-70LL, W24100-70LL Datasheet (Winbond Electronics)

Preliminary W24100

1

2

3

5

6

789

10

121314

16

OE

CS1

I/O7

I/O6

I/O5

I/O4

28

V

CS2

DD

A9

I/O3

I/O1

CS1

WE

OE

128K × 8 CMOS STATIC RAM

GENERAL DESCRIPTION

The W24100 is a normal-speed, very low-power CMOS static RAM organized as 131072 × 8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.

FEATURES

•

Low power consumption:

− Active: 385 mW (max.)

•

Access time: 70 nS

•

Single 5V power supply

•

Fully static operation

•

All inputs and outputs directly TTL compatible

•

Three-state outputs

•

Battery back-up operation capability

•

Data retention voltage: 2V (min.)

•

Packaged in 32-pin 600 mil DIP, 450 mil SOP,
standard type one TSOP (8 mm × 20 mm) and
small type one TSOP (8 mm × 13.4 mm)

PIN CONFIGURATIONS

32-pin

SOP

32-pin
TSOP

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

NC

A16

2

A14

3

4

A12

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12

I/O1

13

I/O2

14

I/O3

15

V

SS

16

A11
A8

A13

4

WE
A15

NC

A16

11

A14
A12

A7
A6

15

A5
A4

BLOCK DIAGRAM

CLK GEN.

A16

V

DD

A15

CS2

WE

A13

A8

A9

A11

OE

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

PIN DESCRIPTION

A14
A12

I/O1
I/O8

WE
CS1

CS2

A4
A3

A2
A7
A6
A5
A9

:

OE

SYMBOL DESCRIPTION

32

A10

31
30

I/O8

29
27

26
25

VSS

24
23

I/O2

22
21

A0

20

A1

19

A2

18

A3

17

A0−A16

I/O1−I/O8

, CS2

VDD Power Supply
VSS Ground

Address Inputs
Data Inputs/Outputs
Chip Select Input

Write Enable Input
Output Enable Input

NC No Connection

W
D
C

O
D

DATA
CNTRL.

CLK
GEN.

R
O

E

E
R

A15

PRECHARGE CKT.

CORE CELL ARRAY

1024 ROWS

128 X 8 COLUMNS

I/O CKT.

COLUMN DECODER

A0 A11

A13A8A1

A10

Publication Release Date: October 1999

- 1 - Revision A1

TRUTH TABLE

CS1

OE WE

CS1

CS1

CS

CS1

Preliminary W24100

CS2

MODE

I/O1−I/O8

VDD CURRENT

H X X X Not Selected High Z ISB, ISB1
X L X X Not Selected High Z ISB, ISB1

L H H H Output Disable High Z IDD
L H L H Read Data Out IDD
L H X L Write Data In IDD

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Supply Voltage to VSS Potential -0.5 to +7.0 V
Input/Output to V

SS

Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150
Operating Temperature 0 to 70

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.

°

C

°

C

Operating Characteristics

(VDD = 5V ±10%; VSS = 0V; TA = 0° C to 70° C)

PARAMETER

Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage

Current

Output Low Voltage
Output High Voltage
Operating Power

Supply Current

Standby Power Supply
Current

Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 5V.

SYM. TEST CONDITIONS MIN. TYP.* MAX. UNIT

VIL - -0.5 - +0.8 V
VIH - +2.2 - V

ILI VIN = V

ILO

V
(min.) or OE = V
or WE = V

VOL I

VOH I

IDD

SS

to VDD -1 - +1

I/O

= VSS to V

OL

= +2.1 mA - - 0.4 V

OH

= -1.0 mA 2.4 - - V

DD,

IL

(max.)

IH

(min.)

= V

IH

= VIL (max.) and

-1 - +1

- - 70 mA

DD

+0.5 V

µ

A

µ

A

CS2 = VIH (min.), I/O = 0 mA
Cycle = min., Duty = 100%

ISB

= VIH (min.), Cycle = min.

- - 3 mA

Duty = 100%

ISB1

≥ VDD -0.2V or

CS2 ≤ 0.2V

LL -

L -

-

50

-

100

µ

A

- 2 -

Preliminary W24100

CAPACITANCE

(VDD = 5 V, TA = 25° C, f = 1 MHz)

PARAMETER SYM. CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance C

Note: These parameters are sampled but not 100% tested.

I/O

V

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load See the drawing below

OUT

= 0V 8 pF

AC Test Loads and Waveform

OUTPUT

1 TTL

100 pF
Including
Jig and
Scope

3.0V

0V

5 nS

1 TTL

OUTPUT

5 pF
Including
Jig and
Scope

(For T T T T T T )

CLZ, OLZ, CHZ, OHZ, WHZ, OW

90%

10%

90%

10%

5 nS

Publication Release Date: October 1999

- 3 - Revision A1

Preliminary W24100

CS1

AC Characteristics, continued
(VDD = 5V ±10%; VSS = 0V; TA = 0° C to 70° C)

Read Cycle

PARAMETER SYM. W24100-70L W24100-70LL UNIT

MIN. MAX. MIN. MAX.

Read Cycle Time TRC 70 - 70 - nS
Address Access Time TAA - 70 - 70 nS
Chip Select Access Time T
Output Enable to Output Valid T
Chip Selection to Output in Low Z T
Output Enable to Output in Low Z T
Chip Deselection to Output in High Z T
Output Disable to Output in High Z T
Output Hold from Address Change TOH 10 - 10 - nS

These parameters are sampled but not 100% tested

∗

ACS

- 70 - 70 nS

AOE

- 35 - 35 nS

CLZ

* 10 - 10 - nS

OLZ

* 5 - 5 - nS

CHZ

* - 30 - 30 nS

OHZ

* - 30 - 30 nS

Write Cycle

PARAMETER SYM. W24100-70L W24100-70LL UNIT

MIN. MAX. MIN. MAX.

Write Cycle Time TWC 70 - 70 - nS
Chip Selection to End of Write TCW 50 - 50 - nS
Address Valid to End of Write TAW 50 - 50 - nS
Address Setup Time TAS 0 - 0 - nS
Write Pulse Width TWP 50 - 50 - nS
Write Recovery Time

, CS2, WE

TWR 0 - 0 - nS

Data Valid to End of Write TDW 30 - 30 - nS
Data Hold from End of Write TDH 0 - 0 - nS
Write to Output in High Z T
Output Disable to Output in High Z T

WHZ

* - 25 - 25 nS

OHZ

* - 25 - 25 nS

Output Active from End of Write TOW 5 - 5 - nS

These parameters are sampled but not 100% tested

∗

- 4 -

TIMING WAVEFORMS

Read Cycle 1

(Address Controlled)

Address

DOUT

Read Cycle 2

(Chip Select Controlled)

CS1

Preliminary W24100

T

RC

T AA

T

OH

T

OH

CS2

D

OUT

Read Cycle 3

(Output Enable Controlled)

Address

OE

CS1

CS2

D

OUT

T

ACS

T

CLZ

T

CHZ

T

RC

T

AA

T

AOE

T

OLZ

T

ACS

T

CLZ

T

OH

T

OHZ

T

CHZ

Publication Release Date: October 1999

- 5 - Revision A1

Timing Waveforms, continued

Write Cycle 1

Address

OE

CS1

CS2

WE

D OUT

D

IN

Preliminary W24100

T

WC

T

WR

T

CW

T

AW

T

T

AS

T

OHZ

(1, 4)

WP

T

T

DW

DH

Write Cycle 2

(OE = VIL Fixed)

T

WC

Address

WP

WHZ

(1, 4)

T

DW

T

WR

T

OH

T

OW

T

DH

(2) (3)

T

CW

CS1

CS2

T

AW

WE

D

OUT

D

IN

T

AS

T

T

Notes:

1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.

2. The data output from DOUT are the same as the data written to DIN during the write cycle.

OUT

3. D

provides the read data for the next address.

4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.

- 6 -

DATA RETENTION CHARACTERISTICS

CS

CS

(TA = 0° C to 70° C)

PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT

Preliminary W24100

VDD for Data Retention VDR
Data Retention Current I
Chip Deselect to Data

DDDR

CDR

T

≥ VDD -0.2V
≥ VDD -0.2V, VDD = 3V

See data retention waveform 0 - - nS

2.0 - - V

- - 50

µ

A

Retention Time
Operation Recovery Time TR TRC* - - nS

Read Cycle Time

*

DATA RETENTION WAVEFORM

VDD

CS1

CS2

0.9 DD

V

T

CDR

CS

0.9 DD

>

DR

2V

V

=

>

DD

V

-0.2V

=

V

R

T

Publication Release Date: October 1999

- 7 - Revision A1

ORDERING INFORMATION

Preliminary W24100

PART NO. ACCESS

TIME (nS)

W24100-70L 70 70 100 600 mil DIP
W24100-70LL 70 70 50 600 mil DIP
W24100S-70L 70 70 100 450 mil SOP
W24100S-70LL 70 70 50 450 mil SOP
W24100T-70L 70 70 100 Standard type one TSOP
W24100T-70LL 70 70 50 Standard type one TSOP
W24100Q-70L 70 70 100 Small type one TSOP
W24100Q-70LL 70 70 50 Small type one TSOP

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.

OPERATING

CURRENT

MAX. (mA)

STANDBY

CURRENT

MAX. (

µ

A)

PACKAGE

- 8 -

PACKAGE DIMENSIONS

2. Dimension E1 does not include interlead flash.

3. Dimensions D & E1 include mold mismatch and

6. General appearance spec. should be based on

1

1

32-pin P-DIP

Preliminary W24100

32

E

1

S

2

A

A

L

D

B
B

32-pin SOP Wide Body

32

1

D

S

Seating Plane

y

Dimension in inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.010

A

1

0.150

0.155

A

2

0.016

0.018

B

0.050 1.27

B

1

0.010

c

17

16

A

1

Base Plane

Seating Plane

1e

17

E H

E

16

b

e

E

e

A

a

e

1

θ

L

Detail F

1

c

c

A

2

A

e

A

1

See Detail F

L

E

0.008

1.650 1.660

D

0.6000.590

E
E1
e

1

0.120

0.130

L

0 15

a

0.6500.630 16.00 16.51

e

A

S

Notes:

1. Dimensions D Max. & S include mold flash or
tie bar burrs.

are determined at the mold parting line.

4. Dimension B1 does not include dambar
protrusion/intrusion.

5. Controlling dimension: Inches
final visual inspection spec.

Dimension in Inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.004

A

1

0.101

A

2

0.014

b

0.0080.006

c

D

H

L

θ

Notes:

1. Dimensions D Max. & S include mold flash
or tie bar burrs.

2. Dimension b does not include dambar
protrusion/intrusion.

3. Dimensions D & E include mold mismatch
and determined at the mold parting line.

4. Controlling dimension: Inches

5. General appearance spec should be based
on final visual inspection spec.

0.805

E
e

E

0.023

L

0.047

E

S
y

0

Dimension in mm

0.210

0.25

0.160

3.81

0.41

0.022

0.20

0.014

0.610

14.99

13.84

0.5550.5500.545

0.110

2.29 2.54 2.790.090 0.100

3.05

0.140

0.670

0.085

0.118

0.106

0.111

0.016

0.020

0.012 0.31

0.817

11.18

0.4500.4450.440

0.056

0.5560.5560.546 14.3814.1213.87

0.039

0.031

0.063 1.19

0.055

0.036

0.004
10

.

3.94

0.46

0.25

41.91 42.16

15.24

13.97

3.30

Dimension in mm

0.10

2.57

2.69

0.36

0.41

0.200.15

20.45

11.30

1.12 1.27 1.420.044 0.050

0.79 0.99

0.58

1.40

0

5.33

4.06

0.56

1.371.220.0540.048

0.36

15.49

14.10

3.56

17.02

2.16

150

3.00

2.82

0.51

20.75

11.43

1.60

0.91

0.10
10

- 9 - Revision A1

Publication Release Date: October 1999

Package Dimensions, continued

32-pin Standard Type One TSOP

H

D

D

1

M

e

0.10(0.004)

b

θ

L

L

1

Preliminary W24100

Dimension in Inches

Symbol

Min. Nom. Max.

__

__

c

E

A

A

2

A

1

Y

A

A

1

A

2

b

c
D
E

H

D

e

L
L

1

Y

θ

Controlling dimension: Millimeters

__

0.002

0.037

0.039

0.007 0.008

0.005 0.006

0.720 0.724

0.311 0.315

0.780 0.787

__

0.020

0.016 0.020

__

0.031

0.000 0.004
1

0.047

0.006

0.041

0.009

0.007

0.728

0.319

0.795

3 5

__

0.024

__ __

Dimension in mm
Min.

Nom.

__

__

__

0.05

0.95

0.17

0.20 0.23

0.12

0.15 0.17

18.30

18.40 18.50

7.90

8.00 8.10

19.80

20.00 20.20

__

0.50

0.40

0.50 0.60

0.80

____

0.00
1

3 5

Max.

1.20

0.15

1.051.00

__

__

0.10

32-pin Small Type One TSOP

H

D

D

1

e

b

θ

L

L

1

Dimension in Inches

Symbol

Min.

Nom. Max.

c

E

2

A

A

1

A

Y

A

0.002

A

1

2

0.037

A

0.007

b

0.0056 0.0059 0.0062

c

0.461

D
E

0.520

D

H

e
L

0.012

1

L

0.027

Y

0.000 0.004

θ

0.039

0.008 0.009

0.465

0.315

0.528

0.020

0.020

Controlling dimension: Millimeters

0.049

0.006

0.041

0.469

0.319

0.536

0.028

Dimension in mm

Nom.

Min.

0.05 0.15

0.95

0.17

0.20 0.27

0.14

0.15 0.16

11.70

11.80 11.90

7.90 8.00 8.100.311

13.20

13.40 13.60

0.50

0.50 0.70

0.30

0.675

0.00
0 3 50 3 5

Max.

1.25

1.051.00

0.10

- 10 -

Preliminary W24100

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Oct. 1999 - Initial Issued

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]

FAX: [phone]

Publication Release Date: October 1999

- 11 - Revision A1