Page 1
PRELIMINARY
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
W216
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 27, 1999, rev. **
Features
• Maximized EMI Suppression usi ng Cypress’s Spread
Spectrum Technology
• Single chip system FTG for Intel
®
440BX AGPset and
VIA Apollo Pro-133
• Three copies of CPU output
• Seven copies of PCI output
• One 48-MHz output for USB / One 24-MHz for SIO
• T wo buffered reference outputs
• Two IOAPIC outputs
• Seventeen SDRAM outputs pr ovide support for 4
DIMMs
• Supports frequencies up to 150 MHz
•I
2
C™ interface for programming
• Power man agem ent control inputs
Key Specific ati o n s
CPU Cycle-to-Cycle Jitter:................. ............ ........... ..250 ps
CPU to CPU Output Skew:.... .. ................................ ... 175 ps
PCI to PCI Output Skew:................. .. ............. .. .. ........ 500 ps
SDRAMIN to SDRAM0:1 5 De lay: ..... .......... .......... .3.7 ns typ.
V
DDQ3
: .................................................................... 3.3V±5%
V
DDQ2
: .................................................................... 2.5V±5%
SDRAM0:15 (leads) to SDRAM_F Ske w :..............0.4 ns typ.
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
T able 1. Mode Input Table
Mode Pin 3
0PCI_STOP#
1REF0
T able 2. Pin Selectable Frequency
Input Address
CPU_F, 1:2
(MHz)
PCI_F, 0:5
(MHz)FS3 FS2 FS1 FS0
1111 133.3 33.3 (CPU/4)
1110 124 31 (CPU/4)
1101 150 37.5 (CPU/4)
1100 140 35 (CPU/4)
1011 105 35 (CPU/3)
1010 110 36.7 (CPU/3)
1001 115 38.3 (CPU/3)
1000 120 40 (CPU/3)
0111 100 33.3 (CPU/3)
0110 Reserved
0101 112 37.3 (CPU/3)
0100 103 34.3 (CPU/3)
0011 66.8 33.4 (CPU/2)
0010 83.3 41.7 (CPU/2)
0001 75 37.5 (CPU/2)
0000 Reserved
Block Diagram
Pin Configuration
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
[1]
VDDQ3
REF0/(PCI_STOP#)
VDDQ2
IOAPIC_F
CPU_F
CPU1
CPU2
PCI_F/MODE
XTAL
PLL Ref Freq
PLL 1
X2
X1
REF1/FS2
VDDQ3
Stop
Clock
Control
Stop
Clock
Control
PCI1
PCI2
PCI3
PCI5
48MHz/FS1
24MHz/FS0
PLL2
÷2,3,4
OSC
VDDQ2
CLK_STOP#
VDDQ3
IOAPIC0
PCI4
I2C
SDATA
Logic
SCLK
I/O Pin
Control
SDRAM0:15
SDRAMIN
16
VDDQ3
PCI0/FS3
Stop
Clock
Control
Stop
Clock
Control
SDRAM_F
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM15
W216
VDDQ2
IOAPIC0
IOAPIC_F
GND
CPU_F
CPU1
VDDQ2
CPU2
GND
CLK_STOP#
SDRAM_F
VDDQ3
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
SDRAM12
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
31
30
29
SDRAM14
GND
SDATA
SCLK
SDRAM13
VDDQ3
24MHz/FS0
48MHz/FS1
Page 2
W216
PRELIMINARY
2
Pin Definitions
Pin Name Pin No.
Pin
Type Pin Description
CPU1:2 51, 49 O
CPU Outputs 1 and 2:
Frequency is set by the FS0:3 inputs or through serial input
interf ace, see Tables 2 and 6. These outputs are affected by the CLK_STOP# input.
CPU_F 52 O
Free-Running CPU Output :
Frequen cy is set b y the FS0:3 inp uts or through serial input
interf ace, see Tables 2 and 6. This output is not affected by the CLK_STOP# input.
PCI1:5 11, 12, 13, 14, 16O
PCI Outputs 1 through 5:
Frequency is set by the FS 0:3 inputs or through serial input
interf ace, see Tables 2 and 6. These outputs are affected by the PCI_STOP# input.
PCI0/FS3 9 I/O
PCI Output/Frequenc y Select Input:
As an output, f requency is se t by the FS0:3 i nputs
or through serial input interface, see Tables 2 and 6. This output is affected by the
PCI_STO P# inpu t. When an inp ut, lat che s data select ing the frequ ency of t he CPU and
PCI outputs.
PCI_F/MODE 8 I/O
Free Running PCI Output:
Frequency i s set by the FS0: 3 inputs or thro ugh serial inp ut
interfac e, s ee Tables 2 and 6. This out put is not affec ted by the PCI_ST OP# in put. When
an input, selects function of pin 3 as described in Table 1.
CLK_STOP# 47 I
CLK_STOP# Input:
When brought LOW, affected outputs are stopped LOW after completing a fu ll clock cy cle (2–3 CPU cloc k latency). When brought HIGH, affect ed outputs
start beginning with a full clock cycle (2–3 CPU cloc k latency).
IOAPIC_F 54 O
Free-running IOAPIC Output:
This output is a buffered ver sion of the reference input
which is not af fec ted by t he CPU_ST O P# logi c input . It’s swi ng is set b y v ol tage appl ied
to VDDQ2.
IOAPIC0 55 I/O
IOAPIC Out put:
Provides 14 .318-MHz f ix ed f requen cy. T he out put v olt age s w ing i s set
by voltage applied to VDDQ2. This output is disabled when CLK_STOP# is set LOW.
48MHz/FS1 29 I/O
48-MHz O u tput:
48 MHz is provided in normal operation. In standard systems, this
output can be used as the ref erence for the Universal Serial Bus. Upon power up, FS1
input will be latched, setting output fr equencies as described in Table 2.
24MHz/FS0 30 I/O
24-MHz O u tput:
24 MHz is provided in normal operation. In standard systems, this
output can be used as the clock input for a Super I/ O chip. Upon power up, FS0 input
will be latched, setting output frequencies as described in Table 2.
REF1/FS2 2 I/O
Refere n ce Outpu t:
14.318 MHz is provided in normal operation. Upon power-up, FS2
input will be latched, setting output fr equencies as described in Table 2.
REF0
(PCI_STOP#)
3 I/O
Fixed 14.318- MHz Output 0 or PCI_STOP# Pin:
Function determined by MO DE pin.
The PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to
remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of
PCI_F . I ts effects take pl ace on the next PCI_F clock cycl e. As an output, this pin provi des
a fixe d clock s ignal equal in fre quency to th e refe rence signa l provi ded at the X1 /X2 pins
(14.318 MHz).
SDRAMIN 17 I
Buffered Input Pin:
The signal provided to this input pin is buffered to 17 outputs
(SDRAM0:15, SDRAM_F).
SDRAM0:15 44, 43, 41, 40,
39, 38, 36, 35,
22, 21, 19, 18,
33, 32, 25, 24
O
Buffered Outputs:
These sixteen dedicated outputs provide copies of the signal provided at the SDRAM IN input. The s wing is set b y VDDQ3, and they are deactiv ated when
CLK_STOP# input is set LOW.
SDRAM_F 46 O
Free-Running Buffered Output:
This output provides a single copy of the SDRAMIN
input. The s wing is set by VDDQ3; this signal is unaffected by the CLK _STOP# input.
SCLK 28 I Clock pin for I
2
C circuitry.
SDATA 27 I/O Data pin for I
2
C circuitry.
X1 5 I
Crystal Connection or Ex ternal Referenc e Frequenc y Input:
This pin has dual func tions. It can be used as an external 14.318-M Hz crystal connection or as an external
reference frequency input.
X2 6 I
Crystal Connection:
An input connect ion for an external 14.318-MHz crystal. If using
an external re ference, this pin must be left unconnected.
VDDQ3 1, 7, 15, 20,
31, 37, 45
P
Po wer Connection:
Pow er supply f or core logic , PLL circuitry, SDRAM output s buff ers,
PCI output buffers, reference output buffers and 48-MHz/24-MHz output buffers. Connect to 3.3V.
VDDQ2 50, 56 P
Po wer Connection:
Pow er supply for I OAPIC and CPU out put buff ers . Connect t o 2.5V
or 3.3V .
Page 3
W216
PRELIMINARY
3
Overview
The W216 was designed as a single-chip alternative to the
standard two-chip Intel 440BX AGPset clock solution. It provides suff icient outputs to support most single-processor, four
SDRAM DIMM designs.
Functional Description
I/O Pin Operation
Pins 2, 8, 9, 29, and 30 ar e dual-purpose l/O pins . Upon powerup these pins act as log ic in puts, all owing the det erminatio n of
assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or V
DD
. Connection to ground sets a
latch to “0,” connection to V
DD
sets a latch to “1.” Fig ure 1 an d
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W216 power-up, the first 2 ms of operation is used for
input logic selection. During t his period, the fi ve I/O pins (2, 8,
9, 29, 30) are three- stated, all owing the out put strapping resis-
tor on the l/O pins to pull the pins and their associated capacitive cloc k load to either a logi c HIGH or LO W st at e. At the end
of the 2-ms period, the establ ished logic “0” or “1” condition of
the l/O pin is latched. Next the output buffer is enabled, converting the l/O pins i nt o opera ting cloc k ou tpu ts. The 2-ms tim er starts when V
DD
reaches 2.0V. The input bits can only be
reset b y turning V
DD
off and then back on again.
It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output (<40Ω, nominal), which is minimally affected by the 10- kΩ strap to ground or V
DD
. As with the series
termination resistor, the output strapping resistor should be
placed as close to the l/O pin as possible in order to keep the
interconnecting trace short. The trace from the resistor to
ground or V
DD
should be kept less than two inches in length
to prevent system noise coupling duri ng input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that V
DD
has stabilized. If VDD has not yet reached
full value , output frequency initi ally ma y be belo w target b ut will
increase to target once V
DD
voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
GND 4, 10, 23, 26,
34, 42, 48, 53
G
Ground Connections:
Connect all ground pins to the common system ground plane.
Pin Definitions
(continued)
Pin Name Pin No.
Pin
Type Pin Description
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W216
V
DD
Clock Load
R
10 k
Ω
Output
Buffer
(Load Option 1)
10 k
Ω
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W216
V
DD
Clock Load
R
10 k
Ω
Output
Buffer
Output
Low
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Figure 2. Input Logic Selection Through Jumper Option
Resistor Value R
Page 4
W216
PRELIMINARY
4
Spread Spectrum Frequency Tim ing G enera to r
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occu pies. By increas ing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3.
As shown in Figure 3, a harmonic of a modulated clock has a
much low er amplitude th an that of an un modulated si gnal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log
10
(P) + 9*log10(F)
Where P is the perce nta ge of de viati on and F is the frequen cy
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in “Spread Spectrum
Clock Generation f or the Reducti on of Radiated Emissio ns” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviati on select ed for this chi p is speci fied in Table 6. Figure 4
details the Cypress spr eading pat tern. Cypress does offer options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
Spread Spectrum clocking is activated or deactivated by selecting the appropriate v al ues fo r bits 1–0 in data byte 0 of the
I
2
C data stream. Refer to Table 7 for more d e ta ils.
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
Spread
Spectrum
Enabled
EMI Reduction
Spread
Spectrum
Non-
Figure 4. Typica l Modulation Profile
MAX
MIN
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
FREQUENCY
Page 5
W216
PRELIMINARY
5
Serial Data Interface
The W216 features a two-pin, serial data int erface that can be
used to configure internal register settings that control particular de vice funct ions. Upon power -up , the W216 i nitiali zes wit h
default register settings, therefore the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chi p) and i s the dedi cated f unc tion of de v ice pi ns SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used duri ng system operation for power management functions. Ta b le 3 summarizes the control functions of
the serial data interface.
Operation
Data is written to the W216 in elev en bytes of eight bits each .
Bytes are written in the order sho w n in Table 4.
T able 3. Serial Data Interface Control Func ti ons Sum mary
Control Function Description Common Application
Output Disable Any indivi dual clock output(s) can be disabled. Dis-
abled outputs ar e actively held low.
Unused outputs are di sabled to reduce EMI
and system power. Examples are clock outputs to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI freque ncy selections alternate
to the selections that are provided by the FS0:3
pins. Frequency is changed in a smoot h and controlled fashion.
For alternate microprocessors and power
management options . Smooth freque ncy transition allows CPU frequency change under
normal system operation.
Spread Spectrum
Enabling
Enables or disab les spread spectrum cloc king. For EMI reducti on.
Output Three-state Puts all clock outputs into a high-impedance state. Production PCB testing.
T es t Mode All clock out put s toggl e in r elation t o X1 input, int er-
nal PLL is bypassed. Refer to Table 5.
Production PCB testing.
(Reserved) Reserved functio n for future de vice revisi on or pro-
duc tion devi c e testi ng.
No user application . Regist er bit must be wri tten as 0.
Table 4. Byte Writing Sequence
Byte Sequence Byte Name Bit Sequence Byte Description
1 Slave Address 11010010 C ommands the W216 to accept the bits in Data Bytes 0–7 for internal
register configuration. Since other devices may exist on the s am e com mon serial data b us, i t is neces sary to ha ve a sp eci fic s lav e address for
each potential receiver. The slave rec eiver address for the W216 is
11010010. Register sett ing will not be made if t he Slav e Address is not
correct (or is f or an alternate slave receiver).
2 Command
Code
Don’t Care Unused by the W216, ther efore bit values ar e ignored (“don’t care”). Thi s
byte must be included in the data write seq uence to mai ntain proper b yte
allocation. The Command Code Byte is part of the st and ard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus.
3 Byte Count Don’t Care Unused by the W216, ther efore bi t values ar e ignored (“don’t care”). This
byte must be included in the data write seq uence to mai ntain proper b yte
allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addr essed
slave receiver on the serial dat a bus.
4 Data Byte 0 Refer to Table 5 The dat a bit s in Dat a Bytes 0 –7 set internal W 216 regi sters that co ntrol
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to Table 5, Data Byte Serial Configuration Map .
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6 Don’t Care Unused by the W216, therefore bit values are ignored (“don’t car e ”).
11 Data Byte 7
Page 6
W216
PRELIMINARY
6
Writing Data Bytes
Each bit in Data Bytes 0–7 controls a particular devi ce funct ion
except for the “reserved” bits which must be written as a lo gic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 5 gives the bit formats for registers located in Data
Bytes 0–7.
Ta ble 6 details additional frequency selections that are available through th e seria l dat a interface .
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0–7 Seri al Conf iguration Map
Bit(s)
Affected Pin
Control Function
Bit Control
DefaultPin No. Pin Name 0 1
Data Byte 0
7-- -- (Reserved) -- -- 0
6 -- -- SEL2 Refer to Ta ble 6 0
5 -- -- SEL1 Refer to Ta ble 6 0
4 -- -- SEL0 Refer to Ta ble 6 0
3 -- -- Frequency Table Selection Frequency Con-
trolled by FS (3:0)
Table 2
Frequency Controlled by SEL (3:0)
Table 6
0
2 -- -- SEL3 Refer to Ta ble 6 0
1 -- Spread Spectrum -- OFF ON 0
0 -- Test Mode -- Normal Three-stat ed 0
Data Byte 1
7-- -- -- -- -- 0
6-- -- -- -- -- 0
5-- -- -- -- -- 0
4-- -- -- -- -- 0
3 46 SDRAM_F Clock Output Disable Low Active 1
2 49 CPU2 Clock Output Disable Low Active 1
1 51 CPU1 Clock Output Disable Low Active 1
0 52 CPU_F Clock Output Disable Low Active 1
Data Byte 2
7-- -- (Reserved) -- -- 0
6 8 PCI_F Clock Output Disable Low Active 1
5 16 PCI5 Clock Output Disable Low Active 1
4 14 PCI4 Clock Output Disable Low Active 1
3 13 PCI3 Clock Output Disable Low Active 1
2 12 PCI2 Clock Output Disable Low Active 1
1 11 PCI1 Clock Output Disable Low Active 1
0 9 PCI0 Clock Output Disable Low Active 1
Data Byte 3
7-- -- (Reserved) -- -- 0
6-- -- (Reserved) -- -- 0
5 29 48MHz Clock Output Disable Low Active 1
4 30 24MHz Clock Output Disable Low Active 1
3 33, 32,
25, 24
SDRAM12:15 Clock Output Disable Low Active 1
Page 7
W216
PRELIMINARY
7
2 22, 21,
19, 18
SDRAM8:11 Clock Output Disable Low Active 1
1 39, 38,
36, 35
SDRAM4:7 Clock Output Disable Low Active 1
0 44, 43,
41, 40
SDRAM0:3 Clock Output Disable Low Active 1
Data Byte 4
7-- -- (Reserved) -- -- 0
6-- -- (Reserved) -- -- 0
5-- -- (Reserved) -- -- 0
4-- -- (Reserved) -- -- 0
3-- -- (Reserved) -- -- 0
2-- -- (Reserved) -- -- 0
1-- -- (Reserved) -- -- 0
0-- -- (Reserved) -- -- 0
Data Byte 5
7-- -- (Reserved) -- -- 0
6-- -- (Reserved) -- -- 0
5 54 IOAPIC_F Disabled Low Active 1
4 55 IOAPICO Disabled Low Active 1
3-- -- (Reserved) -- -- 0
2-- -- (Reserved) -- -- 0
1 2 REF1 Clock Output Disable Low Active 1
0 3 REF0 Clock Output Disable Low Active 1
Table 5. Data Bytes 0–7 Serial Configuration Map
(continued)
Bit(s)
Affected Pin
Control Function
Bit Control
DefaultPin No. Pin Name 0 1
Page 8
W216
PRELIMINARY
8
Note:
2. CPU and PCI frequency selections are listed in
Table 2
and
Table 6
.
T able 6. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions Output Frequency Spread On
Data Byte 0, Bit 3 = 1
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz) Spread Percenta ge
Bit 2
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
1111 133.333.3 (CPU/4)–0.5% Down
1110 12431 (CPU/4)–0.5% Down
1101 15037.5 (CPU/4)–0.5% Down
1100 14035 (CPU/4)–0.5% Down
1011 10535 (CPU/3)–0.5% Down
1010 11036.7 (CPU/3)–0.5% Down
1001 11538.3 (CPU/3)–0.5% Down
1000 12040 (CPU/3)–0.5% Down
0111 10033.3 (CPU/3)–0.5% Down
0110 Reserved –0.5% Down
0101 11237.3 (CPU/3) –0.5% Down
0100 10334.3 (CPU/3)–0.5% Down
0011 66.833.4 (CPU/2)–0.5% Down
0010 83.341.7 (CPU/2)–0.5% Down
0001 7537.5 (CPU/2)–0.5% Down
0000 Reserved –0.5% Down
T able 7. Select Function for Data Byte 0, Bits 0:1
Function
Input Conditions Output Conditions
Data Byte 0
CPU_F, 1:2
PCI_F,
PCI0:5
REF0:1,
IOAPIC0,_F 48MHZ 24MHZBit 1 Bit 0
Normal Operation 0 0 Note 2 Note 2 14.318 MHz 48 MHz 24 MHz
Spread Spectrum 1 0 Note 2 Note 2 14.318 MHz 48 MHz 24 MHz
Three-state X 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Page 9
W216
PRELIMINARY
9
Absolute Maximum Ratings
Stresses gre ater th an those list ed i n this tab le may cause permanent damage to the de vice. These represent a str ess ratin g
only. Operation of the device at these or any other conditions
above those specified in the operating sect ions of this spec if ication is not implied. Maximum conditions for extended periods may affect reliability.
.
Parameter Description Rating Unit
V
DD
, V
IN
V oltage on any pin with respect to GND –0.5 to +7 .0 V
T
STG
Storage Temperature –65 to +150 °C
T
B
Ambient Temperature under Bias –55 to +125 °C
T
A
Operating Temperature 0 to +70 °C
ESD
PROT
Input ESD Protection 2 (min.) kV
DC Electr i cal C h ar acteristics:
TA = 0°C to +70°C, V
DDQ3
= 3.3V±5%, V
DDQ2
= 2.5V±5%
Parameter Description Test Condition Min. Typ. Max. Unit
Supply Current
I
DD
3.3V Supply Current CPU_F, 1:2 = 100 MHz
Outputs Loaded
[3]
320 mA
I
DD
2.5V Supply Current CPU_F, 1:2 = 100 MHz
Outputs Loaded
[3]
40 mA
Logic Inputs
V
IL
Input Low V oltage GND – 0.3 0.8 V
V
IH
Input High V oltage 2.0 VDD + 0.3 V
I
IL
Input Low Current
[4]
–25 µA
I
IH
Input High Current
[4]
10 µA
I
IL
Input Low Current (SEL100/66#) –5µA
I
IH
Input High Current (SEL100/66#) +5 µA
Clock Outputs
V
OL
Output Low Voltage I
OL
= 1 mA 50 mV
V
OH
Output High Voltage IOH = –1 mA 3.1 V
V
OH
Output High Voltage CPU_F, 1:2 IOAPIC IOH = –1 mA 2.2 V
I
OL
Output Low Current CPU_F , 1:2 VOL = 1.25V 60 73 85 mA
PCI_F, PCI0:5 V
OL
= 1.5V 96 110 130 mA
IOAPIC0, IOAPIC_F V
OL
= 1.25V 72 92 110 mA
REF0:1 V
OL
= 1.5V 61 71 80 mA
48-MHz V
OL
= 1.5V 60 70 80 mA
24-MHz V
OL
= 1.5V 60 70 80 mA
SDRAM0:15,_F V
OL
= 1.5V 95 110 130 mA
I
OH
Output High Current CPU_F, 1:2 VOL = 1.25V 43 60 80 mA
PCI_F, PCI0:5 V
OL
= 1.5V 76 96 120 mA
IOAPIC0, IOAPIC_F V
OL
= 1.25V 60 90 130 mA
REF0:1 V
OL
= 1.5V 50 60 72 mA
48-MHz V
OL
= 1.5V 50 60 72 mA
24-MHz V
OL
= 1.5V 50 60 72 mA
SDRAM0:15,_F V
OL
= 1.5V 75 95 120 mA
Notes:
3. All clock outputs loaded with 6" 60Ω transmission lines with 22-pF capacitors.
4. W216 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.
Page 10
W216
PRELIMINARY
10
AC Electrical Characteristics
T
A
= 0°C to +70°C, V
DDQ3
= 3.3V±5%,V
DDQ2
= 2.5V± 5% f
XTL
= 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock o utput; S pr ead Sp ec trum is disabled.
Notes:
5. X1 input threshold voltage (typical) is V
DDQ3
/2.
6. The W216 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;
this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Crystal Oscillator
V
TH
X1 Input Threshold Voltage
[5]
V
DDQ3
= 3.3V 1.65 V
C
LOAD
Load Capacitance, Imposed on
External C rys tal
[6]
14 pF
C
IN,X1
X1 Input Capacitance
[7]
Pin X2 unconnected 28 pF
Pin Capacitance/Induct ance
C
IN
Input Pin Capacitance Except X1 and X2 5 pF
C
OUT
Output Pin Capacitance 6pF
L
IN
Input Pin Inductance 7nH
CPU Clock Outputs, CPU_F, 1:2 (Lump Capacitance Test Load = 20 pF)
Parameter Description
T est Condi tion/
Comments
CPU = 66.8 MHz CPU = 100 MHz CPU = 133 MHz
UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.
t
P
Period Measured on rising edge
at 1.25
15 15.5 10 10.5 7.5 8.0 ns
t
H
High Time Duration of clock cycle
above 2.0V
5.2 3.0 1.87 ns
t
L
Low Time Duration of clock cycle
below 0.4V
5.0 2.8 1.67 ns
t
R
Output Rise
Edge Rate
Measured from 0.4V to
2.0V
141414V/ns
t
F
Output F all Edge
Rate
Measured from 2.0V to
0.4V
141414V/ns
t
D
Duty Cycle Measured on rising and
fall ing edge at 1.25V
45 55 45 55 45 55 %
t
JC
Jitter,
Cycle-to-Cycle
Measured on rising edge
at 1.25V. Maximum difference of cycle time between two a djacent cycles.
250 250 250 ps
t
SK
Output Skew Measured on rising edge
at 1.25V
175 175 175 ps
f
ST
Frequency
Stabilization
from Power-up
(cold start)
Assumes full supply voltage reached within 1 ms
from power- up. Short cycles exist prior to frequency stabilization.
333ms
Z
o
AC Output
Impedance
Average value during
switching transition. Used
for determining series termination value.
20 20 20 Ω
DC Electr i cal C h ar acteristics:
TA = 0°C to +70°C, V
DDQ3
= 3.3V±5%, V
DDQ2
= 2.5V±5% (continued)
Parameter Description Test Condition Min. Typ. Max. Unit
Page 11
W216
PRELIMINARY
11
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF
Parameter Description Test Conditi on/Comments Min. Typ. Max. Unit
t
P
Period Measured on rising edge at 1.5V 30 ns
t
H
High Time Duration of clock cycle abov e 2.4V 12 ns
t
L
Low Time Duration of clock cycle belo w 0.4V 12 ns
t
R
Output Rise Edge Rate Measured f rom 0.4V to 2.4V 1 4 V/ns
t
F
Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns
t
D
Duty Cycle Measured on rising and falling edge at 1.5V 45 55 %
t
JC
Jitter , Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum
differ ence of cyc le time be tween tw o adjacent cycles .
250 ps
t
SK
Output Skew Measured on rising edge at 1.5V 500 ps
t
O
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1.5 4 ns
f
ST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3ms
Z
o
AC Output Impeda nce Average val ue duri ng switching transition. Used for
determining series termination value.
15 Ω
IOAPIC0 and IOAPIC_F Clock Outp uts (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments Min. Typ. Max. Unit
f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz
t
R
Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns
t
F
Output Fal l Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns
t
D
Duty Cycle Measured on rising and falling edge at 1.25V 45 55 %
f
ST
Frequency St abilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabi li zation.
1.5 ms
Z
o
AC Output Impedance Average val ue during switchi ng transition. Used
for determining seri es termination value.
15 Ω
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments Min. Typ. Max. Unit
f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz
t
R
Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns
t
F
Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns
t
D
Duty Cycle Measured on rising and falling edge at 1.5V 45 55 %
f
ST
Frequency St abilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabi li zation.
3ms
Z
o
AC Output Impedance Average val ue during switchi ng transition. Used
for determining seri es termination value.
25 Ω
Page 12
W216
PRELIMINARY
12
SDRAM 0:15,_F Clock Outputs (Lump Capacitance Test Load = 22 pF)
Parameter Description
T est Condi tion/
Comments
SDRAMIN =
66.8 MHz
SDRAMIN =
100 MHz
SDRAMIN =
133 MHz
UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.
t
P
Period Measured on rising edge
at 1.5V
15 15.5 10 10.5 7.5 8.0 ns
t
H
High Time Duration of clock cycle
above 2.4V
5.2 3.0 1.87 ns
t
L
Low Time Duration of clock cycle
below 0.4V
5.0 2.0 1.67 ns
t
R
Output Rise
Edge Rate
Measured from 0.4V to
2.4V
141414V/ns
t
F
Output F all Edge
Rate
Measured from 2.4V to
0.4V
141414V/ns
t
D
Duty Cycle Measured on rising and
fall ing edge at 1.5V
45 55 45 55 45 55 %
t
SK
Output Skew Measured on rising and
fall ing edge at 1.5V
250 250 250 ps
t
PD
Propagation
Delay
Measured from SDRAMIN 3.7 3.7 3.7
ns
Z
o
AC Output
Impedance
Average value during
switching transition. Used
for determining series termination value.
15 15 15 Ω
48-MHz Clock Output (Lump Capacit ance Test Load = 20 pF)
Parameter Description Test Condition/Comments Min. Typ. Max. Unit
f Freque ncy, Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz
f
D
Deviation from 48 MHz (48.008 – 48)/48 +167 ppm
m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17
t
R
Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns
t
F
Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns
t
D
Duty Cycle Measured on rising and falling edge at 1.5V 45 55 %
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply vol tage reached withi n 1 ms
from power-up. Short cycles exist prior to frequency stabilization.
3ms
Z
o
AC Output Impedance Average value during switching transition. Used
for determining seri es termi nation value.
25 Ω
Page 13
W216
PRELIMINARY
13
Document #: 38-00850
24-MHz Clock Output (Lump Capacit ance Test Load = 20 pF)
Parameter Description Test Condition/Comments Min. Typ. Max. Unit
f Freque ncy, Actual Determined by PLL divider ratio (see m/n below) 24.004 MHz
f
D
Deviation from 24 MHz (24.004 – 24)/24 +167 ppm
m/n PLL Ratio (14.31818 MHz x 57/34 = 24.004 MHz) 57/34
t
R
Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns
t
F
Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns
t
D
Duty Cycle Measured on rising and falling edge at 1.5V 45 55 %
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply vol tage reached withi n 1 ms
from power-up. Short cycles exist prior to frequency stabilization.
3ms
Z
o
AC Output Impedance Average value during switching transition. Used
for determining seri es termi nation value.
25 Ω
Ordering Information
Ordering Code
Package
Name Package Type
W216 H 56-pin SSOP (300 mils)
Page 14
W216
PRELIMINARY
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
56-Pin Small Shrink Outlin e P ackage (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
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