Datasheet W194-70 Datasheet (Cypress)

Frequency Multiplier and Zero Delay Buffer

W194

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
January 5, 2000, rev. *A

Features

• T wo outputs

• Configuration opti ons allow v arious mul tipl ications of
the reference frequency—refer to

Table 1

to determi ne
the specific option which meets your mul ti plication
needs

• Available in 8-pin SOIC package

Key Specific ati o n s

Operating Voltage: .............................. 3.3V±5% or 5.0±10%

Operating Range: .......................10 MHz < f

OUT1

< 133 MHz

Absolute Jitter: .........................................................±500 ps

Output to Output Skew: ...................................... ........250 ps

Propagation Delay: .................. ...................... ...........±350 ps

Propagation delay is affected by input rise time.

T able 1. Configuration Options

FBIN FS0 FS1 OUT1 OUT2

OUT1 0 0 2 X REF REF
OUT1 1 0 4 X REF 2 X REF
OUT1 0 1 REF REF/2
OUT1 1 1 8 X REF 4 X REF
OUT2 0 0 4 X REF 2 X REF
OUT2 1 0 8 X REF 4 X REF
OUT2 0 1 2 X REF REF
OUT2 1 1 16 X REF 8 X REF

Block Diagram

Pin Configuration

÷Q

FS0
FS1

Reference

FBIN

Phase

Detector

Charge

Pump

Loop
Filter

VCO

÷2

Output

Buffer

OUT1

OUT2

Output

Buffer

External feedback connection to
OUT1 or OUT2, not both

Input

IN

OUT2
VDD
OUT1
FS1

8
7
6
5

FBIN

IN

GND

FS0

1
2
3
4

SOIC

W194

2

Overview

The W194-70 is a two-output zero del ay buff er and frequency
multiplier. It pro vides an e xternal f eedbac k pat h allo wing max­imum flexibility when implementing the Zero Delay feature.
This is explained further in the secti ons of t his d ata she et title d

“How to Implement Zero Delay,” and “Inser ting Other Devices
in Feedback Path.”

The W194-70 is a pin-compatible upgrade of the Cypress
W42C70-01. The W194-70 addresses some application de­pendent probl ems experienced by users of the older device.

Pin Definitions

Pin Name Pin No.

Pin

Ty pe Pin Description

IN 2 I

Reference Input:

The output signals wil l be synchronize d to this signal.

FBIN 1 I

Feedback Input :

This input must be f ed b y one of th e outputs ( OUT1 or OUT2) to ensure
proper funct ionality. If the tr ace between FBIN and t he output pin being used for feedb ack
is equal in length to the tr aces bet ween the out put s and the si gnal dest inat ions, then the
signals received at the destinations will be synchronized to the REF signal input (IN).

OUT1 6 O

Output 1:

The frequency of the signal provided by this pin is determined by the f eedback

signal connect ed to FBIN, and the FS0:1 inputs (see Table 1).

OUT2 8 O

Output 2:

The frequenc y of t he s ignal prov id ed by this pin is on e-half of t he fr equenc y of

OUT1. See Table 1.

VDD 7 P

Power Connect i ons:

Connect to 3.3V or 5 V. This pin shoul d be b ypasse d with a 0. 1- µF
decoupling capacitor. Use ferrite beads to help reduce noise f or optimal jitter per for­mance.

GND 3 P

Ground Connection:

Connect all grounds to the common system ground plane.

FS0:1 4, 5 I

Function Select Inputs:

Tie to V

DD

(HIGH, 1) or GND (LO W, 0) as desired per Table 1.

C8

G

Ferrite

Bead

Power Supply Connection

V+G

C

A

G

FS1FS0

GND

IN

FBIN

10 µF

0.01 µF

1

2
3

4

8

7

6

5

22

Ω

22

Ω

G

C9 = 0.1 µF

OUTPUT 1

OUTPUT 2

OUT 2

V

DD

OUT 1

Figure 1. Schematic/Suggested Layout

W194

3

How to Implement Zero Delay

Typically, zero delay buffers (ZDBs) are used because a de­signer wants to provide multiple copies of a clock signal in
phase with each other . The whole c oncept behin d ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve t his,
layou t must com pensate f or tra ce length be tween the ZDB an d
the target devices. The method of compensation is described
below.

External feedbac k is the trait that allows f or thi s compensati on.
The PLL on the ZDB will cause the feedback signal to be in
phase with the reference signal. When layi ng out the board,
match the trace lengths between the output being used for
feedback and the FBIN input to the PLL.

If it is desirable to either add a little delay, or slightly precede
the input signal, this m ay also be affec ted by either making the
trace to the FBIN pin a little shorter or a little longer than the
traces to the devices being clocked.

Inserti n g Other Devices in Feedback Path

Another nice feature available due to the external feedback is
the ability to synchronize signals to the signal coming from
some other de vi ce. This i mple mentati on can be ap pl ied to any

device (ASIC, multiple out put clock buffer/driver, etc.) which is
put into the feedback path.

Referring to Figure 2, if the traces between the ASIC/Buffer
and the destination of the clock signa l(s) (A) are equal in lengt h
to the trace between the buffer and the FBIN pin, the signals
at the destination(s) device will be driven HIGH at the same
time the Reference clock provided to the ZDB goes HIGH.
Synchronizing the other out puts of t he ZDB to the outputs f rom
the ASIC/Buff er is mor e comp le x ho we v er, as any propagati on
delay from the ZDB output to the ASIC/Buffer output must be
accounted for.

Reference

Signal

Feedback

Input

ASIC/
Buffer

Zero
Delay
Buffer

A

Figure 2. 6 Output Buffer in the Feedback Path

W194

4

Absolute Maximum Ratings

Stresses gre ater th an those list ed i n this tab le may cause per­manent damage to the de vice. These represent a str ess ratin g
only. Operation of the devic e at these or any other conditions

above those specified in the operating sections of t his specifi­cation is not implied. Maximum conditions for extended peri­ods may affect reliability.

.

Parameter Description Rating Unit

V

DD

, V

IN

V oltage on any pin with respect to GND –0.5 to +7 .0 V

T

STG

Storage Temperature –65 to +150 °C

T

A

Operating Temperature 0 to +70 °C

T

B

Ambient Temperature under Bias –55 to +125 °C

P

D

Power Dissipation 0.5 W

DC Electr i cal C h ar acteristi cs

:

T

A

= 0°C to 70°C, VDD = 3.3V ±5%

Parameter Description Test Condition Min Typ Max Unit

I

DD

Supply Current U nloaded, 100 MHz 17 35 mA

V

IL

Input Low Voltage 0.8 V

V

IH

Input High Voltage 2.0 V

V

OL

Output Low Voltage IOL = 12 mA

I

OL

= 8 mA

0.4 V

V

OH

Output High Voltage IOL = 12 mA

I

OL

= 8 mA

2.4 V

I

IL

Input Low Current VIN = 0V 5 µA

I

IH

Input High Current VIN = V

DD

5 µA

DC Electr i cal C h ar acteristi cs

:

T

A

= 0°C to 70°C, VDD = 5V ±10%

Parameter Description Test Condition Min Typ Max Unit

I

DD

Supply Current U nloaded, 100 MHz 17 35 mA

V

IL

Input Low Voltage 0.8 V

V

IH

Input High Voltage 2.0 V

V

OL

Output Low Voltage IOL = 12 mA

I

OL

= 8 mA

0.4 V

V

OH

Output High Voltage IOL = 12 mA

I

OL

= 8 mA

2.4 V

I

IL

Input Low Current VIN = 0V 5 µA

I

IH

Input High Current VIN = V

DD

5 µA

W194

5

Document #: 38- 00794-A

AC Electrical Characteristics:

TA = 0°C to +70°C, VDD = 3.3V ±5%

Parameter Description Test Condition Min Typ Max Unit

f

IN

Input Frequency

[1]

OUT2 = REF MHz

f

OUT

Output Frequency OUT1 15-pF load

[6]

10 133 MHz

t

R

Output Rise Time 2.0V to 0.8V, 15-pF load 3.5 ns

t

F

Output Fall Time 2.0V to 0.8V, 15-pF load 2.5 ns

t

ICLKR

Input Clock Rise Ti me

[2]

10 ns

t

ICLKF

Input Clock Fall Time

[2]

10 ns

t

PD

FBIN to REF Skew

[3, 4]

Measured at VDD/2 –20.62 ns

t

D

Duty Cycle 15-pF load

[5]

40 50 60 %

t

LOCK

PLL Lock Time Power supply stable 1.0 ms

t

JC

Jitter, Cycle- to - C yc le 300 ps

AC Electrical Characteristics:

TA = 0°C to +70°C, VDD = 5.0V ±10%

Parameter Description Test Condition Min Typ Max Unit

f

IN

Input Frequency

[1]

OUT2 = REF MHz

f

OUT

Output Frequency OUT1 15-pF load

[6]

10 133 MHz

t

R

Output Rise Time 2.0V to 0.8V, 15-pF load 2.5 ns

t

F

Output Fall Time 2.0V to 0.8V, 15-pF load 1.5 ns

t

ICLKR

Input Clock Rise Ti me

[2]

10 ns

t

ICLKF

Input Clock Fall Time

[2]

10 ns

t

PD

FBIN to REF Skew

[3, 4]

Measured at VDD/2 –20.62 ns

t

D

Duty Cycle 15-pF load

[5, 7]

40 50 60 %

t

LOCK

PLL Lock Time Power supply stable 1.0 ms

t

JC

Jitter, Cycle- to - C yc le 200 ps

Notes:

1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration).

2. Longer input rise and fall time will degrade skew and jitter performance.

3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.

4. Skew is measured at 1.4V on rising edges.

5. Duty cycle is measured at 1.4V.

6. For the higher drive -11, the load is 20 pF.

7. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case.

Ordering Information

Ordering Code Option

Package

Name Package Type

W194 -70 G 8-pin SOIC (150-mil)

W194

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagram

8-Pin Small Outlined Integrat ed Circuit (SOIC, 150-mil)