Datasheet W181-03, W181-02, W181-01 Datasheet (Cypress)

Peak Reducing EMI Solution

W181

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 21 , 2000, rev. *B

Features

•

Cypress PREMIS™ family offering

• Generates an EMI optimized c loc king signa l at the out­put

• Selectable i nput t o output frequency

• Single 1.25% or 3.75% dow n or center spread output

• Integrated loop filter components

• Operates with a 3.3V or 5V supply

• Low power CMOS design

• Available in 8-pin SOIC (Small Outline Integrated Cir­cuit) or 14-pin TSSOP (Thin Shrink Sm all Outline Pac k­age select options only)

Key Specifications

Supply Voltages: .... .......... ... ......... ... .. .......... ..VDD = 3.3V±5%

or V

DD

= 5V±10%

Frequency Range: ................... .........28 MHz ≤ F

in

≤

75 MHz

Crystal Reference Range.................. 28 MHz ≤ F

in

≤

40 MHz

Cycle to Cy c le Ji tte r: .. ... ......... ... .. .......... ... ....... 300 ps (max .)

Selectabl e Spread Percentage: ....................1.25% or 3.75%

Output Duty Cycle: ............................... 40/60% (worst case)

Output R is e a n d Fall Tim e : .......... ... .......... .. ......... 5 ns (max.)

T able 1. Modulation Width Selection

SS%

W181-01, 02, 03

Output

W181-51, 52, 53

Output

0F

in

≥

F

out

≥

F

in

–

1.25%

F

in

+ 0.625% ≥ F

in

≥

– 0.625%

1F

in

≥

F

out

≥

F

in

–

3.75%

F

in

+ 1.875% ≥ F

in≥

–1.875%

Table 2. Frequency Range Selection

W181 Option#

FS2 FS1

-01, 51
(MHz)

-02, 52
(MHz)

-03, 53
(MHz)

0 0 28 ≤ F

IN

≤

38 28 ≤ F

IN

≤

38 N/A

0 1 38 ≤ F

IN

≤

48 38 ≤ F

IN

≤

48 N/A

1 0 46 ≤ F

IN

≤

60 N/A 46 ≤ F

IN

≤

60

1 1 58 ≤ F

IN

≤

75 N/A 58 ≤ F

IN

≤

75

PREMIS is a trademark of Cypress Semiconductor Corporation.

Simplified Block Diagram

Pin Configurations

W181-02/03

8
7

6
5

1
2

3
4

CLKIN or X1

NC or X2

GND
SS%

SSON#
FS1

VDD
CLKOUT

W181-01/51

8
7
6
5

1
2
3
4

CLKIN or X1

NC or X2

GND
SS%

FS2
FS1
VDD
CLKOUT

SOIC

Spread Spectrum

W181

(EMI suppressed)

3.3 or 5.0V

Oscilla tor or

Spread Spectrum

W181

(EMI suppressed)

3.3 or 5.0V

XTAL

X1

X2

Reference Input

Input

Output

Output

40 MHz

Max.

W181-01

8

1
2
3
4

CLKIN or X1

NC or X2

GND
SS%

NC

FS1

VDD

CLKOUT

5
6

7

9

10

11

12

13

14

FS2

NC

NC

NC

NC

NC

TSSOP

W181-52/53

W181

2

Pin Definitions

Pin Name

Pin No.

(SOIC)

Pin No.

(TSSOP)(-01)

Pin

Type Pin Description

CLKOUT 5 8 O

Output Modulated Frequency

: Frequency modulated copy

of the unmodulated input clock (SSON# asserted).

CLKIN or X1 1 2 I

Crystal Connection or External Reference Frequency In­put:

This pin has dual functi ons. It may eit her be connected

to an external crystal , or t o an external ref erence clock.

NC or X2 2 3 I

Crystal Connection:

If using an e xternal refere nce, this pin

must be left unconnected.

SSON# 8(02/03/52/

53)

-- I

Spread Spectrum Control (Active LO W):

Asserting this si g­nal (active LO W) turns the inte rnal modulation wa v eform on.
This pin has an internal pull- down resistor.

FS1:2 7, 8 (01/51) 12, 1 I

Frequency Selection Bit(s) 1 and 2:

These pins select the
frequency ra nge of operation. Refer to Table 2. These pins
have internal pull-up resistors.

SS% 4 6 I

Modulation Width Selection:

When Spread Spectrum fea­ture is turned on, this pin is used to sel ect the amount of
variation and peak EMI reduction that is desired on th e output
signal. This pin has an internal pull-up resistor.

VDD 6 10 P

Po wer Connec tion:

Connected to 3.3V or 5V pow er supply.

GND 3 4 G

Ground Connection:

Connect all ground pins to the com-

mon system groun d plane.

NC 5, 7, 9, 11, 13,

14

NC

No Connection.

W181

3

Overview

The W181 products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advanc es in PLL spread spectrum frequency synthesizer t ech­niques. By frequency modulating the output with a low­frequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shieldi ng or redesign.

In a system, not only i s EMI reduce d in the v arious cl oc k li nes,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and dat a lines in the syst em. The Sim­plified Block Diagram on page 1 shows a simple implementa­tion.

Functional Description

The W181 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detec tor also. The PLL will f or ce the fr equen cy of
the VCO output sign al to change until the divided out put signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q

times the ref er ence fre quenc y. (Note: F or t he W181 t he outpu t
frequency is eq ual to the input frequency.) Th e unique feature
of the Spread Spect rum Fr equ ency Timi ng Gener ator is that a
modulating wa vef orm is supe rimposed at t he input to the VCO .
This causes the VCO output to be slowly swept across a pre­determined frequency ban d.

Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro­cess has little impact on system performance.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generation, EMI re­duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be va ried .

Using frequency s elect bits (FS1:2 pins), the frequency range
can be set. Spr eading p erc entage i s set to be 1 .25% o r 3 .75%
(see Tabl e 1).

A larger spreading per centage improves EMI reduction. How­ever, large spread percentages may either exceed system
maximum frequ ency ra tings o r lo wer the a v er age fr equency t o
a point where performance is affected. For these reasons,
spreading percentages between 0.5% and 2.5% are most
common.

Freq. Phase

Modulating

VCO

Post

CLKOUT

Detector

Charge

Pump

Waveform

DividersDivider

Feedback

Divider

PLL

GND

V

DD

Σ

Q

P

Clock Input

Reference Input (EMI suppressed)

Figure 1. Functional Block Diagram

W181

4

Spread Spectrum Frequency Timing Genera­tion

The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occu pies. By increas ing
the bandwidth of the fundamental and its harmonics, the am­plitudes of the radiated electromagnetic emissions are re­duced. This effect is depicted in Figure 2.

As shown in Figure 2, a harmonic of a modulated clock has a
much low er amplitude t han that of an un modulated si gnal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:

dB = 6.5 + 9*log

10

(P) + 9*log10(F)

Where P is the perce ntag e of de viati on an d F is the frequency
in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Gener ation f or the Redu ct ion of Radiat ed Emiss ions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiat ed electro magnetic emis sions. Figure
3 details the Cypress spreading pattern. Cypress does offer
options with more spread and gr eater EMI reduction. Cont act
your local Sales representativ e for details on these devices.

SSFTG Typical Clock

Frequency Span (MHz)

Amplitude (dB)

Spread

Spectrum

Enabled

EMI Reduction

Spread

Spectrum

Non-

Frequency Span (MHz)

Down Spread

Amplitude (dB)

Center Spread

Figure 2. Clock Har monic with and without SSCG Modulat ion Frequenc y Domain Represent ation

MAX.

MIN.

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

FREQUENCY

Figure 3. Typical Modulation Prof ile

W181

5

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause per­manent damage to the de vice . These represent a stress ratin g
only. Operation of the devi ce at these or any other conditions

above those specified in the operating sections of this specifi­cation is not implied. Maximum conditions for extended peri­ods may affect reliability.

Parameter Description Rating Unit

V

DD

, V

IN

Voltage on any pin with respect to GND –0.5 to +7 .0 V

T

STG

Storage Temperature –65 to +150 °C

T

A

Operating Tempera tur e 0 to +70 °C

T

B

Ambient Temperature under Bias –55 to +125 °C

P

D

Power Dissi pation 0.5 W

DC Electr i cal C h ar acteristics

:

0°C < T

A

< 70°C, VDD = 3.3V ±5%

Parameter Description Test Conditi on Min. Typ. Max. Unit

I

DD

Supply Current 18 32 mA

t

ON

Po wer-Up Time First locked clock cycle after Power

Good

5ms

V

IL

Input Low Voltage 0.8 V

V

IH

Input High Vol tage 2.4 V

V

OL

Output Low Voltage 0.4 V

V

OH

Output High Voltage 2.4 V

I

IL

Input Low Current Note 1 –100 µA

I

IH

Input High Current Note 1 10 µA

I

OL

Output Low Current @ 0.4V, VDD = 3.3V 15 mA

I

OH

Output High Current @ 2.4V, VDD = 3.3V 15 mA

C

I

Input Capacitance All pins except CLKIN 7 pF

C

I

Input Capacitance CLKIN pin only 6 10 pF

R

P

Input Pull-Up Resistor 500 kΩ

Z

OUT

Clock Output Imp edance 25 Ω

Note:

1. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.

W181

6

DC Electr i cal C h ar acteristics:

0°C < T

A

< 70°C, VDD = 5V ±10%

Parameter Description Test Condition Min. Typ. Max. Unit

I

DD

Supply Current 30 50 mA

t

ON

Power-Up Time First locked clock cycle after

Power Good

5ms

V

IL

Input Low Voltage 0.15V

DD

V

V

IH

Input High Voltage 0.7V

DD

V

V

OL

Output Low Voltage 0.4 V

V

OH

Output High Voltage 2.4 V

I

IL

Input Low Current Note 1 –100 µA

I

IH

Input High Current Note 1 10 µA

I

OL

Output Low Current @ 0.4V, VDD = 5V 24 mA

I

OH

Output High Current @ 2.4V, VDD = 5V 24 mA

C

I

Input Capacitance All pins except CLKIN 7 pF

C

I

Input Capacitance CLKIN pin only 6 10 pF

R

P

Input Pull-Up Resistor 500 kΩ

Z

OUT

Clock Output I mpedance 25 Ω

AC Electrical Characteristics:

TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10%

Parameter Description T est Condition Min. Typ. Max. Unit

f

IN

Input Frequency I nput Clock 28 75 MHz

f

OUT

Output Frequency Spr ead Off 28 75 MHz

t

R

Output Rise Time VDD, 15-pF load 0.8V–2.4V 2 5 ns

t

F

Output Fall Time VDD, 15-pF load 2.4V–0.8V 2 5 ns

t

OD

Output Duty Cycle 15-pF load 40 60 %

t

ID

Input Duty Cycle 40 60 %

t

JCYC

Jitter, Cycle-to-Cycle 250 300 ps
Harmonic Reduction f

out

= 40 MHz, thir d harmonic
measured, ref erence board,
15-pF load

8dB

W181

7

Application Information

Recommended Circui t Configuration

For optimum performance in system applications the power
supply decoupli ng scheme sho wn in Figure 4 should be used .

V

DD

decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V

DD

pin as possible, otherwise the in-

creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V

DD

connection can be

made via a ferrite bead, as shown.

Recommended Board Layout

Figure 5 shows a recommended 2-layer board layout.

Document #: 38-00790-B

Figure 4. Recommended Circuit Configuration

GND

W181

8
7
6
5

1
2
3
4

C1

FB

C2

3.3 or 5V System Supply
10

µF Tantalum

0.1

µF

Clock

Reference Input

NC

Output

R1

Ordering Information

Ordering Code

Freq. Mask

Code

Package

Name Package Type

W181 01, 02, 03

51, 52, 53

G 8-pin Plastic SOIC (150-mil)

W181 01 X 14-pin Plastic TSSOP

Figure 5. Recommended Board Layout (2-Layer Board)

Clock Output

High frequency supply decoupling
capacitor (0.1-

µF recommended).

Common supply low frequency
decoup ling capacitor (10-

µF tantalum

recommended).

FB

Ferrite Bead

C1 =

C2 =

Match value to line impedance

R1 =

=

R1

C1

C2

G

G

FB

=

Via To GND Plane

G

Reference Input

NC

G

Power Supply Input

(3.3 or 5V)

W181

8

Package Diagram

14-pin Thin Shrink Small Outline Package

W181

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it conv ey or imply any lice nse under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagram

(continued)

8-Pin Sm a ll O u tl in e In te g ra ted Circuit (S O I C , 15 0 mils)