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Spread Aware™, Zero Delay Buffer
W163
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
February 21, 2000, re v. *A
Features
• Spread Aware™—designed to work with SSFTG
reference signals
• Outputs may be three-stated
• Available in 8-pin SOIC package
• Extra strength output drive available (-15 version)
• Internal feedback maximized the number of outputs
available in 8-pin package
Key Specifications
Operating Voltage: ................................................3.3V±10%
Operating Range: ................................ 10 < f
OUT
< 133 MHz
Cycle-to-Cycle Jitter: ..................................................200 ps
Output-to-Ou tp u t S kew: ... .......... ......... .......... .......... ....250 p s
Device-to-Device S kew:...... .......... .......... ......... ............700 p s
Propagation Delay:......................................................350 ps
Spread Aware is a trademark of Cypress Semiconductor Corporati on.
Block Diagram
Pin Configuration
Q0
PLL
REF
Q1
Q2
Q3
QFB
QFB
VDD
8
7
6
5
REF
Q0
Q1
GND
1
2
3
4
Q3
Q2
SOIC
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Overview
The W163 products are five-output zero delay buffers. A
Phase-Lock ed Loop (PLL) i s used to tak e a time- varying signal
and provide five copies of that same signal out. The internal
feedback to the PLL provides outputs in phase with the reference inputs.
Spread Aware
Many syst em s being designed now util ize a technology called
Spread Spectrum F requency Timi ng Generation . Cypress has
been one of the pioneers of SSFTG development, and we designed this product so as not to filter off t he Spread Spectrum
featur e of the Referen ce input, assuming i t ex ists. When a z ero
delay buffer is not designed to pass the SS feature through,
the result is a significant amount of tracking skew which may
cause problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology,
please see the Cypress Applic ation not e titled , “EMI Suppression Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.”
Schematic
Pin Definitions
Pin Name Pin No.
Pin
Typ e Pin Description
REF 1 I
Reference Input:
The output signals Q0:3 will be synchronized to this signal
unless the device is programmed to bypass the PLL.
Q0:3 2, 3, 5, 7 O
Outputs:
These signal s will be synchronous a nd of equal f requency t o the signal
input at pin 1.
QFB 8 O
Feedback Output:
This output signal does no t vary from signal s Q0:3 in func tion,
but is noted as the signal used to establish the propagation delay of nearly 0.
VDD 6 P
Po we r Connections:
Connect to 3.3V. Use ferrite beads to help reduce noise
for optimal jit te r p e rformance.
GND 4 P
Ground Connections:
Connect all grounds to the common system ground
plane.
Q0
Q1
GND
QFB
Q3
VDD
Q2
V
DD
Ferrite
Bead
10
µ
F0.1 µF
REF
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Absolute Maximum Ratings
Stresses gre ater th an those list ed i n this tab le may cause permanent damage to the de vice. These represent a str ess ratin g
only. Operation of the device at these or any other conditions
above those specified in the oper ating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
.
Parameter Description Rating Unit
V
DD
, V
IN
V oltage on any pin with respect to GND –0.5 to +7 .0 V
T
STG
Storage Temperat ure –65 to +150 °C
T
A
Operating Temperature 0 to +70 °C
T
B
Ambient Temperature under Bias –55 to +125 °C
P
D
Power Dissipation 0.5 W
DC Electr i cal C h ar acteristi cs
:
T
A
=0°C to 70°C, VDD = 3.3V ±10%
Parameter Description Test Condition Min Typ Max Unit
I
DD
Supply Current Unloaded, 100 MHz 40 mA
V
IL
Input Low Voltage 0.8 V
V
IH
Input High Voltage 2.0 V
V
OL
Output Low Voltage IOL = 12 mA (-15)
I
OL
= 8 mA (-5)
0.4 V
V
OH
Output High Voltage IOL = 12 mA (-15)
I
OL
= 8 mA (-5)
2.4 V
I
IL
Input Low Current VIN = 0V 50 µA
I
IH
Input High Current VIN = V
DD
100 µA
AC Electrical Characteristics:
TA = 0°C to +70°C, VDD = 3.3V ±10%
Parameter Description Test Condition Min Typ Max Unit
f
IN
Input Frequency 10 133 MHz
f
OUT
Output Frequency 15-pF load
[5]
10 133 MHz
t
R
Output Rise Time (-05)
[1]
2.0 to 0.8V, 15-pF load 2.5 ns
Output Rise Time (-15)
[1]
2.0 to 0.8V, 20-pF load 1.5 ns
t
F
Output Fall Time (-05)
[1]
2.0 to 0.8V, 15-pF load 2.5 ns
Output Rise Time (-15)
[1]
2.0 to 0.8V, 20-pF load 1.5 ns
t
ICLKR
Input Clock Rise Ti me
[1]
?ns
t
ICLKF
Input Clock Fall Time
[1]
?ns
t
PD
FBIN to REF Skew
[2, 3]
Measured at VDD/2 –350 0 350 ps
t
SK
Output to Output Skew All outputs loaded equally –250 0 250 ps
t
SKDD
Device to De vice Skew Measured at FBIN pins,
V
DD
/2
–700 0 700 ps
t
D
Duty Cycle 15-pF load
[4]
45 50 55 %
t
LOCK
PLL Lock Time Power supply stable and 1.0 ms
t
JC
Jitter, Cycle- to - C yc le 200 ps
Notes:
1. Longer input rise and fall time will degrade skew and jitter performance.
2. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.
3. Skew is measured at 1.4V on rising edges.
4. Duty cycle is measured at 1.4V.
5. For the higher drive -15, the load is 20 pF.
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© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 38-00787-*A
Ordering Information
Ordering Code Option
Package
Name Package Type
W163 -05, -15 G 8-pin Plastic SOIC (150-mil)
Package Diagram
8-Pin Small Outline Integrated Circuit (SOIC, 150-mil)
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