Datasheet W132 Datasheet (Cypress)

W132

Spread Aware™, Ten/Eleven Output Zero Delay Buffer

Features

• Spread Aware™—designed to work with SSFTG refer­ence signals

• Well suited to both 100- and 133-MHz designs

• Ten (-09B) or Eleven (-10B) LVCMOS/LVTTL outputs

• Single output enable pin for -10 version, dual pins on

-09 devices allow shutting down a portion of the out­puts.

• 3.3V power supply

• On board 25Ω damping resistors

• Available in 24-pin TSSOP package

Block Diagram

FBIN
CLK

OE0:4

OE

OE5:8

configuration of these blocks dependent upon specific option being used

PLL

FBOUT

Q0
Q1

Q2

Q3

Q4

Q5
Q6
Q7
Q8

Q9

Key Specifications

Operating Voltage: ................................................3.3V±10%

Operating Range: ........................25 MHz < f

< 140 MHz

OUT

Cycle-to-Cycle Jitter: ................................................<150 ps

Output to Output Skew: ............................................<100 ps

Phase Error Jitter:.....................................................<125 ps

Pin Configurations

AGND

VDD

Q0
Q1

Q2
GND
GND

Q3

Q4

VDD

OE

FBOUT

AGND

VDD

Q0
Q1

Q2
GND
GND

Q3

Q4

VDD

OE0:4

FBOUT

10
11
12

10
11
12

W132-10B

W132-09B

24
23
22
21
20
19
18
17
16
15
14
13

24
23
22
21
20
19
18
17
16
15
14
13

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9

CLK
AVDD
VDD
Q9
Q8
GND
GND
Q7
Q6
Q5
VDD
FBIN

CLK
AVDD
VDD
Q8
Q7
GND
GND
Q6
Q5
VDD
OE5:8
FBIN

Spread Aware is a trademark of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 3, 1999, rev. **.1

Pin Definitions

Pin

Name

CLK 24 24 I
FBIN 13 13 I

Q0:8 3, 4, 5, 8,

Q9 n/a 21 O

FBOUT 12 12 O

AVDD 23 23 P

AGND 1 1 G
VDD 2, 10, 15, 222, 10, 14, 22P

GND 6, 7, 18, 196, 7, 18, 19G

Pin No.

(-09B)

9, 16, 17,

20, 21

Pin No.

(-10B)

3, 4, 5, 8,
9, 15, 16,

17, 20

Pin

Type Pin Description

Reference Input:
Feedback Input:

to ensure proper function ality. If the trace betw een FBIN and FBO UT is equal in
length to the traces between the outputs and the signal destinations, then the
signals receiv ed at the destin ations will be sy nchronized to the CLK signal inpu t.

O

Integrated Series Resisto r Ou tputs:

provided by these pins will be equal to the reference signal if properly laid out.
Each output has a 25Ω series damping resistor integrated.

Integrated Series Resistor Output:

provided by thi s pin will b e equal to the ref erenc e signal if pro perly laid out. This
output has a 25Ω series damping resistor integrated.

Feedback Output:

Typically it is connected d irectly t o the FBIN inpu t with a t race equ al in leng th to
the traces between outputs Q0:9 and the destination points of these output
signals.

Analog Powe r Connection:

noise for optimal jitter performance.

Analog Ground Connection:
Power Connections:

for optimal jitter performance.

Ground Connections:

Output signals Q0:9 will be synchronized to this signal.

This input mus t be fed by one of the o utputs (typically FBOUT)

The frequency and phase of the signa ls

The frequency and phase of the signal

This output has a 25Ω series resistor integrated on chip.

Connect to 3.3V. Use ferrite beads to help reduce

Connect to common system ground plane.

Connect to 3.3V. Use ferrite beads to help reduce noise

Connect to common system ground plane.

W132

OE n/a 11 I

OE0:4 11 n/a I

OE5:8 14 n/a I

Output Enable Input:

to GND (LOW, 0) all outputs are disabled to a LOW state.

Output Enable Input:

to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state.

Output Enable Input:

to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.

Overview

The W132 is a PLL-based c lock driver d esigned f or use in dual
inline memory modules. The clock driver has output frequen­cies of up to 133 MHz and output to output skews of less than
250 ps. The W132 provides minimum cycle-to-cycle and long
term jitter, which is of significant importance to meet the tight
input-to-input skew budget in DIMM applications.

The current generation of 256 and 512 megabyte memory
modules needs to support 100-MHz clocking speeds. Espe­cially fo r cards c onfigu red in 16 x4 or 8 x8 f o rmat, the cl oc k si g­nal provided from the motherboard is generally not strong
enough to meet all the requirements of the memory and logic

Tie to V

Tie to V

Tie to V

on the DIMM. The W132 takes in the signal from the mother­board and buffers out clock signals with enough drive to sup­port all the DIMM board clocking needs. The W132 is also
designed to meet the needs of new PC133 SDRAM designs,
operating to 133 MHz.

The W132 was spe cifically de signed to accep t SSFTG signal s
currently being used in motherboard designs to reduce EMI.
Zero delay b uffers which are not designed to pass this f e ature
through may cause skewing failures.

Output enable p ins allo w f or shutdown of output w hen they are
not being used. This reduces EMI and power consumption.

(HIGH, 1) for normal oper ation. when brought

DD

(HIGH, 1) for normal oper ation. when brought

DD

(HIGH, 1) for normal oper ation. when brought

DD

2

Figure 2. 6 Output Buffer in the Feedback Path

W132

1

AGND

2

3

4

5

6

7

8

9

10

11

12

VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE
FBOUT

VDD

VDD

0.1µ

0.1µ

F

F

Figure 1. Schematic

Spread Aware

Many systems bein g design ed no w utiliz e a tec hnology called
Spread Spectrum F requenc y Timing Ge neration. Cy press has
been one of the pioneers of SSFT G de v elop ment, an d we de­signed this product so as not to fil ter off the Spread Spectrum
feature of the R eference input, as suming it ex ists. When a zero
delay buffer is not desig ned to pass t he SS feature thro ugh,
the result is a significant amount of tracking skew which may
cause problems in systems requiring synchronization.

For more details on Spread Spectrum timing technology,
please see the Cypress application note titled, “EMI Suppres­sion Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.”

How to Implement Zero Delay

Typically, zero delay buffers (ZDBs) are used becau se a de­signer wants to provide multiple copies of a clock signal in
phase with each oth er. Th e whole concept b ehind ZDBs is th at
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this,
layo ut must compens ate for tr ace length be tween the ZDB and
the target devices. The method of compensation is described
below.

External feedbac k is the trait that a llows f or this compensa tion.
The PLL on the ZDB will cause the feedback signal to be in
phase with the reference s ignal. Whe n laying out the board,
match the trace lengths between the output being used for
feed back and the FBIN input to the PLL.

24

GND

23

AVDD

VDD

Q9

Q8
GND
GND

Q7

Q6

Q5

VDD

FBIN

22

21

20

19

18

17

16

15

14

13

0.1µ

0.1µ

F

10µ

F

0.1µ

F

F

VDD

FB

10µ

FB

3.3V

F

VDD

If it is desirable to either add a little delay, or slightly precede
the input signal, this may also be affecte d by either m aking the
trace to the FBIN pin a little shorter or a little longer than the
traces to the devices being clocked.

Inserting Other Devices in Feedback P ath

Another nice feature available due to the external feedback is
the ability to synch ronize signals up to the si gnal coming from
some other de vice . This impleme ntation can b e applied to an y
device (ASIC , mu ltiple output cl oc k b uff e r/driv er, etc.) which is
put into the feedback path.

Referring to Figure 2, if the traces between the ASIC/buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin, the signals
at the destinatio n(s) dev ice will be driv en high at the same time
the Reference clock provided to the ZDB goes high. Synchro­nizing the other outputs of the ZDB to the outputs form the
ASIC/Buffer is m ore comple x how e ver , as any prop agation de­lay in the ASIC/Buffer must be accounted for.

Reference

Signal

Feedback

Input

Zero
Delay
Buffer

ASIC/
Buffer

A

3

Absolute Maximum Ratings

W132

Stresses greate r than those list ed in this tab le m a y ca use p er­manent damage to the devi ce. Thes e represent a s tress ratin g
only. Operation of the d evice a t th es e o r a ny o t he r co nd i ti ons

.

above th os e sp ec ifi ed i n the ope rating sections of this s pe cif i­cation is not implied. Maximum conditions for extended peri­ods may aff ect reliability.

Parameter Description Rating Unit

V

, V

DD

IN

T

STG

T

A

T

B

P

D

DC Electrical Characteristics

Voltage on any pin with respect to GND –0.5 to +7.0 V
Storage Temperature –65 to +150 °C
Operating Temperature 0 to +70 °C
Ambient Temperature under Bias –55 to +125 °C
Power Dissipation 0.5 W

=0°C to 70°C, VDD = 3.3V ±10%

T

:

A

Parameter Description Test Condition Min Typ Max Unit

I

DD

V

IL

V

IH

V

OL

V

OH

I

IL

I

IH

Supply Current Unloaded, 100 MHz 200 mA
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 12 mA 0.8 V
Output High Voltage IOH = –12 mA 2.1 V
Input Low Current VIN = 0V 50 µA
Input High Current VIN = V

DD

50 µA

AC Electrical Characteristics:

TA = 0°C to +70°C, VDD = 3.3V ±10%

Parameter Description Test Condition Min Typ Max Unit

f

OUT

t

R

t

F

t

ICLKR

t

ICLKF

t

PEJ

t

SK

t

D

t

LOCK

t

JC

Notes:

1. Longer input rise and fall time will degrade skew and jitter performance.

2. Skew is measured at V

3. Duty cycle is measured at V

4. Production tests are run at 133 MHz.

Output Fre que nc y 30-pF load
Output Rise Time 0.8V to 2.0V, 30-pF load 2.1 ns
Output Fall Time 2.0V to 0.8V, 30-pF load 2.5 ns
Input Clock Rise Time
Input Clock Fall Time
CLK to FBIN Skew Variation

[1]

[1]

[2, 3]

Measured at VDD/2 –350 0 350 ps
Output to Output Skew All outputs loaded equally –100 0 100 ps
Duty Cycle 30-pF load 43 50 58 %
PLL Lock Time Power supply stable 1.0 ms
Jitter, Cycle-to-Cycle 150 ps

/2 on rising edges.

DD

/2.

DD

[4]

25 140 MHz

4.5 ns

4.5 ns

Ordering Informat ion

Ordering Code Option Package Type

W132 -09B, -10B X = 24-pin TSSOP

Document #: 38-00792

4

Package Diagram

W132

24-Pin Thin Shrink Small Outline Package (TSSOP)

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circui try embodied in a Cypre ss Semiconductor product. Nor d oes it conv ey or imply any license under patent or ot her rights. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.