Datasheet VNQ830 Datasheet (ST)

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Page 1

Features

Type R

VNQ830 65 mΩ

1. Per each channel.

DS(on)

(1)

OUT

6A 36V

VNQ830

Quad channel high-side driver

■ CMOS compatible inputs

■ Open Drain status outputs

■ On-state open-load detection

■ Off-state open-load detection

■ Shorted load protection

■ Undervoltage and overvoltage shutdown

■ Loss of ground protection

■ Very low standby current

■ Reverse battery protection

SO-28 (double island)

Description

The VNQ830 is a quad HSD formed by assembling two VND830 chips in the same SO-28 package. The VND830 is a monolithic device made using| STMicroelectronics™ VIPower™ M0-3 Technology. The device is intended for driving any type of multiple load with one side connected to ground.

The active V device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects the open load condition in both the on and off state.

In the off state the device detects if the output is shorted to V in the case where the ground pin becomes disconnected.

pin voltage clamp protects the

. The device automatically turns off

Table 1. Device summary

Order codes

Package

Tube Tape and reel

SO-28 (double island) VNQ830 VNQ83013TR

February 2011 Doc ID 7390 Rev 4 1/28

www.st.com

Page 2

Contents VNQ830

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 18

3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 18

3.1.2 Solution 2: a diode (D

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

) in the ground line . . . . . . . . . . . . . . . . . . . . 19

GND

3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.4 Open load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.5 Maximum demagnetization energy (V

= 13.5V) . . . . . . . . . . . . . . . . . . 21

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/28 Doc ID 7390 Rev 4

Page 3

VNQ830 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7. V Table 8. Switching (V

Table 9. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 11. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 13. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 14. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 15. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 16. Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 17. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 18. SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

- output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

= 13 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Doc ID 7390 Rev 4 3/28

Page 4

List of figures VNQ830

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 13. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 14. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 17. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 19. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 20. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 21. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 22. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 23. Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 25. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 26. Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 27. SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 28. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 23

Figure 29. Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 30. Thermal fitting model of a quad channel HSD in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 31. SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 32. SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 33. SO-28 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4/28 Doc ID 7390 Rev 4

Page 5

VNQ830 Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

CC1,2

CLAMP

OVERVOLTAGE

UNDERVOLTAGE

GND1,2

INPUT1

STAT US1

INPUT2

STAT US2

GND3,4

INPUT3

STAT US3

INPUT4

STAT US4

OVERTEMP. 1

OVERTEMP. 2

CLAMP

OVERTEMP. 3

OVERTEMP. 4

LOGIC

CLAMP 1

DRIVER 1

CURRENT LIMITER 1

OPENLOAD ON 1

OPENLOAD OFF 1

OVERVOLTAGE

UNDERVOLTAGE

CLAMP 3

DRIVER 3

CURRENT LIMITER 3

OPENLOAD ON 3

OPENLOAD OFF 3

CLAMP 2

DRIVER 2

CURRENT LIMITER 2

OPENLOAD ON 2

OPENLOAD OFF 2

CLAMP 4

DRIVER 4

CURRENT LIMITER 4

OPENLOAD ON 4

OPENLOAD OFF 4

OUTPUT1

OUTPUT2

CC3,4

OUTPUT3

OUTPUT4

Doc ID 7390 Rev 4 5/28

Page 6

Block diagram and pin description VNQ830

Figure 2. Configuration diagram (top view)

VCC1,2

GND 1,2

INPUT1

STATUS1

STATUS2

INPUT2

1,2

3,4

GND 3,4

INPUT3

STATUS3

STATUS4

INPUT4

3,4

1,2

OUTPUT1

OUTPUT2

OUTPUT3

OUTPUT4

3,4

Table 2. Suggested connections for unused and not connected pins

Connection / pin Status N.C. Output Input

Floating X X X X

To ground X

Through 10KΩ

resistor

6/28 Doc ID 7390 Rev 4

Page 7

VNQ830 Electrical specifications

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

-V

-I

GND

OUT

-I

OUT

STAT

ESD

MAX

DC supply voltage 41 V

Reverse DC supply voltage -0.3 V

DC reverse ground pin current -200 mA

DC output current Internally limited A

Reverse DC output current -6 A

DC input current +/- 10 mA

DC Status current +/- 10 mA

Electrostatic discharge (human body model: R=1.5KΩ; C = 100pF)

–INPUT –STATUS –OUTPUT –V

4000 4000 5000 5000

Maximum switching energy (L = 2.5 mH; R

=9A)

Power dissipation (per island) at T

tot

Junction operating temperature Internally limited °C

Storage temperature -55 to 150 °C

stg

= 0 Ω; V

= 13.5 V; T

bat

= 150 °C;

jstart

= 25 °C 6.25 W

lead

140 mJ

V V V V

Doc ID 7390 Rev 4 7/28

Page 8

Electrical specifications VNQ830

2.2 Thermal data

Table 4. Thermal data (per island)

Symbol Parameter Value Unit

thj-lead

thj-amb

Thermal resistance junction-lead 20 °C/W

Thermal resistance junction-ambient (one chip ON)

Thermal resistance junction-ambient (two chips ON)

1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35 µm thick) connected to all V

2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35 µm thick) connected to all V

pins. Horizontal mounting and no artificial air flow.

2.3 Electrical characteristics

Values specified in this section are for 8V < V otherwise stated.

Figure 3. Current and voltage conventions

S3,4

CC3,4

IN1

STAT3

STAT1

IN2

STAT2

IN3

STAT3

IN4

STAT4

IN4

STAT4

IN1

STAT1

IN2

STAT2

IN3

INPUT1

STATUS1

INPUT2

STATUS2

INPUT3

STATUS3

INPUT4

STATUS4

GND

(1)

< 36V; -40 °C < Tj < 150 °C, unless

S1,2

CC3,4

3,4

GND3,4

CC1,2

OUTPUT1

OUTPUT2

OUTPUT3

OUTPUT4

GND

(*)

OUT1

OUT2

OUT3

OUT4

1,2

GND1,2

OUT2

(2)

OUT1

°C/W

CC1,2

Note: V

= V

CCn

- V

during reverse battery condition.

OUTn

8/28 Doc ID 7390 Rev 4

Page 9

VNQ830 Electrical specifications

Table 5. P owe r

Symbol Parameter Test conditions Min. Typ. Max. Unit

L(off1)

L(off2)

L(off3)

L(off4)

Table 6. Protections

Operating supply

voltage

Undervoltage shutdown 3 4 5.5 V

USD

Overvoltage shutdown 36 V

On-state resistance

Supply current

Off-state output current V

Off-state output current

5.5 13 36 V

= 2 A; Tj = 25 °C 65 mΩ

OUT

= 2 A; V

OUT

Off-state; V V

= V

OUT

Off-state; V

= V

OUT

On-state; V I

= 0 A

OUT

= V

OUT

= 0 V; V

= V

OUT

> 8 V 130 mΩ

= 13 V;

= 0 V

= 13 V;

= 0 V; Tj = 25 °C

= 13 V; V

= 5 V;

12 40 µA

12 25 µA

57mA

= 0 V 0 50 µA

= 3.5 V -75 0 µA

OUT

= 0 V; V

= 13 V;

Tj=125°C

= V

=25°C

OUT

= 0 V; V

= 13 V;

5µA

3µA

Symbol Parameter Test conditions Min. Typ. Max. Unit

SDL

demag

Shutdown temperature 150 175 200 °C

TSD

Reset temperature 135 °C

Thermal hysteresis 7 15 °C

hyst

Status delay in overload conditions

Current limitation

lim

Turn-off output clamp voltage I

> T

TSD

= 13 V 6 9 15 A

5.5 V < V

OUT

< 36 V 15 A

-41V

= 2A; L = 6mH

-48V

20 µs

Note: To ensure long term reliability under heavy overload or short circuit conditions, protection

and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.

Table 7. VCC - output diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

Forward on voltage -I

= 1.2 A; Tj = 150 °C — — 0.6 V

OUT

Doc ID 7390 Rev 4 9/28

Page 10

Electrical specifications VNQ830

Table 8. Switching (V

Symbol Parameter Test conditions Min. Typ. Max. Unit

d(on)

d(off)

Turn-on delay time

Turn-off delay time

= 13 V; Tj = 25 °C)

RL = 6.5 Ω from VIN rising edge to V (see Figure 5)

RL = 6.5 Ω from VIN falling edge to V (see Figure 5)

OUT

= 1.3 V

= 11.7 V

—30 —µs

/dt

OUT

Table 9. Logic inputs

Turn-on voltage slope

(on)

/dt

Turn-off voltage slope

(off)

RL = 6.5 Ω from V to V

OUT

= 10.4 V

(see Figure 5)

RL = 6.5 Ω from V to V

OUT

= 1.3 V

(see Figure 5)

OUT

= 1.3 V

= 11.7 V

—

See

Figure 10

See

Figure 12

—V/µs

Symbol Parameter Test conditions Min. Typ. Max. Unit

I(hyst)

Table 10. Status pin

Input low level 1.25 V

Low level input current V

Input high level 3.25 V

High level input current V

= 1.25 V 1 µA

= 3.25 V 10 µA

Input hysteresis voltage 0.5 V

= 1 mA 6 6.8 8 V

Input clamp voltage

ICL

= -1 mA -0.7 V

Symbol Parameter Test conditions Min. Typ. Max. Unit

LSTAT

Table 11. Open-load detection

Status low output voltage I

STAT

Status leakage current Normal operation; V

Status pin Input capacitance Normal operation; V

STAT

Status clamp voltage

SCL

= 1.6 mA 0.5 V

STAT

=5V 10 µA

STAT

= 5 V 100 pF

STAT

= 1 mA 6 6.8 8 V

STAT

= - 1 mA -0.7 V

STAT

Symbol Parameter Test conditions Min. Typ. Max. Unit

DOL(on)

DOL(off)

Open-load on-state detection threshold V

Open-load on-state detection delay I

Open-load off-state voltage detection

threshold

Open-load detection delay at turn-off 1000 µs

10/28 Doc ID 7390 Rev 4

= 5 V 50 100 200 mA

= 0 A 200 µs

OUT

= 0 V 1.5 2.5 3.5 V

Page 11

VNQ830 Electrical specifications

Figure 4. Status timings

OPEN LOAD STATUS TIMING (with external pull-up)

> V

OUT

INn

STATn

DOL(off)

OUT

DOL(on)

Figure 5. Switching characteristics

OUTn

80%

/dt

OUT

(on)

< I

OVER TEMP STATUS TIMING

INn

STATn

SDL

Tj > T

TSD

SDL

90%

/dt

OUT

(off)

10%

INn

d(on)

d(off)

Doc ID 7390 Rev 4 11/28

Page 12

Electrical specifications VNQ830

Table 12. Truth table

Conditions Input Output Status

Normal operation

Current limitation

Overtemperature

Undervoltage

Overvoltage

Output voltage > V

Output current < I

L H H

L H

L X X

H H

L H

< T

> T

H H

X X

H H

TSD

) H ) L

12/28 Doc ID 7390 Rev 4

Page 13

VNQ830 Electrical specifications

Table 13. Electrical transient requirements (part 1)

ISO T/R

Test level

7637/1

Test pulse

I II III IV Delays and impedance

1 - 25V - 50V - 75V - 100V 2ms, 10Ω

2 + 25V + 50V + 75V + 100V 0.2ms, 10Ω

3a - 25V - 50V - 100V - 150V 0.1µs, 50Ω

3b + 25V + 50V + 75V + 100V 0.1µs, 50Ω

4 - 4V - 5V - 6V - 7V 100ms, 0.01Ω

5 + 26.5V + 46.5V + 66.5V + 86.5V 400ms, 2Ω

Table 14. Electrical transient requirements (part 2)

ISO T/R

Test level

7637/1

Test pulse

IIIIIIIV

1C C C C

2C C C C

3a C C C C

3b C C C C

4C C C C

5C E E E

Table 15. Electrical transient requirements (part 3)

Class Contents

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.

Doc ID 7390 Rev 4 13/28

Page 14

Electrical specifications VNQ830

Figure 6. Waveforms

NORMAL OPERATION

INPUT

LOAD VOLTAGE

STATUS

INPUT

LOAD VOLTAGE

STATUS

INPUT

LOAD VOLTAGE STATUS

USD

VCC<V

UNDERVOLTAGE

OVERVOLTAGE

USDhyst

undefined

> V

INPUT

LOAD VOLTAGE

STATUS

INPUT

LOAD VOLTAGE

STATUS

INPUT

LOAD CURRENT

STATUS

OPEN LOAD with external pull-up

> V

OUT

OPEN LOAD without external pull-up

TSD

OVERTEMPERATURE

14/28 Doc ID 7390 Rev 4

Page 15

VNQ830 Electrical specifications

2.4 Electrical characteristics curves

Figure 7. Off-state output current Figure 8. High level input current

IL(off1) (uA)

2.5

2.25

1.75

1.5

1.25

0.75

0.5

0.25

-50 -25 0 25 50 75 100 125 150 175

Off state Vcc=36V

Vin=Vout=0V

Tc (°C)

Iih (uA)

4.5

3.5

2.5

1.5

0.5

Vin=3.25V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 9. Input clamp voltage Figure 10. Turn-on voltage slope

Vicl (V)

7.8

7.6

7.4

7.2

6.8

6.6

6.4

6.2

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

dVout/dt(on) (V/ms)

800

700

600

500

400

300

200

100

Vcc=13V

Rl=6.5Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Figure 11. Overvoltage shutdown Figure 12. Turn-off voltage slope

Vov (V)

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

dVout/dt(off) (V/ms)

600

550

500

450

400

350

300

250

200

Vcc=13V

Rl=6.5Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Doc ID 7390 Rev 4 15/28

Page 16

Electrical specifications VNQ830

Figure 13. I

Ilim (A)

-50 -25 0 25 50 75 100 125 150 175

vs T

LIM

Vcc=13V

case

Tc (°C)

Figure 14. On-state resistance vs V

Ron (mOhm)

120

110

100

5 10152025303540

Tc=150°C

Tc=25°C

Tc= - 40°C

Iout=2A

Vcc (V)

Figure 15. Input high level Figure 16. Input hysteresis voltage

Vih (V)

3.6

3.4

3.2

2.8

2.6

2.4

2.2

-50 -25 0 25 50 75 10 0 125 150 175

Tc (°C)

Vhyst (V)

1.5

1.4

1.3

1.2

1.1

0.9

0.8

0.7

0.6

0.5

-50 -25 0 25 50 75 10 0 125 150 175

Tc (°C)

Figure 17. On-state resistance vs Tcase Figure 18. Input low level

Ron (mOhm)

160

140

120

100

-50 -25 0 25 50 75 100 125 150 175

Iout=2A

Vcc=8V; 13V & 36V

Tc (°C)

16/28 Doc ID 7390 Rev 4

Vil (V)

2.6

2.4

2.2

1.8

1.6

1.4

1.2

-50 -25 0 25 50 75 10 0 125 150 175

Tc (°C)

Page 17

VNQ830 Electrical specifications

Figure 19. Status leakage current Figure 20. Status low output voltage

Ilstat (uA)

0.05

0.04

Vstat=5V

0.03

0.02

0.01

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vstat (V)

0.8

0.7

Istat=1.6mA

0.6

0.5

0.4

0.3

0.2

0.1

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 21. Status clamp voltage Figure 22. Open-load on-state detection

threshold

Vscl (V)

7.8

7.6

7.4

7.2

6.8

6.6

6.4

6.2

Istat=1mA

-50 -25 0 25 50 75 10 0 125 150 175

Tc (°C)

Figure 23. Open-load off-state voltage

Iol (mA)

150

140

130

120

110

100

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

Vin=5V

Tc (°C)

detection threshold

Vol (V)

4.5

3.5

2.5

1.5

0.5

Vin=0V

-50 -25 0 25 50 75 10 0 125 150 175

Tc (°C)

Doc ID 7390 Rev 4 17/28

Page 18

Application information VNQ830

3 Application information

Figure 24. Application schematic

+5V

prot

STATUS1

INPUT1

STATUS2

INPUT2

CC1,2

CC3,4

OUTPUT1

GND3,4

OUTPUT2

OUTPUT3

OUTPUT4

GND

prot

+5V

STATUS3

INPUT3

STATUS4

INPUT4

GND1,2

GND

Note: Channels 3 and 4 have the same internal circuit as channel 1 and 2.

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against reverse battery.

3.1.1 Solution 1: a resistor in the ground line (R

This can be used with any type of load.

The following show how to dimension the R

1. R

2. R

18/28 Doc ID 7390 Rev 4

≤ 600 mV / 2(I

GND

≥(-VCC) / (-I

GND

S(on)max

GND

)

GND

resistor:

GND

only)

Page 19

VNQ830 Application information

where -I

is the DC reverse ground pin current and can be found in the absolute

GND

maximum rating section of the device datasheet.

Power dissipation in R

= (-VCC)2/ R

GND

This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I maximum on-state currents of the different devices.

Please note that, if the microprocessor ground is not shared by the device ground, then the R

will produce a shift (I

GND

values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R

If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below.

3.1.2 Solution 2: a diode (D

A resistor (R an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (≈600 mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.

= 1 kΩ) should be inserted in parallel to D

GND

(when V

S(on)max

GND

< 0 during reverse battery situations) is:

* R

GND

) in the ground line

S(on)max

becomes the sum of the

) in the input thresholds and the status output

if the device will be driving

GND

3.2 Load dump protection

Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the V

maximum DC rating. The same applies if the device is subject to transients on the VCC

line that are greater than those shown in the ISO T/R 7637/1 table.

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (R prevent the microcontroller I/O pins from latching up.

The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit microcontroller I/Os:

-V

CCpeak

/ I

latchup

≤ R

prot

≤ (V

OHμC

- V

GND

) / I

IHmax

) in line to

prot

Doc ID 7390 Rev 4 19/28

Page 20

Application information VNQ830

Example

For the following conditions:

CCpeak

latchup

OHμC

5kΩ ≤ R

= -100 V

≥ 20 mA

≥ 4.5 V

≤ 65 kΩ.

prot

Recommended values are:

= 10 kΩ

prot

3.4 Open load detection in off-state

Off-state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (V microprocessor.

The external resistor has to be selected according to the following requirements:

1. No false open load indication when load is connected: in this case we have to avoid V

to be higher than V

OUT

= (V

OUT

/ (RL + RPU))RL < V

; this results in the following condition

Olmin

Olmin.

2. No misdetection when load is disconnected: in this case the V V

Because I up resistor R

; this results in the following condition R

OLmax

may significantly increase if V

s(OFF)

should be connected to a supply that is switched OFF when the module is in

standby.

) like the +5V line used to supply the

has to be higher than

< (V

is pulled high (up to several mA), the pull-

out

- V

OUT

OLmax

) / I

L(off2)

Figure 25. Open-load detection in off-state

INPUT

STATUS

DRIVER

LOGIC

GROUND

V batt. VPU

L(off2)

OUT

20/28 Doc ID 7390 Rev 4

Page 21

VNQ830 Application information

3.5 Maximum demagnetization energy (V

Figure 26. Maximum turn-off current versus load inductance

LMAX (A)

100

= 13.5V)

0.1 1 10 100

A = single pulse at T

B= repetitive pulse at T

C= repetitive pulse at T

VIN, I

Note: Values are generated with R

In case of repetitive pulses, T must not exceed the temperature specified above for curves B and C.

= 150 °C

Jstart

Demagnetization

L(mH)

= 100 °C

= 125 °C

Demagnetization

= 0 Ω.

(at beginning of each demagnetization) of every pulse

jstart

Demagnetization

Doc ID 7390 Rev 4 21/28

Page 22

Package and PCB thermal data VNQ830

4 Package and PCB thermal data

4.1 SO-28 thermal data

Figure 27. SO-28 PC board

Note: Layout condition of R

thickness = 2mm, Cu thickness = 35µm, Copper areas: 0.5 cm

Table 16. Thermal calculation according to the PCB heatsink area

Chip 1 Chip 2 T

ON OFF R

OFF ON R

ON ON

= thermal resistance junction to ambient with one chip ON

thA

= thermal resistance junction to ambient with both chips ON and P

thB

= mutual thermal resistance

thC

thA

thC

thB

amb

(R P

dchip2

thA

and Zth measurements (PCB FR4 area = 58mm x 58mm, PCB

x P

x (P

x P

+ T

dchip1

dchip2

dchip1

amb

jchip1

+ T

+ P

) + R

amb

dchip2

thC

) +

thC

thA

thB

amb

(R P

dchip1

thA

x P

x (P

x P

dchip1

dchip2

dchip1

dchip2

+ T

amb

, 3 cm2, 6 cm2).

jchip2

+ T

amb

+ T

amb

+ P

dchip2

) + R

thC

) +

dchip1

= P

Note

dchip2

= P

≠ P

dchip2

22/28 Doc ID 7390 Rev 4

Page 23

VNQ830 Package and PCB thermal data

Figure 28. R

RTHj _a m b

(°C/W)

012345 67

vs PCB copper area in open box free air condition

thj-amb

PCB Cu heatsink are a (cm ^2)/island

thA

thB

thC

Figure 29. Thermal impedance junction ambient single pulse

ZT H (°C /W)

1000

100

0.1

0.0001 0.001 0.01 0.1 1 10 100 1000

Time (s)

Footprint

6 cm

Doc ID 7390 Rev 4 23/28

Page 24

Package and PCB thermal data VNQ830

Equation 1: pulse calculation formula

where

THδ

RTHδ Z

δ tpT⁄=

THtp

1 δ–()+⋅=

Figure 30. Thermal fitting model of a quad channel HSD in SO-28

Tj_1

Pd1

Tj_2

Pd2

Tj_3

Pd3

Tj_4

Pd4

C13 C14

R13

C15 C16

R15

R14

R16

C3 C4

R3R1 R6R5R2

R17

R9R7

R18

C10

R10

C5 C6C2

C11 C12

R12R11

Table 17. Thermal parameters

Area / island (cm2) Footprint 6

R1 = R7 = R13 = R15 (°C/W) 0.15

R2 = R8 = R14 = R16 (°C/W) 0.7

R3 = R9 (°C/W) 1.8

R4 = R10 (°C/W) 10

R5 = R11 (°C/W) 15

R6 = R12 (°C/W) 30 13

C1 = C7 = C13 = C15 (W.s/°C) 0.0005

C2 = C8 = C14 = C16 (W.s/°C) 3E-03

C3 = C9 (W.s/°C) 1.50E-02

C4 = C10 (W.s/°C) 0.15

C5 = C11 (W.s/°C) 1.5

C6 = C12 (W.s/°C) 5 8

R17 = R18 (°C/W) 150

T_amb

24/28 Doc ID 7390 Rev 4

Page 25

VNQ830 Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

is an ST trademark.

Figure 31. SO-28 package dimensions

Table 18. SO-28 mechanical data

Millimeters

Symbol

Min. Typ. Max.

A 2.65

a1 0.10 0.30

b 0.35 0.49

b1 0.23 0.32

C0.50

c1 45° (typ.)

D 17.7 18.1

E 10.00 10.65

e1.27

e3 16.51

F 7.40 7.60

L 0.40 1.27

S 8° (max.)

Doc ID 7390 Rev 4 25/28

Page 26

Package and packing information VNQ830

5.2 SO-28 packing information

Figure 32. SO-28 tube shipment (no suffix)

Base Q.ty 28 Bulk Q.ty 700 Tube length (± 0.5) 532 A 3.5

Figure 33. SO-28 tape and reel shipment (suffix “TR”)

B 13.8 C (± 0.1) 0.6

All dimensions are in mm.

Reel dimensions

Tape dimensions

According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986

Tape width W 16 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 12 Hole Diameter D (± 0.1/-0) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.05) 7.5 Compartment Depth K (max) 6.5 Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm min

Base Q.ty 1000 Bulk Q.ty 1000 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 16.4 N (min) 60 T (max) 22.4

Empty components pock ets saled with cover tape.

User direction of feed

Start

No componentsNo components Components

500mm min

26/28 Doc ID 7390 Rev 4

Page 27

VNQ830 Revision history

6 Revision history

Table 19. Document revision history

Date Revision Changes

21-Jun-2004 1 Initial release.

Emax value (page 1). Current and voltage convention update (page 3). Configuration diagram (top view) & suggested connections for unused

and n.c. pins insertion (page 3). 6 cm2 Cu condition insertion in Thermal Data table (page 4).

- output diode section update (page 5).

Protections note insertion (page 5).

03-May-2006 2

On-state resistance Vs V Turn-off voltage slope curve conditions correction (page 14). "Maximum turn-off current versus load inductance" curve modification

(page 15). "SO-28 thermal impedance junction ambient single pulse”: curve

modification (page 17). Revision history table insertion (page 20). Disclaimers update (page 21).

curve conditions correction (page 13).

Document reformatted and restructured.

25-Nov-2008 3

Added contents, list of tables and figures.

Added ECOPACK

packages information.

07-Feb-2011 4 Updated Figure 5: Switching characteristics

Doc ID 7390 Rev 4 27/28

Page 28

VNQ830

Please Read Carefully:

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28/28 Doc ID 7390 Rev 4