Datasheet VNQ810P-E Datasheet (ST)

Features

Type R

VNQ810P-E 160mΩ

1. Per each channel.

DS(on)

(1)

I

OUT

3.5A

(1)

V

CC

36V

VNQ810P-E

Quad channel high-side driver

■ ECOPACK

■ Automotive Grade: compliance with AEC

®

: lead free and RoHS compliant

guidelines

■ Very low standby current

■ CMOS compatible input

■ On-state open-load detection

■ Off-state open-load detection

■ Thermal shutdown protection and diagnosis

■ Undervoltage shutdown

■ Overvoltage clamp

■ Output stuck to V

■ Load current limitation

■ Reverse battery protection

■ Electrostatic discharge protection

detection

CC

SO-28 (double island)

Description

The VNQ810P-E is a quad HSD formed by
assembling two VND810P-E chips in the same
SO-28 package. The VNQ810P-E is a monolithic
device made by using STMicroelectronics
VIPower™ M0-3 technology, intended for driving
any kind of load with one side connected to
ground. Active V
device against low energy spikes (see ISO7637
transient compatibility table).

Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload. The device detects
open-load condition both in on and off-state.
Output shorted to V
Device automatically turns off in case of ground
pin disconnection.

pin voltage clamp protects the

CC

is detected in the off-state.

CC

Table 1. Device summary

Order codes

Package

Tube Tape and reel

SO-28 (double island) VNQ810P-E VNQ810PTR-E

April 2010 Doc ID 17387 Rev 1 1/28

www.st.com

1

Contents VNQ810P-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17

3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 17

3.1.2 Solution 2: a diode (D

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

) in the ground line . . . . . . . . . . . . . . . . . . . . 18

GND

3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5 Maximum demagnetization energy (V

= 13.5V) . . . . . . . . . . . . . . . . . . 20

CC

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2 SO-28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/28 Doc ID 17387 Rev 1

VNQ810P-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7. V

Table 8. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 9. Switching (V

Table 6. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 10. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 11. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 13. Electrical transient requirements on V
Table 14. Electrical transient requirements on V
Table 15. Electrical transient requirements on V

Table 16. Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 17. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 18. SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

- output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

= 13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

pin (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CC

pin (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CC

pin (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CC

Doc ID 17387 Rev 1 3/28

List of figures VNQ810P-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Switching time Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 11. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 14. I

Figure 15. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 16. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 17. On-state resistance vs T
Figure 18. On-state resistance vs V

Figure 19. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 20. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 21. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 22. Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 23. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 25. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 26. SO-28 (double island) maximum turn-off current versus load inductance . . . . . . . . . . . . . 20

Figure 27. SO-28 double island PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 28. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 22

Figure 29. SO-28 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 30. Thermal fitting model of a quad channel HSD in SO-28. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 31. SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 32. SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 33. SO-28 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

LIM

vs T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CC

4/28 Doc ID 17387 Rev 1

VNQ810P-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

CC1,2

V

cc

CLAMP

OVERVOLTAGE

UNDERVOLTAGE

GND1,2

INPUT1

STAT US1

INPUT2

STAT US2

GND3,4

INPUT3

STAT US3

INPUT4

STAT US4

OVERTEMP. 1

OVERTEMP. 2

V

cc

CLAMP

OVERTEMP. 3

OVERTEMP. 4

LOGIC

LOGIC

CLAMP 1

DRIVER 1

CURRENT LIMITER 1

OPENLOAD ON 1

OPENLOAD OFF 1

OVERVOLTAGE

UNDERVOLTAGE

CLAMP 3

DRIVER 3

CURRENT LIMITER 3

OPENLOAD ON 3

OPENLOAD OFF 3

CLAMP 2

DRIVER 2

CURRENT LIMITER 2

OPENLOAD ON 2

OPENLOAD OFF 2

CLAMP 4

DRIVER 4

CURRENT LIMITER 4

OPENLOAD ON 4

OPENLOAD OFF 4

OUTPUT1

OUTPUT2

V

CC3,4

OUTPUT3

OUTPUT4

Doc ID 17387 Rev 1 5/28

Block diagram and pin description VNQ810P-E

Figure 2. Configuration diagram (top view)

VCC1,2

1

GND 1,2

INPUT1

STATUS1

STATUS2

INPUT2

1,2

V

CC

3,4

V

CC

GND 3,4

INPUT3

STATUS3

STATUS4

INPUT4

V

3,4

CC

Table 2. Suggested connections for unused and not connected pins

14

28

15

V

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT3

OUTPUT3

OUTPUT3

OUTPUT4

OUTPUT4

OUTPUT4

V

CC

CC

1,2

3,4

Connection / pin Status N.C. Output Input

Floating X X X X

To ground X

Through 10 KΩ

resistor

6/28 Doc ID 17387 Rev 1

VNQ810P-E Electrical specifications

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the Ta bl e 5 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics SURE program and other relevant quality
document.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

-V

-I

I

OUT

-I

I

STAT

V

E

P

T

CC

CC

GND

OUT

I

IN

ESD

MAX

tot

T

j

stg

DC supply voltage 41 V

Reverse DC supply voltage -0.3 V

DC reverse ground pin current -200 mΑ

DC output current Internally limited A

Reverse DC output current -6 A

DC input current +/-10 mA

DC Status current +/-10 mA

Electrostatic discharge (human body model: R = 1.5 KΩ;
C=100pF)

- INPUT

- STATUS

- OUTPUT

- V

CC

Maximum switching energy
(L = 2.5 mH; R

= 0 Ω; V

L

= 13.5 V; T

bat

Power dissipation (per island) at T

= 150 °C; IL = 9 A)

jstart

= 25°C 6.25 W

lead

4000
4000
5000
5000

23 mJ

V
V
V
V

Junction operating temperature Internally limited °C

Storage temperature - 55 to 150 °C

2.2 Thermal data

Table 4. Thermal data (per island)

Symbol Parameter Value Unit

R

thj-lead

R

thj-amb

R

thj-amb

1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected
to all V

2. When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35 µm thick) connected to
all V

Thermal resistance junction-lead 20 °C/W

Thermal resistance junction-ambient (one chip ON) 60

Thermal resistance junction-ambient (two chips ON) 46

pins. Horizontal mounting and no artificial air flow.

CC

pins. Horizontal mounting and no artificial air flow.

CC

(1)

(1)

44

31

(2)

(2)

°C/W

°C/W

Doc ID 17387 Rev 1 7/28

Electrical specifications VNQ810P-E

2.3 Electrical characteristics

Values specified in this section are for 8 V < V

CC

otherwise stated.

Figure 3. Current and voltage conventions

I

S3,4

V

INPUT1

STATUS1

INPUT2

STATUS2

INPUT3

STATUS3

INPUT4

STATUS4

GND

CC3,4

3,4

V

CC3,4

V

IN1

V

STAT1

V

IN2

V

STAT2

V

IN3

V

STAT3

V

1. VFn = V

Table 5. Power output

CCn

- V

during reverse battery condition.

OUTn

I

IN1

I

STAT1

I

IN2

I

STAT2

I

IN3

I

STAT3

I

IN4

I

STAT4

IN4

V

STAT4

< 36 V; -40 °C < Tj < 150 °C, unless

I

S1,2

I

GND3,4

V

CC1,2

OUTPUT1

OUTPUT2

OUTPUT3

OUTPUT4

GND

1,2

I

GND1,2

I

OUT1

I

OUT2

I

OUT3

I

OUT4

V

OUT4

V

V

OUT3

(1)

F1

V

OUT1

V

OUT2

V

CC1,2

Symbol Parameter Test conditions Min. Typ. Max. Unit

(1)

V

CC

V

USD

V

OV

R

I

L(off1)

I

L(off2)

I

L(off3)

I

L(off4)

1. Per island.

Operating supply voltage 5.5 13 36 V

(1)

Undervoltage shutdown 3 4 5.5 V

(1)

Overvoltage shutdown 36 V

= 1 A; Tj = 25 °C

I

On-state resistance

ON

Supply current

I

S

Off-state output current V

Off-state output current V

Off-state output current

Off-state output current

OUT

= 1 A; V

I

OUT

Off-state; V
V

= V

IN

OUT

Off-state; V

= V

V

IN

OUT

On-state; V

=0A

I

OUT

= V

IN

OUT

= 0V; V

IN

V

= V

IN

OUT

Tj=125°C

= V

V

IN

OUT

=25°C

T

j

> 8 V

CC

= 13 V;

CC

= 0 V

= 13 V;

CC

= 0 V; Tj = 25 °C

= 13 V; V

CC

IN

= 5 V;

12 40 µA

12 25 µA

= 0 V 0 50 µA

= 3.5 V -75 0 µA

OUT

= 0V; V

= 0V; V

CC

CC

= 13 V;

= 13 V;

160
320mΩmΩ

57mA

5µA

3µA

8/28 Doc ID 17387 Rev 1

VNQ810P-E Electrical specifications

Table 6. Protections

(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

T

T

t

V

demag

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related

Tabl e 7. VCC - output diode

Shutdown temperature 150 175 200 °C

TSD

T

Reset temperature 135 °C

R

Thermal hysteresis 7 15 °C

hyst

Status delay in overload

SDL

conditions

Current limitation

I

lim

Turn-off output clamp voltage I

diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

> T

T

j

TSD

V

= 13 V 3.5 5 7.5 A

CC

5.5 V < V

= 1A; L = 6mH VCC-41 VCC-48 VCC-55 V

OUT

< 36 V 7.5 A

CC

20 µs

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

Table 8. Status pin

Forward on voltage -I

F

= 0.5 A; Tj = 150 °C - - 0.6 V

OUT

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

LSTAT

C

V

Table 9. Switching (V

Status low output voltage I

STAT

STAT

Status leakage current Normal operation; V

Status pin Input capacitance Normal operation; V

STAT

I

Status clamp voltage

SCL

CC

= 13V)

STAT

I

STAT

= 1.6mA 0.5 V

= 5 V 10 µA

STAT

= 5 V 100 pF

STAT

= 1 mA 6 6.8 8 V

= - 1 mA -0.7 V

Symbol Parameter Test conditions Min. Typ. Max. Unit

= 13 Ω from VIN rising edge

R

t

d(on)

t

d(off)

dV

/dt

OUT

dV

/dt

OUT

Turn-on delay time

Turn-off delay time

Turn-on voltage slope

(on)

Turn-off voltage slope

(off)

L

to V

R
edge to V

R
to V

R
to V

= 1.3 V

OUT

= 13 Ω from VIN falling

L

= 13 Ω from V

L

OUT

= 13 Ω from V

L

OUT

= 11.7 V

OUT

= 10.4 V

= 1.3 V

OUT

OUT

= 1.3 V

= 11.7 V

-30 -µs

-30 -µs

See

-

-

Figure 10

See

Figure 12

-V/µs

-V/µs

Doc ID 17387 Rev 1 9/28

Electrical specifications VNQ810P-E

Table 10. Open-load detection

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

t

DOL(on)

V

t

DOL(off)

Table 11. Logic inputs

Open-load on-state detection threshold V

OL

Open-load on-state detection delay I

Open-load off-state voltage detection

OL

threshold

= 5 V 20 40 80 mA

IN

= 0 A 200 µs

OUT

= 0 V 1.5 2.5 3.5 V

V

IN

Open-load detection delay at turn-off 1000 µs

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

I

V

I

I(hyst)

Input low level 1.25 V

IL

Low level input current V

IL

Input high level 3.25 V

IH

High level input current V

IH

= 1.25 V 1 µA

IN

= 3.25 V 10 µA

IN

Input hysteresis voltage 0.5 V

I

= 1 mA 6 6.8 8 V

Input clamp voltage

ICL

IN

= -1 mA - 0.7 V

I

IN

Figure 4. Status timings

OPEN LOAD STATUS TIMING (with external pull-up)

V

> V

OUT

V

INn

I

< I

OUT

OL

OL

OVER TEMP STATUS TIMING

V

INn

Tj > T

TSD

V

STATn

t

DOL(off)

t

DOL(on)

10/28 Doc ID 17387 Rev 1

V

STATn

t

SDL

t

SDL

VNQ810P-E Electrical specifications

Figure 5. Switching time Waveforms

Table 12. Truth table

Conditions Input Output Sense

Normal operation

Current limitation

Overtemperature

Undervoltage

Overvoltage

Output voltage > V

Output current < I

OL

OL

L

H

L
H
H

L
H

L
H

L
H

L
H

L
H

L
H

L
X
X

L
L

L
L

L
L

H
H

L
H

(T

(T

< T

j

> T

j

H
H

H

TSD

TSD

H

L

X
X

H
H

L

H

H

L

) H

) L

Doc ID 17387 Rev 1 11/28

Electrical specifications VNQ810P-E

Table 13. Electrical transient requirements on VCC pin (part 1/3)

ISO T/R

Test levels

7637/1

Test pulse

I II III IV Delays and impedance

1 - 25V - 50V - 75V - 100V 2ms, 10Ω

2 + 25V + 50V + 75V + 100V 0.2ms, 10Ω

3a - 25V - 50V - 100V - 150V 0.1µs, 50Ω

3b + 25V + 50V + 75V + 100V 0.1µs, 50Ω

4 - 4V - 5V - 6V - 7V 100ms, 0.01Ω

5 + 26.5V + 46.5V + 66.5V + 86.5V 400ms, 2Ω

Table 14. Electrical transient requirements on VCC pin (part 2/3)

ISO T/R

Test levels results

7637/1

Test pulse

IIIIIIIV

1C C C C

2C C C C

3a C C C C

3b C C C C

4C C C C

5C E E E

Table 15. Electrical transient requirements on VCC pin (part 3/3)

Class Contents

C

E

All functions of the device are performed as designed after exposure to
disturbance.

One or more functions of the device is not performed as designed after exposure
and cannot be returned to proper operation without replacing the device.

12/28 Doc ID 17387 Rev 1

VNQ810P-E Electrical specifications

Figure 6. Waveforms

Normal operation

INPUT

n

OUTPUT VOLTAGE

STATUS

V

INPUT

n

CC

n

OUTPUT VOLTAGE

STATUS

V

INPUT

n

CC

n

OUTPUT VOLTAGE

STATUS

n

n

n

n

V

USD

VCC<V

OV

Undervoltage

V

USDhyst

undefined

Overvoltage

V

> V

CC

OV

INPUT

n

OUTPUT VOLTAGE

STATUS

INPUT

n

n

OUTPUT VOLTAGE

STATUS

T

INPUT

n

j

n

OUTPUT VOLTAGE

STATUS

n

Open-load with external pull-up

V

> V

n

V

OL

OUT

OL

Open-load without external pull-up

n

T

TSD

T

R

n

Overtemperature

Doc ID 17387 Rev 1 13/28

Electrical specifications VNQ810P-E

2.4 Electrical characteristics curves

Figure 7. Off-state output current Figure 8. High level input current

IL(off1) (uA)

1.44

1.28

1.12

0.96

0.64

0.48

0.32

0.16

Figure 9. Input clamp voltage Figure 10. Status leakage current

1.6

Off state
Vcc=36V

Vin=Vout=0V

0.8

0

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Vicl (V)

8

7.8

7.6

7.4

7.2

7

6.8

6.6

6.4

6.2

6

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Iih (uA)

5

4.5

3.5

2.5

1.5

0.5

Vin=3.25V

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Ilstat (uA)

0.05

0.04

Vstat=5V

0.03

0.02

0.01

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 11. Status low output voltage Figure 12. Status clamp voltage

Vstat (V)

0.8

0.7

Istat=1.6mA

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vscl (V)

8

7.8

7.6

7.4

7.2

6.8

6.6

6.4

6.2

Istat=1mA

7

6

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

14/28 Doc ID 17387 Rev 1

VNQ810P-E Electrical specifications

Figure 13. Overvoltage shutdown Figure 14. I

Vov (V)

50

48

46

44

42

40

38

36

34

32

30

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 15. Turn-on voltage slope Figure 16. Turn-off voltage slope

dVout/dt(on) (V/ms)

1000

900

800

700

600

500

400

300

200

100

Vcc=13V

Rl=13Ohm

0

-50 -25 0 25 50 75 100 125 150 175

Ilim (A)

10

9

8

7

6

5

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

dVout/dt(off) (V/ms)

500

450

400

350

300

250

200

150

100

50

0

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Figure 17. On-state resistance vs T

case

Figure 18. On-state resistance vs V

vs T

LIM

Vcc=13V

Rl=13Ohm

case

Tc (°C)

Tc (°C)

CC

Ron (mOhm)

400

350

300

250

200

150

100

50

0

-50 -25 0 25 50 75 100 125 150 175

Iout=0.5A

Vcc=8V; 13V & 36V

Tc (°C)

Ron (mOhm)

300

275

250

225

200

175

150

125

100

75

50

5 10152025303540

Iout=0.5A

Tc= 150°C

Tc= 25°C

Tc= - 40°C

Vcc (V)

Doc ID 17387 Rev 1 15/28

Electrical specifications VNQ810P-E

Figure 19. Input high level Figure 20. Input low level

Vih (V)

3.6

3.4

3.2

3

2.8

2.6

2.4

2.2

2

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 21. Open-load on-state detection

threshold

Iol (mA)

60

55

50

45

40

35

30

25

20

15

10

Vcc=13V

Vin=5V

-50 -25 0 25 50 75 100 125 150 175

Vil (V)

2.6

2.4

2.2

2

1.8

1.6

1.4

1.2

1

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 22. Open-load off-state voltage

detection threshold

Vol (V)

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

Vin=0V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Tc (°C)

Figure 23. Input hysteresis voltage

Vhyst (V)

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

16/28 Doc ID 17387 Rev 1

VNQ810P-E Application information

3 Application information

Figure 24. Application schematic

+5V

+5V

μ

R

C

+5V

V

R

prot

R

prot

prot

R

prot

STATUS1

INPUT1

STATUS2

INPUT2

CC1,2

V

CC3,4

OUTPUT1

D

ld

GND3,4

D

OUTPUT2

OUTPUT3

OUTPUT4

GND

R

prot

R

prot

R

prot

R

prot

+5V

+5V

STATUS3

INPUT3

STATUS4

INPUT4

GND1,2

V

GND

R

GND

Note: Channels 3 and 4 have the same internal circuit as channel 1 and 2.

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against
reverse battery.

3.1.1 Solution 1: a resistor in the ground line (R

It can be used with any type of load.

The following show how to dimension the R

Equation 1

R

≤ 600mV / 2 (I

GND

S(on)max

)

Doc ID 17387 Rev 1 17/28

GND

resistor:

GND

only)

Application information VNQ810P-E

Equation 2

R

GND

where - I

≥ ( - VCC) / ( - I

is the DC reverse ground pin current and can be found in the absolute

GND

GND

)

maximum rating section of the device datasheet.

Power dissipation in R

P

= ( - VCC)2/ R

D

GND

GND

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with Equation 1 where I
maximum on-state currents of the different devices.

Please note that, if the microprocessor ground is not shared by the device ground, then the
R

produces a shift (I

GND

S(on)max

values. This shift varies depending on how many devices are ON in the case of several high
side drivers sharing the same R

If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.

3.1.2 Solution 2: a diode (D

A resistor (R
inductive load. This small signal diode can be safely shared amongst several different HSD.
Also in this case, the presence of the ground network produces a shift ( 600mV) in the
input threshold and the status output values if the microprocessor ground is not common
with the device ground. This shift not varies if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the Absolute Maximum
Rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.

= 1kΩ) should be inserted in parallel to D

GND

(when V

GND

< 0 during reverse battery situations) is:

CC

* R

GND

) in the input thresholds and the status output

GND

.

) in the ground line

S(on)max

becomes the sum of the

if the device is driving an

GND

≈

3.2 Load dump protection

Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V

maximum DC rating. The same applies if the device is subject to transients on the VCC

CC

line that are greater than those shown in the ISO T/R 7637/1 table.

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (R
the microcontroller I/O pins from latching up.

The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:

- V

CCpeak

18/28 Doc ID 17387 Rev 1

/ I

latchup

≤ R

prot

≤ (V

OHμC

- V

IH

- V

GND

) / I

IHmax

) in line to prevent

prot

VNQ810P-E Application information

Example

For the following conditions:

V

CCpeak

I

latchup

V

OHμC

5kΩ ≤ R

= - 100 V

≥ 20 mA

≥ 4.5 V

≤ 65 kΩ.

prot

Recommended values are:

R

= 10 kΩ

prot

3.4 Open-load detection in off-state

Off-state open-load detection requires an external pull-up resistor (RPU) connected between
output pin and a positive supply voltage (V
microprocessor.

The external resistor has to be selected according to the following requirements:

1. No false open-load indication when load is connected: in this case we have to avoid
V

to be higher than V

OUT

V

= (V

OUT

PU

/ (RL + RPU))RL < V

; this results in the following condition

Olmin

Olmin.

2. No misdetection when load is disconnected: in this case the V
V

Because I
up resistor R

; this results in the following condition R

OLmax

may significantly increase if V

s(OFF)

should be connected to a supply that is switched OFF when the module is in

PU

standby.

) like the +5V line used to supply the

PU

has to be higher than

PU

- V

OUT

OLmax

) / I

L(off2)

< (V

PU

is pulled high (up to several mA), the pull-

out

.

The values of V

OLmin

, V

OLmax

and I

are available in Section 2.3: Electrical

L(off2)

characteristics.

Figure 25. Open-load detection in off-state

V

CC

INPUT

STATUS

DRIVER

+

LOGIC

+

-

VOL

GROUND

V batt. VPU

I

L(off2)

OUT

R

PU

R

R

L

Doc ID 17387 Rev 1 19/28

Application information VNQ810P-E

3.5 Maximum demagnetization energy (V

Figure 26. SO-28 (double island) maximum turn-off current versus load inductance

LMAX (A)

I

10

A

B

C

1

0.01 0.1 1 10 100
L(mH)

= 13.5V)

CC

A = single pulse at T

Jstart

B= repetitive pulse at T

C= repetitive pulse at T

VIN, I

L

Demagnetization

Note: Values are generated with R

In case of repetitive pulses, T
must not exceed the temperature specified above for curves B and C.

= 150 ºC

= 100 ºC

Jstart

= 125 ºC

Jstart

Demagnetization

= 0Ω.

L

(at beginning of each demagnetization) of every pulse

jstart

Demagnetization

t

20/28 Doc ID 17387 Rev 1

VNQ810P-E Package and PCB thermal data

4 Package and PCB thermal data

4.1 SO-28 thermal data

Figure 27. SO-28 double island PC board

Note: Layout condition of R

thickness = 2 mm, Cu thickness = 35 µm, Copper areas: 0.5 cm

Table 16. Thermal calculation according to the PCB heatsink area

Chip 1 Chip 2 T

ON OFF R

OFF ON R

ON ON R

ON ON

R

= thermal resistance junction to ambient with one chip ON

thA

R

= thermal resistance junction to ambient with both chips ON and P

thB

R

= mutual thermal resistance

thC

(R
+ T

thA

thC

thB

thA

amb

and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB

th

x P

x P

x (P

x P

dchip1

dchip2

dchip1

dchip1

jchip1

+ T

+ T

+ P

) + R

amb

amb

dchip2

thC

x P

) + T

dchip2

R

thC

R

thA

ambRthB

(R
+ T

thA

x P

x P

x (P

amb

x P

dchip1

dchip2

dchip1

dchip2

T

jchip2

+ T

+ T

+ P

) + R

2

, 3 cm2, 6 cm2).

amb

amb

) + T

dchip2

thC

x P

dchip1

ambPdchip1

dchip1

P

dchip1

= P

dchip2

Note

= P

≠ P

dchip2

dchip2

Doc ID 17387 Rev 1 21/28

Package and PCB thermal data VNQ810P-E

Figure 28. R

vs PCB copper area in open box free air condition

thj-amb

RTHj_am b

(°C/W)

70

60

50

40

30

20

10

01234567

PCB Cu heatsink area (cm^2)/island

Figure 29. SO-28 thermal impedance junction ambient single pulse

Zth(°C/W)

100

R

thA

R

thB

R

thC

0,5 cm ^2/island

3 cm ^2/island

6 cm ^2/island

10

1

0.1

0.01

0.0001 0.001 0.01 0.1 1 10 100 1000

time(s)

Equation 3

Z

THδRTH

where

: pulse calculation formula

δ Z

THtp

1 δ–()+⋅=

δ tpT⁄=

One channel ON

Two channels
ON on same chip

22/28 Doc ID 17387 Rev 1

VNQ810P-E Package and PCB thermal data

Figure 30. Thermal fitting model of a quad channel HSD in SO-28

Tj_1

Pd1

Tj_2

Pd2

Tj_3

Pd3

Tj_4

Pd4

C1

C13 C14

R13

C7

C15 C16

R15

R14

R16

C8

R8

C3 C4

R3R1 R6R5R2

R17

C9

R9R7

R4

R18

C10

R10

T_amb

C5 C6C2

C11 C12

R12R11

Table 17. Thermal parameters

Area / island (cm2)0.56

R1 = R7 = R13 = R15 (°C/W) 0.35

R2 = R8 = R14 = R16 (°C/W) 1.8

R3 = R9 (°C/W) 4.5

R4 = R10 (°C/W) 11

R5 = R11 (°C/W) 15

R6 = R12 (°C/W) 30 13

C1 = C7 = C13 = C15 (W.s/°C) 0.0001

C2 = C8 = C14 = C16 (W.s/°C) 7E-04

C3 = C9 (W.s/°C) 6E-03

C4 = C10 (W.s/°C) 0.2

C5 = C11 (W.s/°C) 1.5

C6 = C12 (W.s/°C) 5 8

R17 = R18 (°C/W) 150

Doc ID 17387 Rev 1 23/28

Package and packing information VNQ810P-E

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

5.2 SO-28 package information

Figure 31. SO-28 package dimensions

.

24/28 Doc ID 17387 Rev 1

VNQ810P-E Package and packing information

Table 18. SO-28 mechanical data

Millimeters

Symbol

Min. Typ. Max.

A 2.65

a1 0.10 0.30

b 0.35 0.49

b1 0.23 0.32

C0.50

c1 45° (typ.)

D 17.7 18.1

E 10.00 10.65

e1.27

e3 16.51

F 7.40 7.60

L 0.40 1.27

S 8° (max.)

Doc ID 17387 Rev 1 25/28

Package and packing information VNQ810P-E

5.3 SO-28 packing information

Figure 32. SO-28 tube shipment (no suffix)

Base Q.ty 28
Bulk Q.ty 700
Tube length (± 0.5) 532
A 3.5

C

B

A

Figure 33. SO-28 tape and reel shipment (suffix “TR”)

B 13.8
C (± 0.1) 0.6

All dimensions are in mm.

Reel dimensions

Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4

Tape dimensions

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

26/28 Doc ID 17387 Rev 1

500mm min

Empty components pock ets
saled with cover tape.

User direction of feed

Start

No componentsNo components Components

500mm min

VNQ810P-E Revision history

6 Revision history

Table 19. Document revision history

Date Revision Changes

27-Apr-2010 1 Initial release.

Doc ID 17387 Rev 1 27/28

VNQ810P-E

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28/28 Doc ID 17387 Rev 1