Datasheet VNQ5050AK-E Datasheet (ST)

Quad channel high side driver with analog current sense

Features

Parameters Symbol Value

Max supply voltage V

Operating voltage range V

Max on-state resistance (per ch.) R

Current limitation (typ) I

Off-state supply current I

1. Typical value with all loads connected.

■ General features:

– Inrush current active management by

power limitation
– Very low standby current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC

European directive

■ Diagnostic functions:

– Proportional load current sense
– High current sense precision for wide

current range
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage

■ Protection:

– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss of V
– Thermal shutdown

Table 1. Device summary

Package

CC

CC

ON

LIMH

S

41 V

4.5 to 36 V

50 mΩ

19 A

(1)

2µA

CC

VNQ5050AK-E

for automotive applications

PowerSSO-24

– Reverse battery protection (see Figure 25)
– Electrostatic discharge protection

Application

■ All types of resistive, inductive and capacitive

loads.

■ Suitable as LED driver.

Description

The VNQ5050AK-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology. It is intended for driving resistive or
inductive loads with one side connected to
ground. Active V
device against low energy spikes (see ISO7637
transient compatibility table).

This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open. When CS_DIS
is driven high, the CURRENT SENSE pin is in a
high impedance condition.

Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
a safe level up to thermal shutdown intervention.
Thermal shutdown with automatic restart allows
the device to recover normal operation as soon as
the fault condition disappears.

Order codes

Tube Tape and Reel

pin voltage clamp protects the

CC

PowerSSO-24 VNQ5050AK-E VNQ5050AKTR-E

May 2009 Doc ID 13329 Rev 9 1/31

www.st.com

1

Contents VNQ5050AK-E

Contents

1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20

3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20

3.1.2 Solution 2: a diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . 21

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23

4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2 PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31 Doc ID 13329 Rev 9

VNQ5050AK-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7. Switching (V
Table 8. Current sense (8V<V

Table 9. Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 13. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 14. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

=13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CC

Doc ID 13329 Rev 9 3/31

List of figures VNQ5050AK-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Delay response time between rising edge of output current and rising edge of current sense

(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. I

OUT/ISENSE

Figure 8. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 12. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 15. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 16. On-state resistance vs T
Figure 17. On-state resistance vs V

Figure 18. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 19. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 20. I

LIMH

vs T

Figure 21. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 22. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 23. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 24. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 25. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 26. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 27. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23

Figure 28. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 24

Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 25

Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 25

Figure 32. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 33. PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 34. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

vs I

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

OUT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4/31 Doc ID 13329 Rev 9

VNQ5050AK-E Block diagram and pin configuration

1 Block diagram and pin configuration

Figure 1. Block diagram

V

CC

V

CC

CLAMP

GND

INPUT1

LOGIC

INPUT2

INPUT3

INPUT4

Pwr

CS_DIS

Table 2. Pin functions

Name Function

V

CC

OUTPUT

GND

INPUT

n

n

Battery connection

Power output

Ground connection. Must be reverse battery protected by an external
diode/resistor network

Voltage controlled input pin with hysteresis, CMOS compatible. Controls
output switch state

UNDERVOLTAGE

DRIVER 1

I

OUT1

1

LIM

PwCLAMP 1

I

LIM

V

DSLIM

OVERTEMP. 1

K 1

OUTPUT1

CURRENT
SENSE1

V

1

1

INPUT2

CURRENT

SENSE2

INPUT3

CURRENT

SENSE3

INPUT4

CURRENT

SENSE4

Control & Protection
Equivalent to
channel1

Control & Protection
Equivalent to
channel1

Control & Protection
Equivalent to
channel1

CC

V

CC

V

CC

OUTPUT2

CURRENT
SENSE2

OUTPUT3

CURRENT
SENSE3

OUTPUT4

CURRENT
SENSE4

CURRENT SENSE

Analog current sense pin, delivers a current proportional to the load current

n

CS_DIS Active high CMOS compatible pin, to disable the current sense pin

Doc ID 13329 Rev 9 5/31

Block diagram and pin configuration VNQ5050AK-E

Figure 2. Configuration diagram (top view)

V

CC

GND

INPUT1

CURRENT SENSE1

INPUT2

CURRENT SENSE2

INPUT3

CURRENT SENSE3

INPUT4

CURRENT SENSE4

CS_DIS.

V

CC

OUTPUT1

OUTPUT1

OUTPUT1

OUTPUT2

OUTPUT2

OUTPUT2

OUTPUT3

OUTPUT3

OUTPUT3

OUTPUT4

OUTPUT4

OUTPUT4

TA B = V

Table 3. Suggested connections for unused and not connected pins

CC

Connection/pin Current sense N.C. Output Input CS_DIS

Floating N.R.

To ground

1. Not recommended.

(1)

Through 1 kΩ

resistor

XX X X

XN.R.

Through 10 kΩ

resistor

Through 10 kΩ

resistor

6/31 Doc ID 13329 Rev 9

VNQ5050AK-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I

S

V

CC

I

CSD

V

CSD

I

INn

V

INn

CS_DIS

INPUTn

GND

OUTPUTn

CURRENT
S

ENSEn

I

GND

I

SENSEn

V

SENSEn

V

Fn

I

OUTn

V

OUTn

V

CC

Note: V

Fn

= V

- VCC during reverse battery condition.

OUTn

2.1 Absolute maximum ratings

Stress values that exceed those listed in the “Absolute maximum ratings” table can cause
permanent damage to the device. These are stress ratings only, and operation of the device
at these, or any other conditions greater than those, indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics sure
program and other relevant quality documents.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

- I

- I

V

-V

I

OUT

DC supply voltage 41 V

CC

Reverse DC supply voltage 0.3 V

CC

DC reverse ground pin current 200 mA

GND

DC output current Internally limited A

Reverse DC output current 20 A

OUT

DC input current -1 to 10 mA

I

IN

I

CSD

-I

CSENSE

V

CSENSE

E

DC current sense disable input current -1 to 10 mA

DC reverse CS pin current 200 mA

Current sense maximum voltage

Maximum switching energy (single pulse)

MAX

(L=3 mH; R

=0 Ω; V

L

=13.5 V; T

bat

jstart

=150 ºC; I

OUT

= I

limL

(Typ.))

V

-41

CC

+V

CC

104 mJ

V
V

Doc ID 13329 Rev 9 7/31

Electrical specifications VNQ5050AK-E

Table 4. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Electrostatic discharge
(human body model: R=1.5KΩ; C=100pF)

4000
2000
4000
5000
5000

V
V
V
V
V

V

V

ESD

ESD

T

– Input
– Current sense
–CS_DIS
– Output
–V

CC

Charge device model (CDM-AEC-Q100-011) 750 V

Junction operating temperature -40 to 150 °C

T

j

Storage temperature -55 to 150 °C

stg

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter Max value Unit

R

thj-case

R

thj-amb

Thermal resistance junction-case (With one channel ON) 2.8 °C/W

Thermal resistance junction-ambient See Figure 29 °C/W

8/31 Doc ID 13329 Rev 9

VNQ5050AK-E Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8 V<VCC<36V, -40°C<Tj<150 °C, unless otherwise
stated.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

USDhyst

R

V

clamp

I

L(off)

1. PowerMOS leakage included.

2. For each channel.

Operating supply voltage 4.5 13 36 V

CC

Undervoltage shutdown - 3.5 4.5 V

USD

Undervoltage shutdown
hysteresis

On-state resistance

ON

Clamp voltage IS=20 mA 41 46 52 V

I

Supply current

S

Off-state output current

Output - VCC diode

V

F

voltage

(2)

I

=2 A; Tj=25 °C

OUT

=2 A; Tj=150 °C

I

OUT

I

=2 A; VCC=5 V; Tj=25 °C

OUT

Off-State; VCC=13 V; Tj=25 °C;
VIN=V

OUT=VSENSE=VCSD

On-State; V
I

OUT

VIN=V
Tj=25 °C

(2)

V

=0 A

OUT

IN=VOUT

=13 V; VIN=5 V;

CC

=0 V; VCC=13 V;

=0 V; VCC=13 V;

Tj=125 °C

-I

=2 A; Tj=150 °C - - 0.7 V

OUT

=0 V

-0.5 - V

mΩ

--50100

(1)

2

5

­8

000.01 3

mΩ

65

mΩ

(1)

14µAmA

µA

5

Table 7. Switching (VCC=13V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

d(on)

t

d(off)

(dV

OUT

(dV

OUT

W

ON

W

OFF

Turn-on delay time RL= 6.5 Ω (see Figure 6)- 20 - µs

Turn-off delay time RL= 6.5 Ω (see Figure 6)- 45 - µs

/dt)onTurn-on voltage slope RL= 6.5 Ω -

/dt)

Turn-off voltage slope RL= 6.5 Ω -

off

Switching energy
losses during t

won

Switching energy
losses during

t

woff

RL= 6.5 Ω (see Figure 6) - 0.15 - mJ

RL= 6.5 Ω (see Figure 6)- 0.3 - mJ

See

Figure 19

See

Figure 21

-V/µs

-V/µs

Doc ID 13329 Rev 9 9/31

Electrical specifications VNQ5050AK-E

Table 8. Current sense (8V<VCC<16V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

= 0.05 A;

OUT

dK

dK

K

K

1/K1

K

2/K2

I

0

1

2

OUT/ISENSE

I

OUT/ISENSE

(1)

Current sense ratio drift

I

OUT/ISENSE

(1)

Current sense ratio drift

V
T

I
V
T

= 0.5 V; V

SENSE

= -40°C...150°C

j

= 1 A;

OUT

= 0.5 V; V

SENSE

= -40°C...150°C

j

CSD

CSD

Tj= 25 °C...150 °C

I

= 1 A; V

OUT

V

= 0 V;

CSD

= -40 °C to 150 °C

T

J

I

= 2 A;

OUT

V
T
T

I
V

= 4 V; V

SENSE

= -40°C...150°C

j

= 25 °C...150 °C

j

= 2 A; V

OUT

= 0 V;

CSD

SENSE

CSD

SENSE

= 0.5 V;

= 4 V;

TJ= -40 °C to 150 °C

=0 V;

=0 V;

= 0 V;

1340 2420 3460

1370

1860

2510

1510

1860

2210

-10 - 10 %

1590

1760

2140

1600

1760

1930

-8 - 8 %

I

= 4 A;

OUT

dK

K

3

3/K3

I

OUT/ISENSE

(1)

Current sense ratio drift

V
T
T

I
V

= 4 V; V

SENSE

= -40°C...150°C

j

= 25 °C...150 °C

j

= 4 A; V

OUT

CSD

SENSE

= 0 V;

CSD

= 0 V;

= 4 V;

1650

1740

1950

1650

1740

1830

-5 - 5 %

-

TJ= -40 °C to 150 °C

I

I

SENSE0

Analog sense leakage
current

= 0 A; V

OUT

V

= 5 V; VIN= 0 V;

CSD

= -40°C...150°C

T

j

= 0 V; VIN= 5 V;

V

CSD

= -40°C...150°C

T

j

= 2 A; V

I

OUT

= 5 V; VIN= 5 V;

V

CSD

= -40°C...150°C

T

j

SENSE

SENSE

= 0 V;

= 0 V;

0

-

1

µA

0

-

2

µA

0

-

1

µA

Openload ON state

I

OL

current detection

VIN = 5 V, I

= 5 µA 4 - 20 mA

SENSE

threshold

V

SENSE

Max analog sense
output voltage

I

OUT

= 4 A; V

= 0 V 5 - - V

CSD

Analog sense output

V

SENSEH

voltage in over

V

CC

= 13 V; R

= 10 KΩ -9-V

SENSE

temperature condition

10/31 Doc ID 13329 Rev 9

VNQ5050AK-E Electrical specifications

Table 8. Current sense (8V<VCC<16V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Analog sense output

I

SENSEH

t

DSENSE1H

t

DSENSE1L

current in over
temperature condition

Delay response time
from falling edge of
CS_DIS pin

Delay response time
from rising edge of
CS_DIS pin

= 13 V; V

V

CC

V
I

<4 V, 0.5 A<Iout<4 A

SENSE

= 90 % of I

SENSE

(see Figure 4)

V
I

<4 V, 0.5 A<Iout<4 A

SENSE

=10 % of I

SENSE

(see Figure 4)

= 5 V - 8 - mA

SENSE

SENSE max

SENSE max

-50100µs

- 5 20 µs

Delay response time

t

DSENSE2H

from rising edge of
INPUT pin

Delay response time
between rising edge of

Δ

t

DSENSE2H

output current and
rising edge of current
sense

Delay response time

t

DSENSE2L

from falling edge of
INPUT pin

1. Parameter guaranteed by design; it is not tested.

Table 9. Protection

(1)

V
I
(see Figure 4)

V
I
I
I

V
I
(see Figure 4)

<4 V, 0.5 A<Iout<4 A

SENSE

=90 % of I

SENSE

<4 V,

SENSE

=90 % of I

SENSE

=90 % of I

OUT

OUTMAX

=2 A (see Figure 5)

<4 V, 0.5 A<Iout<4 A

SENSE

=10 % of I

SENSE

SENSE max

SENSEMAX,

OUTMAX

SENSE max

-80250µs

- - 65 µs

- 100 250 µs

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

limH

DC short circuit
current

=13 V

V

CC

5V<V

CC

<36 V

13.5 19 26.5

26.5

Short circuit current

I

limL

during thermal

V

=13 V; TR<Tj<T

CC

TSD

-7-A

cycling

T

TSD

Shutdown
temperature

150 175 200 °C

A
A

T

Reset temperature TRS + 1 TRS + 5 - °C

R

T

T

V

DEMAG

V

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related

Thermal reset of

RS

STATUS

Thermal hysteresis

HYST

(T

Turn-off output
voltage clamp

Output voltage drop

ON

limitation

diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

TSD-TR

)

=2 A; VIN=0; L=6 mH VCC-41 VCC-46 VCC-52 V

I

OUT

I

=0.1 A; Tj=-40 °C...150 °C

OUT

(see Figure 9)

135 - - °C

-7-°C

-25-mV

Doc ID 13329 Rev 9 11/31

Electrical specifications VNQ5050AK-E

Table 10. Logic input

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

V

I

V

I(hyst)

V

ICL

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

V

CSCL

Input low level voltage - - 0.9 V

IL

Low level input current VIN= 0.9 V 1 - - µA

IL

Input high level voltage 2.1 - - V

IH

High level input current VIN= 2.1 V - - 10 µA

IH

Input hysteresis voltage 0.25 - - V

I

= 1 mA

Input clamp voltage

IN

= -1 mA

I

IN

CS_DIS low level voltage - - 0.9 V

Low level CS_DIS current V

=0.9 V 1 - - µA

CSD

CS_DIS high level voltage 2.1 - - V

High level CS_DIS current V

=2.1 V - - 10 µA

CSD

CS_DIS hysteresis voltage 0.25 - - V

I

= 1 mA

CS_DIS clamp voltage

CSD

I

CSD

= -1 mA

Figure 4. Current sense delay characteristics

INPUT

CS_DIS

5.5

5.5

-0.7

-0.7

7V

V

7V

V

LOAD CURRENT

SENSE CURRENT

t

DSENSE2H

t

DSENSE1L

t

DSENSE1H

t

DSENSE2L

12/31 Doc ID 13329 Rev 9

VNQ5050AK-E Electrical specifications

Figure 5. Delay response time between rising edge of output current and rising

edge of current sense (CS enabled)

V

IN

Δ

t

DSENSE2H

t

I

OUT

90% I

OUTMAX

I

OUTMAX

t

I

SENSE

Figure 6. Switching characteristics

V

OUT

t

Won

80%

dV

/dt

OUT

(on)

t

r

INPUT

t

d(on)

90% I

10%

I

SENSEMAX

SENSEMAX

t

d(off)

t

Woff

90%

t

f

dV

OUT

/dt

t

(off)

t

t

Doc ID 13329 Rev 9 13/31

Electrical specifications VNQ5050AK-E

Figure 7. I

I

/ I

out

sense

2600

2400

2200

2000

1800

1600

1400

1200

1000

min Tj = 25 °C to 150 °C

11,522,533,544,55

OUT/ISENSE

vs I

max Tj = -40 °C to 150 °C

min Tj = -40 °C to 150 °C

OUT

max Tj = 25 °C to 150 °C

I

OUT

typical value

(A)

Figure 8. Maximum current sense ratio drift vs load current

dk/k(%)

15

10

5

0

-5

-10

-15

1 1,5 2 2,5 3 3,5 4

Note: Parameter guaranteed by design; it is not tested.

I

OUT

(A)

14/31 Doc ID 13329 Rev 9

VNQ5050AK-E Electrical specifications

Table 11. Truth table

Conditions Input Output Sense (V

Normal operation

CSD

L

H

L
H

0

Nominal

=0 V)

(1)

Over temperature

Undervoltage

Short circuit to GND
(Rsc ≤ 10 mΩ)

Short circuit to V

CC

L

H

L

H

L
H
H

L
H

L
L

V

SENSEH

L
L

L
L
L

0 if T

V

SENSEH

H
H

< Nominal

Negative output voltage clamp L L 0

1. If the V
and external circuit.

is high, the SENSE output is at a high impedance, its potential depends on leakage currents

CSD

Figure 9. Output voltage drop limitation

Vcc-Vout

Tj=150oC

Tj=25

Tj=-40

o

C

o

C

0

0
0

0

< T

j

TSD

if Tj > T

0

TSD

Von

Iout

Von/Ron(T)

Doc ID 13329 Rev 9 15/31

Electrical specifications VNQ5050AK-E

Table 12. Electrical transient requirements (part 1/3)

ISO 7637-2:

2004(E)

test pulse

1 -75 V -100 V

2a +37 V +50 V

Test levels

III IV

Number of

pulses or

test times

5000

pulses

5000

pulses

Burst cycle/pulse

repetition time

Delays and
Impedance

0.5 s 5 s 2 ms, 10 Ω

0.2 s 5 s 50 µs, 2 Ω

3a -100 V -150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω

3b +75 V +100 V 1h 90 ms 100 ms 0.1 µs, 50 Ω

4 -6 V -7 V 1 pulse -

5b

(2)

+65 V +87 V 1 pulse - 400 ms, 2 Ω

100 ms, 0.01

Table 13. Electrical transient requirements (part 2/3)

ISO 7637-2:

Test level results

2004(E)

test pulse

III IV

1C C

2a C C

(1)

Ω

3a C C

3b C C

4C C

(2)

5b

CC

1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

Table 14. Electrical transient requirements (part 3/3)

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure

E

to disturbance and cannot be returned to proper operation without replacing the
device.

16/31 Doc ID 13329 Rev 9

VNQ5050AK-E Electrical specifications

2.4 Electrical characteristics curves

Figure 10. Off-state output current Figure 11. High level input current

Iloff (uA)

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

-50 -25 0 25 50 75 100 125 150 175

Off state
Vcc=13V

Vin=Vout=0V

Tc (° C)

Iih (uA)

5

4.5

3.5

2.5

1.5

0.5

Vin=2.1V

4

3

2

1

0

-50 -25 0 25 50 75 100 1 25 150 175

Tc ( °C )

Figure 12. Input clamp voltage Figure 13. Input low level

Vicl (V)

7

6.8

6.6

6.4

6.2

5.8

5.6

5.4

5.2

Iin=1mA

6

5

-50 -25 0 25 50 75 100 125 150 175

Tc (° C)

Vil (V)

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

-50 -25 0 25 50 75 100 1 25 150 175

Tc ( °C )

Figure 14. Input high level Figure 15. Input hysteresis voltage

Vih (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Doc ID 13329 Rev 9 17/31

Vhyst (V)

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Electrical specifications VNQ5050AK-E

Figure 16. On-state resistance vs T

Ron (mOhm)

100

90

80

70

60

50

40

30

20

10

0

-50 -25 0 25 50 75 100 125 150 175

Iout=2A

Vcc=13V

Tc (°C)

case

Figure 17. On-state resistance vs V

Ron (mOhm)

100

90

80

70

60

50

40

30

20

10

0

0 5 10 15 20 25 30 35 40

Vcc (V)

Tc= 150 °C

Tc= 12 5°C

Tc= 25° C

Tc= -4 0°C

Figure 18. Undervoltage shutdown Figure 19. Turn-on voltage slope

Vusd (V)

16

14

12

10

8

6

4

2

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

(dVout/dt)on (V/ms)

1000

900

800

700

600

500

400

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

Rl=6.5Ohm

Tc ( °C )

CC

Figure 20. I

LIMH

vs T

case

Ilimh (A)

25

22.5

20

17.5

15

12.5

10

7.5

5

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

Tc ( °C )

18/31 Doc ID 13329 Rev 9

Figure 21. Turn-off voltage slope

(dVout/dt)off (V/ms)

1000

900

800

700

600

500

400

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

Rl=6.5Ohm

Tc (°C)

VNQ5050AK-E Electrical specifications

Figure 22. CS_DIS high level voltage Figure 23. CS_DIS clamp voltage

Vcsdh (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 24. CS_DIS low level voltage

Vcsdl (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75 100 1 25 150 175

Tc ( °C )

Vcsdcl (V)

8

7.5

7

Icsd=1mA

6.5

6

5.5

5

4.5

4

-50 -25 0 25 50 75 100 125 150 175

Tc (° C)

Doc ID 13329 Rev 9 19/31

Application information VNQ5050AK-E

3 Application information

Figure 25. Application schematic

+5V

V

CC

R

prot

μ

C

R

prot

CS_DIS

IINPUT

OUTPUT

D

ld

R

prot

C

ext

CURRENT SENSE

R

SENSE

GND

R

GND

GND

D

GND

V

Note: Channel 2, 3, 4 have the same internal circuit as channel 1.

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (R

This can be used with any type of load.

The following is an indication on how to dimension the R

1. R

2. R

where -I
maximum rating section of the device datasheet.

≤ 600 mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

S(on)max

GND

).

)

GND

only)

resistor.

GND

Power Dissipation in R

P

= (-VCC)2/R

D

GND

(when VCC<0: during reverse battery situations) is:

GND

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the
R

will produce a shift (I

GND

S(on)max

values. This shift will vary depending on how many devices are ON in the case of several

* R

high side drivers sharing the same R

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).

20/31 Doc ID 13329 Rev 9

S(on)max

) in the input thresholds and the status output

GND

.

GND

becomes the sum of the

VNQ5050AK-E Application information

3.1.2 Solution 2: a diode (D

A resistor (R

= 1 kΩ) should be inserted in parallel to D

GND

) in the ground line.

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V

max DC rating. The same applies if the device is subject to transients on the VCC line

CC

that are greater than the ones shown in the ISO T/R 7637/1 table.

3.3 Microcontroller I/Os protection

If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.

if the device drives an

GND

prot

) in line to

-V

CCpeak/Ilatchup

≤ R

prot

≤ (V

OHμC-VIH-VGND

) / I

IHmax

Calculation example:

For V

5kΩ ≤ R

Recommended values: R

CCpeak

prot

= - 100 V and I

≤ 180 kΩ.

latchup

= 10 kΩ, C

prot

≥ 20 mA; V

EXT

OHμC

= 10 nF.

≥ 4.5 V

Doc ID 13329 Rev 9 21/31

Application information VNQ5050AK-E

Figure 26. Waveforms

NORMAL OPERATION

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

UNDERVOLTAGE

V

V

CC

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

V

USD

USDhyst

INPUT

CS_DIS

LOAD VOLTAGE

LOAD CURRENT

SENSE CURRENT

T

j

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

T

R

T

T

TSD

RS

current

limitation

<Nominal

power
limitation

SHORT TO V

CC

<Nominal

OVERLOAD OPERATION

thermal cycling

SHORTED LOAD NORMAL LOAD

I

LIMH

I

LIML

V

SENSEH

22/31 Doc ID 13329 Rev 9

VNQ5050AK-E Application information

3.4 Maximum demagnetization energy (VCC=13.5V)

Figure 27. Maximum turn-off current versus inductance (for each channel)

100

A

B

10

I (A)

1

0,1110100L (mH)

C

A: T

B: T

C: T

VIN, I

= 150°C single pulse

jstart

= 100°C repetitive pulse

jstart

= 125°C repetitive pulse

jstart

L

Note: Values are generated with R

In case of repetitive pulses, T
must not exceed the temperature specified above for curves A and B.

Demagnetization Demagnetization Demagnetization

=0Ω.

L

(at beginning of each demagnetization) of every pulse

jstart

t

Doc ID 13329 Rev 9 23/31

Package and PC board thermal data VNQ5050AK-E

4 Package and PC board thermal data

4.1 PowerSSO-24 thermal data

Figure 28. PowerSSO-24 PC board

Note: Layout condition of R

area= 77 mm x 86 mm, PCB thickness=1.6mm, Cu thickness=70 µm (front and back side),
Copper areas: from minimum pad lay-out to 8 cm

Figure 29.

RTHj_amb(°C/W)

R

thj-amb

55

50

45

40

35

30

0246810

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

vs PCB copper area in open box free air condition (one channel on)

PCB Cu heatsink area (cm^2)

24/31 Doc ID 13329 Rev 9

VNQ5050AK-E Package and PC board thermal data

Figure 30.

PowerSSO-24 thermal impedance junction ambient single pulse (one channel on)

ZTH (°C/W)

1000

100

10

1

0.1

0.0001 0.001 0.01 0.1 1 10 100 1000

Time (s)

Footprint

2

2 cm

8 cm

2

Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24

(a)

a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Doc ID 13329 Rev 9 25/31

Package and PC board thermal data VNQ5050AK-E

Equation 1: pulse calculation formula

Z

THδ

R

TH

δ Z

THtp

1 δ–()+⋅=

where δ = tP/T

Table 15. Thermal parameters

Area/island (cm2)Footprint28

R1=R7=R9=R11 (°C/W) 0.4 - -

R2=R8=R10=R12 (°C/W) 2 - -

R3 (°C/W) 6 - -

R4 (°C/W) 7.7 - -

R5 (°C/W) 9 9 8

R6 (°C/W) 28 17 10

C1=C7=C9=C11 (W.s/°C) 0.001 - -

C2=C8=C10=C12 (W.s/°C) 0.0022 - -

C3 (W.s/°C) 0.025 - -

C4 (W.s/°C) 0.75 - -

C5 (W.s/°C) 1 4 9

C6 (W.s/°C) 2.2 5 17

26/31 Doc ID 13329 Rev 9

VNQ5050AK-E Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com

ECOPACK® is an ST trademark.

5.2 PowerSSO-24™ mechanical data

Table 16. PowerSSO-24™ mechanical data

Symbol

Min. Typ. Max.

A- -2.45

A2 2.15 - 2.35

Millimeters

.

a1 0 - 0.10

b 0.33 - 0.51

c 0.23 - 0.32

D 10.10 - 10.50

E7.4 - 7.6

e-0.8-

e3 - 8.8 -

G- -0.1

G1 - - 0.06

H 10.1 - 10.5

h--0.4

k0°-8°

L 0.55 - 0.85

N- -10º

X4.1 - 4.7

Y6.5 - 7.1

Doc ID 13329 Rev 9 27/31

Package and packing information VNQ5050AK-E

Figure 32. PowerSSO-24™ package dimensions

28/31 Doc ID 13329 Rev 9

VNQ5050AK-E Package and packing information

5.3 Packing information

Figure 33. PowerSSO-24 tube shipment (no suffix)

Base Q.ty 49
Bulk Q.ty 1225

C

B

A

Figure 34. PowerSSO-24 tape and reel shipment (suffix “TR”)

Tube length (± 0.5) 532
A 3.5
B 13.8
C (± 0.1) 0.6

All dimensions are in mm.

Reel dimensions

Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 24.4
N (min) 100
T (max) 30.4

Tape dimensions

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986

Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

End

Start

Top

cover

tape

500mm min

Empty components pockets
saled with cover tape.

User direction of feed

No componentsNo components Components

500mm min

Doc ID 13329 Rev 9 29/31

Revision history VNQ5050AK-E

6 Revision history

Table 17. Document revision history

Date Revision Changes

14-Sep-2004 1 Initial release.

12-Jan-2006 2 Major general update.

Reformatted and restructured.
Added contents, lists of tables and list of figures.

9-Mar-2007 3

22-Aug-2007 4

01-Oct-2007 5

Added Section 3.4: Maximum demagnetization energy

(VCC = 13.5V).

Added ECOPACK® packages information.
Added new disclaimer.

Figure 14: Input high level and Figure 15: Input hysteresis voltage

corrected.

Table 4: Absolute maximum ratings: changed E

value from 51 to

MAX

104 mJ.

Table 8: Current sense (8V<V

dk3/k3, Δt

DSENSE2H

.

<16V): added dk1/k1, dk2/k2,

CC

Added Figure 5: Delay response time between rising edge of output

current and rising edge of current sense (CS enabled).

Updated Figure 7: I

OUT/ISENSE

vs I

OUT

.

Added Figure 8: Maximum current sense ratio drift vs load current.

Table 12: Electrical transient requirements (part 1/3): added notes.
Figure 31: Thermal fitting model of a double channel HSD in

PowerSSO-24, added note.

CC

<16V):

CC

<16V):

04-Dec-2007 6

12-Feb-2008 7

14-May-2009 8

Updated Table 8: Current sense (8V<V
– changed t
– added I

OL

DSENSE2H

parameter.

max value from 300 µs to 250µs.

Corrected typing error in Table 8: Current sense (8V<V
changed I

test condition from VIN = 0V to VIN = 5V.

OL

Table 16: PowerSSO-24™ mechanical data:

– Updated a1 (max) from 0.075 to 0.10.

Table 16: PowerSSO-24™ mechanical data:

– Updated A (min) from 2.15 to - and A (max) from 2.47 to 2.45

29-May-2009 9

– Updated A2 (max) from 2.40 to 2.35
– Updated k (min) from - to 0°, k (typ) from 5° to - and

k (max) from - to 8°

30/31 Doc ID 13329 Rev 9

VNQ5050AK-E

Please Read Carefully:

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