Datasheet VND920 Datasheet (ST)

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Page 1

Double channel high-side solid-state relay

Features

Typ e R

VND920 16 mΩ 35 A

1. Per channel with all the output pins connected to the PCB.

DS(on

OUT

(1)

36 V

VND920

■ CMOS compatible input

■ Proportional load current sense

■ Shorted load protection

■ Undervoltage and overvoltage shutdown

■ Overvoltage clamp

■ Thermal shutdown

■ Current limitation

■ Protection against loss of ground and loss of

■

Very low standby power dissipation

■ Reverse battery protected

Table 1. Device summary

SO-28 (double island)

Description

The VND920 is a double chip device designed in STMicroelectronics™ VIPower™ M0-3 technology. The VND920 is intended for driving any type of load with one side connected to ground. The active V protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload.

The device integrates an analog current sense output which delivers a current proportional to the load current. The device automatically turns off in the case where the ground pin becomes disconnected.

pin voltage clamp

Order codes

Package

Tube Tape and reel

SO-28 VND920 VND92013TR

February 2011 Doc ID 7767 Rev 5 1/26

www.st.com

Page 2

Contents VND920

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17

3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 17

3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 18

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 19

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/26 Doc ID 7767 Rev 5

Page 3

VND920 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Switching (V Table 7. V

Table 8. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9. Current sense (9 V £ VCC £ 16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 13. Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 14. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 15. SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

output diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

= 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Doc ID 7767 Rev 5 3/26

Page 4

List of figures VND920

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. I

Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11. Over-voltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 13. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 14. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 15. Input high-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 17. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 18. Input low-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 19. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 20. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 21. SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 22. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 21

Figure 23. Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 24. Thermal fitting model of a double channel HSD in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 25. SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 26. SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 27. SO-28 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

OUT/ISENSE

versus I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

OUT

4/26 Doc ID 7767 Rev 5

Page 5

VND920 Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

GND 1

INPUT 1

GND 2

CLAMP

OVERTEMPERATURE

DETECTION

CLAMP

LOGIC

OVERVOLTAGE

DETECTION

UNDERVOLTAGE

DETECTION

DRIVER

CURRENT LIMITER

VDS LIMITER

OVERVOLTAGE

DETECTION

UNDERVOLTAGE

DETECTION

Power CLAMP

OUTPUT 1

OUT CURRENT

Power CLAMP

SENSE 1

DRIVER

INPUT 2

LOGIC

OVERTEMPERATURE

DETECTION

CURRENT LIMITER

VDS LIMITER

OUT CURRENT

OUTPUT 2

SENSE 2

Doc ID 7767 Rev 5 5/26

Page 6

Block diagram and pin description VND920

Figure 2. Configuration diagram (top view)

GND 1

INPUT 1

CURRENT SENSE 1

NC NC

GND 2

INPUT 2

CURRENT SENSE 2

NC NC

Table 2. Suggested connections for unused and not connected pins

Connection / pin Current Sense N.C. Output Input

Floating X X X

OUTPUT 1 OUTPUT 1 OUTPUT 1

OUTPUT 2

OUTPUT 2 OUTPUT 2

OUTPUT 2

OUTPUT 2 OUTPUT 2

To ground

Through 1KΩ

resistor

Through 10KΩ

resistor

6/26 Doc ID 7767 Rev 5

Page 7

VND920 Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

CC1

Note: V

= V

CCn

- V

IN1

IN2

during reverse battery condition.

OUTn

INPUT1

INPUT2

GROUND1

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality document.

Table 3. Absolute maximum ratings

GND1

CC2

OUTPUT1

OUTPUT2

GROUND2

CC1

CURRENT SENSE 1

CURRENT SENSE 2

GND2

OUT1

SENSE1

OUT2

SENSE2

OUT2

(*)

SENSE1

OUT1

CC2

Symbol Parameter Value Unit

-V

-I

OUT

-I

OUT

CSENSE

gnd

DC supply voltage 41 V

Reverse DC supply voltage - 0.3 V

DC reverse ground pin current - 200 mA

DC output current Internally limited A

Reverse DC output current - 21 A

DC input current +/- 10 mA

Current sense maximum voltage

- 3

+ 15

V V

Electrostatic discharge (human body model: R = 1.5 KΩ; C=100pF)

ESD

–INPUT – CURRENT SENSE –OUTPUT –V

4000 2000 5000 5000

V V V V

Doc ID 7767 Rev 5 7/26

Page 8

Electrical specifications VND920

Table 3. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Maximum switching energy

MAX

stg

(L = 0.25 mH; R T

= 150 °C; IL=45A)

jstart

Power dissipation TC≤ 25 °C 6.25 W

tot

Junction operating temperature Internally limited °C

Case operating temperature - 40 to 150 °C

=0Ω; V

=13.5V;

bat

Storage temperature - 55 to 150 °C

355 mJ

2.2 Thermal data

Table 4. Thermal data (per island)

Symbol Parameter Value Unit

thj-lead

thj-amb

1. When mounted on a standard single-sided FR-4 board with 1cm2 of Cu (at least 35 µm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow.

2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35 µm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow.

Thermal resistance junction-lead 20 °C/W

Thermal resistance junction-ambient (one chip ON) 60

Thermal resistance junction-ambient (two chips ON) 46

(1)

(2)

°C/W

8/26 Doc ID 7767 Rev 5

Page 9

VND920 Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8 V < VCC<36V; -40 °C < Tj< 150 °C, unless otherwise stated.

Tabl e 5. Powe r

Symbol Parameter Test conditions Min. Typ. Max. Unit

USD

CLAMP

L(off1)

L(off2)

L(off3)

L(off4)

Operating supply voltage 5.5 13 36 V

Undervoltage shutdown 3 4 5.5 V

Overvoltage shutdown 36 V

=10A; Tj= 25 °C; 16 mΩ

OUT

On-state resistance

=10A; 32 mΩ

OUT

=3A; VCC=6V 55 mΩ

OUT

Clamp voltage ICC=20mA 41 48 55 V

Supply current

Off-state output current VIN=V

Off-state output current VIN=0V; V

Off-state output current

Off-state; V V

IN=VOUT

Off-state; V VIN=V

On-state; V I

=0A; R

OUT

IN=VOUT

Tj=125°C

IN=VOUT

Tj=25°C

=13V;

=0V

=13V;

=0V; Tj= 25 °C

OUT

=13V; VIN=5V;

= 0 V 0 50 µA

OUT

=3.9kΩ

SENSE

=3.5V -75 0 µA

10 25 µA

10 20 µA

=0V; VCC=13V;

5mA

5µA

3µA

Note: V

and VOV are correlated. Typical difference is 5V.

CLAMP

Table 6. Switching (VCC=13V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

d(on)

d(off)

OUT

Tabl e 7. VCC output diode

Turn-on delay time RL=1.3Ω (see Figure 4)50µs

Turn-off delay time RL=1.3Ω (see Figure 4)50µs

/dt

Turn-on voltage slope RL=1.3Ω (see Figure 4) See Figure 10 V/µs

(on)

/dt

Turn-off voltage slope RL=1.3Ω (see Figure 4) See Figure 12 V/µs

(off)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Forward on voltage -I

=5A; Tj= 150 °C 0.6 V

OUT

Doc ID 7767 Rev 5 9/26

Page 10

Electrical specifications VND920

Table 8. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

I(hyst)

Table 9. Current sense (9 V ≤ VCC≤ 16 V)

Input low-level voltage 1.25 V

Low-level input current VIN=1.25V 1 µA

Input high-level voltage 3.25 V

High-level input current VIN= 3.25 V 10 µA

Input hysteresis voltage 0.5 V

=1mA 6 6.8 8 V

Input clamp voltage

ICL

=-1mA -0.7 V

Symbol Parameter Test conditions Min. Typ. Max. Unit

dK1/K

2/K2

OUT/ISENSE

Current sense

ratio drift

OUT/ISENSE

Current sense ratio drift

OUT/ISENSE

=1A; V

OUT

Tj= -40 °C...150 °C

=1A; V

OUT

Tj= -40 °C...150 °C

= 10 A; V

OUT

Tj= -40 °C; Tj= 25°C...150°C

= 10A; V

OUT

= -40 °C...150 °C

= 30 A; V

OUT

= -40 °C

Tj = 25 °C...150 °C

SENSE

=0.5V;

= 4 V;

= 4V;

= 4 V;

3300 4400 6000

-10 +10 %

4200

4900

6000

4400

4900

5750

-8 +8 %

4200

4900

5500

4400

4900

5250

= 30 A; V

3/K3

SENSE0

SENSE

Current sense ratio drift

Analog sense current

Max analog sense output voltage

OUT

= -40 °C...150 °C

= 6...16 V; I

V T

V R

= 0 V;

SENSE

= -40 °C...150 °C

= 5.5 V; I

= 10 kΩ

SENSE

> 8 V, I

SENSE

OUT

= 10 kΩ

SENSE

OUT

= 10 A;

= 5 A;

Sense voltage in

SENSEH

overtemperature

= 13 V; R

SENSE

condition

10/26 Doc ID 7767 Rev 5

= 4 V;

-6 +6 %

= 0 A;

010µA

= 3.9 kΩ 5.5 V

Page 11

VND920 Electrical specifications

Table 9. Current sense (9 V ≤ VCC≤ 16 V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Analog sense output

VSENSEH

impedance in overtemperature condition

DSENSE

1. Current sense signal delay after positive input slope.

Table 10. Protections

Current sense delay response

(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

= 13 V; Tj > T

To 9 0 % I

SENSE

; output open 400 Ω

TSD

(1)

500 µs

TSD

hyst

lim

demag

1. To ensure long term reliability under heavy over-load or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration and number of activation cycles.

Table 11. Truth table

Shutdown temperature 150 175 200 °C

Reset temperature 135 °C

Thermal hysteresis 7 15 °C

= 13 V 30 45 75 A

Current limitation

Turn-off output clamp voltage

Output voltage drop

limitation

5V < V

OUT

< 36 V 75 A

=2A; VIN=0V;

L=6mH

=1A;

OUT

Tj = -40 °C...150 °C

- 41 V

- 48 V

50 mV

- 55 V

Conditions Input Output Sense

Normal operation

Over-temperature

Under-voltage

Over-voltage

Short circuit to GND

Short circuit to V

L H

L H H

L H

L L

L L L

H H

Nominal

SENSEH

j<TTSD

j>TTSD

< Nominal

0 0

) V

SENSEH

Negative output voltage clamp L L 0

) 0

Doc ID 7767 Rev 5 11/26

Page 12

Electrical specifications VND920

Table 12. Electrical transient requirements

ISO T/R

Test level

7637/1

Test pulse

1- 25V

2 + 25V

3a - 25V

3b + 25V

4- 4V

5+ 26.5V

1. All functions of the device are performed as designed after exposure to disturbance.

2. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.

I II III IV Delays and impedance

(1)

- 50V

+ 50V

- 50V

+ 50V

- 5V

+ 46.5V

(1)

(2)

- 75V

+ 75V

- 100V

+ 75V

(1)

- 6V

+ 66.5V

(1)

(2)

- 100V

+ 100V

- 150V

+ 100V

- 7V

+ 86.5V

(1)

(2)

2ms, 10Ω

0.2ms, 10Ω

0.1µs, 50Ω

100ms, 0.01Ω

400ms, 2Ω

Figure 4. Switching characteristics

OUT

90%

OUT

/dt

(off)

SENSE

OUT

80%

/dt

(on)

90%

10%

d(on)

DSENSE

INPUT

12/26 Doc ID 7767 Rev 5

d(off)

Page 13

VND920 Electrical specifications

Figure 5. I

OUT/ISENSE

6500

6000

5500

5000

4500

4000

3500

3000

OUT/ISENSE

versus I

OUT

max.Tj=-40°C

max.Tj=25...150°C

min.Tj=25...150°C

typical value

min.Tj=-40°C

02468101214161820222426283032

(A)

OUT

Doc ID 7767 Rev 5 13/26

Page 14

Electrical specifications VND920

Figure 6. Waveforms

NORMAL OPERATION

INPUT

LOAD CURRENT

SENSE

UNDERVOLTAGE

INPUT

LOAD CURRENT

SENSE

INPUT LOAD CURRENT SENSE

USD

VCC > V

USD

USDhyst

OVERVOLTAGE

OVhyst

INPUT

LOAD CURRENT LOAD VOLTAGE SENSE

INPUT

LOAD VOLTAGE LOAD CURRENT SENSE

INPUT

LOAD CURRENT

SENSE

SHORT TO GROUND

SHORT TO V

<Nominal

TSD

OVERTEMPERATURE

<Nominal

SENSE

SENSEH

SENSE

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Page 15

VND920 Electrical specifications

2.4 Electrical characteristics curves

Figure 7. Off-state output current Figure 8. High-level input current

IL(off1) (uA)

-50 -25 0 2 5 50 75 100 125 150 175

Tc (°C)

Iih (uA)

4.5

3.5

2.5

1.5

0.5

Vin=3.25V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 9. Input clamp voltage Figure 10. Turn-on voltage slope

Vicl (V)

9.5

8.5

7.5

6.5

5.5

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

dVout/dt(on) (V/ms)

700

650

600

550

500

450

400

350

300

250

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

Rl=1.3Ohm

Tc (ºC)

Figure 11. Over-voltage shutdown Figure 12. Turn-off voltage slope

Vov (V)

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Doc ID 7767 Rev 5 15/26

dVout/dt(off) (V/ms)

550

500

450

400

350

300

250

200

150

100

Vcc=13V

Rl=1.3Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Page 16

Electrical specifications VND920

Figure 13. I

Ilim (A)

100

-50 -25 0 25 50 75 100 125 150 175

vs T

LIM

Vcc=13V

case

Tc (°C)

Figure 14. On-state resistance vs V

Ron (mOhm)

5 10152025303540

Tc= 150ºC

Tc= 25ºC

Tc= - 40ºC

Vcc (V)

Figure 15. Input high-level Figure 16. Input hysteresis voltage

Vih (V)

3.6

3.4

3.2

2.8

2.6

2.4

2.2

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vhyst (V)

1.5

1.4

1.3

1.2

1.1

0.9

0.8

0.7

0.6

0.5

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 17. On-state resistance vs Tcase Figure 18. Input low-level

Ron (mOhm)

-50 -25 0 25 50 75 100 12 5 150 175

Iout=10A

Vcc=8V; 36V

Tc (ºC)

16/26 Doc ID 7767 Rev 5

Vil (V)

2.6

2.4

2.2

1.8

1.6

1.4

1.2

-50 -25 0 2 5 50 75 100 125 150 175

Tc (°C)

Page 17

VND920 Application information

3 Application information

Figure 19. Application schematic

+5V

prot

INPUT1

C. SENSE 1

INPUT2

CC1

CC2

OUTPUT1

μC

SENSE1,2

prot

C. SENSE 2

GND1

GND

GND2

OUTPUT2

GND

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (R

This can be used with any type of load.

The following is an indication on how to dimension the R

1. R

2. R

where - I maximum rating section of the device datasheet.

≤ 600 mV / (I

GND

≥ (-VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

S(on)max

GND

)

GND

only)

resistor.

GND

Power Dissipation in R

= (-VCC)2/ R

GND

(when V

< 0: during reverse battery situations) is:

This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I

S(on)max

becomes the sum of the

maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the R

will produce a shift (I

GND

S(on)max

* R

) in the input thresholds and the status output

GND

values. This shift will vary depending on how many devices are ON in the case of several high-side drivers sharing the same R

GND

If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).

Doc ID 7767 Rev 5 17/26

Page 18

Application information VND920

3.1.2 Solution 2: diode (D

A resistor (R

= 1 kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (≈600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.

Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating.

Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the V

max DC rating. The same applies if the device is subject to transients on the VCC line

that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (R prevent the microcontroller I/O pins to latch-up.

if the device drives an

GND

prot

) in line to

The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.

-V

CCpeak/Ilatchup

≤ R

prot

≤ (V

OHµC-VIH-VGND

) / I

IHmax

Calculation example:

For V

CCpeak

5kΩ ≤ R

Recommended values: R

= -100V and I

≤ 65 kΩ.

prot

latchup

=10kΩ .

prot

≥ 20 mA; V

OHµC

≥ 4.5 V

18/26 Doc ID 7767 Rev 5

Page 19

VND920 Application information

3.4 Maximum demagnetization energy (VCC = 13.5V)

Figure 20. Maximum turn-off current versus inductance

LMAX (A)

100

0.01 0.1 1 10 100 L(mH)

A: T

B: T

C: T

,

= 150°C single pulse

jstart

= 100°C repetitive pulse

jstart

= 125°C repetitive pulse

jstart

'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ

*$3*&)7

Note: Values are generated with R

demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

=0 Ω.In case of repetitive pulses, T

(at beginning of each

jstart

Doc ID 7767 Rev 5 19/26

Page 20

Package and PCB thermal data VND920

4 Package and PCB thermal data

4.1 SO-28 thermal data

Figure 21. SO-28 PC board

Note: Layout condition of R

and Zth measurements (PCB FR4 area = 58 mm x 58 mm,

PCB thickness = 2 mm, Cu thickness = 35 µm, Copper areas: 0.5 cm

Table 13. Thermal calculation according to the PCB heatsink area

Chip 1 Chip 2 T

ON OFF R

OFF ON R

ON ON R

ON ON (R

jchip1

thAxPdchip1+Tamb

thCxPdchip2+Tamb

x(P

thB

dchip1+Pdchip2

thAxPdchip1

= Thermal resistance Junction to Ambient with one chip ON

thA

= Thermal resistance Junction to Ambient with both chips ON and P

thB

= Mutual thermal resistance

thC

)+R

)+T

amb

thCxPdchip2+Tamb(RthAxPdchip2

thCxPdchip1+Tamb

thAxPdchip2+Tamb

x(P

thB

jchip2

dchip1+Pdchip2

)+R

thCxPdchip1+TambPdchip1

)+T

, 3 cm2, 6 cm2).

amb

dchip1=Pdchip2

Note

dchip1=Pdchip2

≠ P

dchip2

20/26 Doc ID 7767 Rev 5

Page 21

VND920 Package and PCB thermal data

Figure 22. R

RTHj_am b

(°C/W)

01234567

vs PCB copper area in open box free air condition

thj-amb

PCB Cu heats ink area (cm ^2)/island

thA

thB

thC

Figure 23. Thermal impedance junction ambient single pulse

Zth(°C /W )

100

0.1

0.01

0.0001 0.001 0.01 0.1 1 10 100 1000

time(s)

0,5 cm ^2/island

3 cm ^2/island

6 cm ^2/island

One channel ON

Tw o channels ON

Doc ID 7767 Rev 5 21/26

Page 22

Package and PCB thermal data VND920

Equation 1pulse calculation formula

where

THδ

RTHδ Z

δ tpT⁄=

THtp

1 δ–()+⋅=

Figure 24. Thermal fitting model of a double channel HSD in SO-28

Tj_1

Pd1

Tj_2

Table 14. Thermal parameters

C1 C2

Pd2

C3 C4

R3R1 R6R5R2

T_amb

C5 C6C2

Area/island (cm2)0.56

R1 (°C/W) 0.02

R2 (°C/W) 0.1

R3 (°C/W) 2.2

R4 (°C/W) 11

R5 (°C/W) 15

R6 (°C/W) 30 13

C1 (W.s/°C) 0.0015

C2 (W.s/°C) 7.00E - 03

C3 (W.s/°C) 1.50E - 02

C4 (W.s/°C) 0.2

C5 (W.s/°C) 1.5

C6 (W.s/°C) 5 8

22/26 Doc ID 7767 Rev 5

Page 23

VND920 Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

is an ST trademark.

Figure 25. SO-28 package dimensions

Table 15. SO-28 mechanical data

Millimeters

Symbol

Min. Typ. Max.

A 2.65

a1 0.10 0.30

b 0.35 0.49

b1 0.23 0.32

C0.50

c1 45° (typ.)

D 17.7 18.1

E 10.00 10.65

e1.27

e3 16.51

F 7.40 7.60

L 0.40 1.27

S 8° (max.)

Doc ID 7767 Rev 5 23/26

Page 24

Package and packing information VND920

5.2 SO-28 packing information

Figure 26. SO-28 tube shipment (no suffix)

Base Q.ty 28 Bulk Q.ty 700 Tube length (± 0.5) 532 A 3.5

Figure 27. SO-28 tape and reel shipment (suffix “TR”)

B 13.8 C (± 0.1) 0.6

All dimensions are in mm.

Reel dimensions

Base Q.ty 1000 Bulk Q.ty 1000 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 16.4 N (min) 60 T (max) 22.4

Tape dimensions

According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986

Tape width W 16 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 12 Hole Diameter D (± 0.1/-0) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.05) 7.5 Compartment Depth K (max) 6.5 Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

24/26 Doc ID 7767 Rev 5

500mm min

Empty components pockets saled with cover tape.

User direction of feed

Start

No componentsNo components Components

500mm min

Page 25

VND920 Revision history

6 Revision history

Table 16. Document revision history

Date Revision Changes

07-Jul-2004 1 Initial release.

Minor changes. Current and voltage convention update (page 2). Configuration diagram (top view) and suggested connections for

09-Sep-2004 2

03-May-2006 3 Suggested connections for unused and n.c.pins correction.

17-Dec-2008 4

unused and n.c. pins insertion (page 2). 6 cm2 Cu condition insertion in thermal data table (page 3).

- output diode section update (page 4).

Revision history table insertion (page 34). Disclaimers update (page 35).

Document reformatted and restructured. Added content, list of figures and tables.

Added ECOPACK

packages information.

28-Feb-2011 5

Updated following figures: – Figure 13: ILIM vs Tcase – Figure 22: Rthj-amb vs PCB copper area in open box free air

condition

Doc ID 7767 Rev 5 25/26

Page 26

VND920

Please Read Carefully:

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26/26 Doc ID 7767 Rev 5