Page 1
Features
Type R
VND830PEP-E 60mΩ
1. Per each channel.
DS(on)
(1)
I
6A
OUT
(1)
V
CC
36V
VND830PEP-E
Double channel high side driver
■ CMOS compatible inputs
■ Open drain status outputs
■ On-state open load detection
■ Off-state open load detection
■ Shorted load protection
■ Undervoltage and overvoltage shutdown
■ Protection against loss of ground
■ Very low standby current
■ Reverse battery protection (see Application
schematic on page 16)
■ In compliance with the 2002/95/EC european
directive
Table 1. Device summary
PowerSSO-24
Description
The VND830PEP-E is a monolithic device
designed in STMicroelectronics VIPower™ M0-3
Technology, intended for driving any kind of load
with one side connected to ground.
Active V
against low energy spikes (see ISO7637 transient
compatibility table).
Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload. The device detects open
load condition both in on and off-state. Output
shorted to V
automatically turns off in case of ground pin
disconnection.
pin voltage clamp protects the device
CC
is detected in the off-state. Device
CC
Order codes
Package
Tube Tape and reel
July 2009 Doc ID 10826 Rev 5 1/25
PowerSSO-24 VND830PEP-E VND830PEPTR-E
www.st.com
1
Page 2
Contents VND830PEP-E
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16
3.1.2 Solution 2: a diode (D
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
) in the ground line . . . . . . . . . . . . . . . . . . . . 17
GND
3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/25 Doc ID 10826 Rev 5
Page 3
VND830PEP-E List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Switching (V
Table 7. V
- output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
Table 8. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 9. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 10. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 11. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 13. Electrical transient requirements on V
Table 14. Electrical transient requirements on V
Table 15. Electrical transient requirements on V
Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 17. PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
= 13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
pin (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
pin (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
pin (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
Doc ID 10826 Rev 5 3/25
Page 4
List of figures VND830PEP-E
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Open-load status timing (with external pull-up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Over temperature status timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 20. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 27. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 29. Rthj-amb vs PCB copper area in open box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 20
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 20
Figure 32. PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4/25 Doc ID 10826 Rev 5
Page 5
VND830PEP-E Block diagram and pin description
1 Block diagram and pin description
Figure 1. Block diagram
Figure 2. Configuration diagram (top view)
V
CC
GND
NC
INPUT2
NC
INPUT1
NC
C.SENSE1
NC
C.SENSE2
NC
V
CC
Table 2. Suggested connections for unused and not connected pins
Connection / pin Current sense N.C. Output Input
Floating X X X
To ground
Through 1KΩ
resistor
X
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
TAB = V
CC
Through 10KΩ
resistor
Doc ID 10826 Rev 5 5/25
Page 6
Electrical specifications VND830PEP-E
2 Electrical specifications
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
DC supply voltage 41 V
CC
Reverse DC supply voltage - 0.3 V
CC
DC reverse ground pin current - 200 mA
GND
DC output current Internally limited A
Reverse DC output current - 6 A
OUT
DC input current +/- 10 mA
I
IN
DC status current +/- 10 mA
stat
- V
- I
-I
V
I
OUT
I
Electrostatic discharge (human body model:R=1.5KΩ; C=100pF)
– Input
V
ESD
– Status
– Output
–V
CC
P
T
Power dissipation TC = 25°C 54 W
tot
Junction operating temperature Internally limited °C
T
j
T
Case operating temperature - 40 to 150 °C
c
Storage temperature - 55 to 150 °C
stg
2.2 Thermal data
4000
4000
5000
5000
V
V
V
V
Table 4. Thermal data (per island)
Symbol Parameter Value Unit
R
thj-case
R
thj-amb
1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick) connected
to all V
2. When mounted on a standard single-sided FR-4 board with 8cm2 of Cu (at least 35µm thick) connected to
all V
Thermal resistance junction-case (max) 2.3 °C/W
Thermal resistance junction-ambient (one chip ON) (max) 57
pins.
CC
pins.
CC
6/25 Doc ID 10826 Rev 5
(1)
42
(2)
°C/W
Page 7
VND830PEP-E Electrical specifications
2.3 Electrical characteristics
Note: V
Values specified in this section are for 8V < V
< 36V; -40°C < Tj < 150°C, unless
CC
otherwise stated.
Figure 3. Current and voltage conventions
= V
Fn
Table 5. Power output
Symbol Parameter Test conditions Min. Typ. Max. Unit
CCn
- V
during reverse battery condition.
OUTn
V
V
V
R
I
L(off1)
I
L(off2)
I
L(off3)
I
L(off4)
Operating supply voltage 5.5 13 36 V
CC
Undervoltage shutdown 3 4 5.5 V
USD
Overvoltage shutdown 36 V
OV
I
= 2A; Tj = 25°C
On-state resistance
ON
I
Supply current
S
Off-state output current V
Off-state output current V
Off-state output current
Off-state output current
OUT
= 2A; Tj = 125°C
I
OUT
Off-state; V
= V
V
IN
OUT
Off-state; V
= V
V
IN
OUT
On-state; V
= 0A
I
OUT
= V
IN
OUT
= 0V; V
IN
V
= V
IN
OUT
Tj = 125°C
V
= V
IN
OUT
Tj = 25°C
= 13V;
CC
= 0V
= 13V;
CC
= 0V; Tj = 25°C
= 13V; V
CC
IN
= 5V;
12
12
= 0V 0 50 µA
= 3.5V -75 0 µA
OUT
= 0V; V
= 0V; V
CC
CC
= 13V;
= 13V;
5
60
120mΩmΩ
µA
40
µA
25
mA
7
5µA
3µA
Doc ID 10826 Rev 5 7/25
Page 8
Electrical specifications VND830PEP-E
Table 6. Switching (V
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
dV
OUT
dV
OUT
Table 7. VCC - output diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
Turn-on delay time
Turn-off delay time
/dt
Turn-on voltage slope
(on)
/dt
Turn-off voltage slope
(off)
CC
= 13V)
R
= 6.5Ω from VIN rising
L
edge to V
= 6.5Ω from VIN falling
R
L
edge to V
= 6.5Ω from V
R
L
V
= 10.4V
OUT
R
= 6.5Ω from V
L
to V
OUT
OUT
OUT
= 1.3V
= 1.3V
= 11.7V
OUT
OUT
= 1.3V to
= 11.7V
-30 -µs
-30 -µs
See
-
-
Figure 14
See
Figure 13
-V/µs
-V/µs
V
F
Table 8. Status pin
Forward on voltage - I
= 1.3A; Tj = 150°C - - 0.6 V
OUT
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
STAT
I
LSTAT
C
STAT
V
SCL
Table 9. Logic inputs
Status low output voltage
= 1.6 mA 0.5 V
I
STAT
Status leakage current Normal operation; V
Status pin input
capacitance
Status clamp voltage
Normal Operation; V
I
= 1mA
STAT
= - 1mA
I
STAT
= 5V 10 µA
STAT
= 5V 100 pF
STAT
66.8
-0.7
8V
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
I
V
I
I(hyst)
Input low level 1.25 V
IL
Low level input current V
IL
Input high level 3.25 V
IH
High level input current V
IH
= 1.25V 1 µA
IN
= 3.25V 10 µA
IN
Input hysteresis voltage 0.5 V
Input clamp voltage
ICL
I
IN
I
IN
= 1mA
= -1mA
66.8
- 0.7
8V
V
V
Table 10. Protections
Symbol Parameter Test conditions Min. Typ. Max. Unit
T
Shutdown temperature 150 175 200 °C
TSD
Reset temperature 135 °C
T
R
(1)
8/25 Doc ID 10826 Rev 5
Page 9
VND830PEP-E Electrical specifications
Table 10. Protections
(1)
(continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
T
t
SDL
I
V
demag
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Table 11. Open-load detection
Thermal hysteresis 7 15 °C
hyst
Status delay in overload
conditions
Current limitation
lim
Turn-off output clamp voltage I
> T
T
j
TSD
5.5V < V
= 2A; L = 6mH
OUT
CC
< 36V
691515A
-41V
V
CC
CC
-48V
20 µs
-
CC
55
A
V
Symbol Parameter Test conditions Min. Typ. Max. Unit
IOL
t
DOL(on)
Open-load on-state
detection threshold
Open-load on-state
detection delay
V
= 5V 50 100 200 mA
IN
= 0A 200 µs
I
OUT
Open-load off-state
VOL
voltage detection
V
= 0V 1.5 2.5 3.5 V
IN
threshold
Open-load detection
t
DOL(off)
delay at turn-off
1000 µs
Figure 4. Open-load status timing (with external pull-up)
Doc ID 10826 Rev 5 9/25
Page 10
Electrical specifications VND830PEP-E
Figure 5. Over temperature status timing
Figure 6. Switching time waveforms
Table 12. Truth table
Conditions Inputn Outputn Statusn
Normal Operation
L
H
L
Current Limitation
H
H
Over temperature
Undervoltage
L
H
L
H
10/25 Doc ID 10826 Rev 5
L
H
L
X
X
L
L
L
L
H
H
H
(Tj < TTSD) H
(Tj > TTSD) L
H
L
X
X
Page 11
VND830PEP-E Electrical specifications
Table 12. Truth table (continued)
Conditions Inputn Outputn Statusn
Overvoltage
Output voltage > V
Output current < I
Table 13. Electrical transient requirements on VCC pin (part 1/3)
OLn
OLn
ISO T/R
L
H
L
H
L
H
Test level
L
L
H
H
L
H
7637/1
Test pulse
I II III IV Delays and impedance
1 - 25V - 50V - 75V - 100V 2ms, 10Ω
2 + 25V + 50V + 75V + 100V 0.2ms, 10Ω
3a - 25V - 50V - 100V - 150V 0.1µs, 50Ω
3b + 25V + 50V + 75V + 100V 0.1µs, 50Ω
4 - 4V - 5V - 6V - 7V 100ms, 0.01Ω
5 + 26.5V + 46.5V + 66.5V + 86.5V 400ms, 2Ω
Table 14. Electrical transient requirements on VCC pin (part 2/3)
H
H
L
H
H
L
ISO T/R
Test lev el
7637/1
Test pulse
IIIIIIIV
1C C C C
2C C C C
3a C C C C
3b C C C C
4C C C C
5C E E E
Table 15. Electrical transient requirements on VCC pin (part 3/3)
Class Contents
C
E
All functions of the device are performed as designed after exposure to
disturbance.
One or more functions of the device is not performed as designed after exposure
and cannot be returned to proper operation without replacing the device.
Doc ID 10826 Rev 5 11/25
Page 12
Electrical specifications VND830PEP-E
Figure 7. Waveforms
12/25 Doc ID 10826 Rev 5
Page 13
VND830PEP-E Electrical specifications
2.4 Electrical characteristics curves
Figure 8. Off-state output current Figure 9. High level input current
Figure 10. Input clamp voltage Figure 11. Status leakage current
IL(off1) (µA)
2.5
2.25
1.75
1.5
1.25
0.75
0.5
0.25
Vcc=36V
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Vicl (V)
8
7.8
7.6
7.4
7.2
6.8
6.6
6.4
6.2
Iin=1mA
7
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Iih (µ A)
5
4.5
3.5
2.5
1.5
0.5
Vin=3.25V
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Ilst at (µA)
0.1
0.09
0.08
Vstat=5V
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Figure 12. Status low output voltage Figure 13. Status clamp voltage
Vsta t ( V)
0.8
0.7
Istat=1.6mA
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150 175
Vscl (V)
8
7.8
7.6
Istat=1mA
7.4
7.2
7
6.8
6.6
6.4
6.2
6
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)
Doc ID 10826 Rev 5 13/25
Tc (° C)
Page 14
Electrical specifications VND830PEP-E
Figure 14. Turn-on voltage slope Figure 15. Turn-off voltage slope
dVout/dt(on) (V/ms)
1000
900
800
700
600
500
400
300
200
100
Vcc=13V
Rl=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Figure 16. On-state resistance vs Tcase Figure 17. On-state resistance vs V
Ron (mOh m)
160
140
120
100
80
60
40
20
0
-50 -25 0 25 50 75 100 125 150 175
Iout=2A
Vcc=8V; 13V & 36V
Tc ( ° C)
dVout/dt(off) (V/ms)
500
450
400
350
300
250
200
150
100
Vcc=13V
Rl=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Ron (mOh m)
120
110
100
90
80
70
60
50
40
30
20
10
0
5 10152025 303540
Tc= 15 0° C
Tc=25°C
Tc= -4 0°C
Iout=2A
Vcc ( V)
CC
Figure 18. I
LIM
vs T
case
Ilim ( A)
20
18
16
14
12
10
Vcc=13V
8
6
4
2
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C)
14/25 Doc ID 10826 Rev 5
Figure 19. Input high level
Vih (V)
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C)
Page 15
VND830PEP-E Electrical specifications
Figure 20. Open-load on-state detection
threshold
Iol (mA)
140
135
130
125
120
115
110
105
100
95
90
Vcc=13V
Vin=5V
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Figure 22. Input hysteresis voltage Figure 23. Input low level
Vhyst (V)
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C)
Figure 21. Open-load off-state detection
threshold
Vol ( V)
5
4.5
4
3.5
3
2.5
2
1.5
0.5
0
Vil (V)
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
Vin=0V
1
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C)
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C)
Figure 24. Overvoltage shutdown Figure 25. Undervoltage shutdown
Vov (V)
50
48
46
44
42
40
38
36
34
32
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C)
Vusd (V)
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C)
Doc ID 10826 Rev 5 15/25
Page 16
Application information VND830PEP-E
3 Application information
Figure 26. Application schematic
3.1 GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1 Solution 1: a resistor in the ground line (R
This can be used with any type of load.
The following show how to dimension the R
1. R
2. R
where - I
maximum rating section of the device datasheet.
Power dissipation in R
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
Please note that, if the microprocessor ground is not shared by the device ground, then the
R
GND
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
≤ 600mV / (I
GND
≥ ( - VCC) / (- I
GND
is the DC reverse ground pin current and can be found in the absolute
GND
P
= (- VCC)2/ R
D
GND
will produce a shift (I
S(on)max
GND
(when V
GND
S(on)max
)
)
< 0 during reverse battery situations) is:
CC
* R
GND
.
GND
resistor:
GND
) in the input thresholds and the status output
GND
S(on)max
only)
becomes the sum of the
16/25 Doc ID 10826 Rev 5
Page 17
VND830PEP-E Application information
If the calculated power dissipation leads to a large resistor, or several devices have to share
the same resistor, then ST suggests using solution 2 below.
3.1.2 Solution 2: a diode (D
A resistor (R
= 1kΩ) should be inserted in parallel to D
GND
) in the ground line
GND
inductive load. This small signal diode can be safely shared amongst several different HSD.
Also in this case, the presence of the ground network will produce a shift ( 600mV) in the
input threshold and the status output values if the microprocessor ground is not common
with the device ground. This shift will not vary if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the absolute maximum
rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.
3.2 Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V
maximum DC rating. The same applies if the device is subject to transients on the VCC
CC
line that are greater than those shown in the ISO T/R 7637/1 table.
3.3 MCU I/O protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the µC I/O pins from latching up.
if the device will be driving an
GND
≈
) in line to
prot
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os:
- V
CCpeak
/ I
latchup
≤ R
prot
≤ (V
OHμC
Example
For the following conditions:
V
CCpeak
I
latchup
V
OHμC
5kΩ ≤ R
= - 100V
≥ 20mA
≥ 4.5V
≤ 65kΩ.
prot
Recommended values are:
R
= 10kΩ
prot
3.4 Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (V
microprocessor.
The external resistor has to be selected according to the following requirements:
- V
- V
IH
) / I
GND
) like the +5V line used to supply the
PU
IHmax
Doc ID 10826 Rev 5 17/25
Page 18
Application information VND830PEP-E
1. no false open-load indication when load is connected: in this case we have to avoid
V
to be higher than V
OUT
V
OUT
= (V
/ (RL+RPU)) RL < V
PU
2. no misdetection when load is disconnected: in this case the V
V
R
Because I
up resistor R
standby. The values of V
; this results in the following condition
OLmax
PU
< (V
– V
PU
may significantly increase if V
s(OFF)
should be connected to a supply that is switched off when the module is in
PU
OLmax
) / I
OLmin
; this results in the following condition
Olmin
L(off2)
, V
.
OLmax
Olmin
and I
.
is pulled high (up to several mA), the pull-
out
are available in the electrical
L(off2)
has to be higher than
OUT
characteristics section.
Figure 27. Open-load detection in off-state
18/25 Doc ID 10826 Rev 5
Page 19
VND830PEP-E Package and PC board thermal data
4 Package and PC board thermal data
4.1 PowerSSO-24 thermal data
Figure 28. PowerSSO-24 PC board
Note: Layout condition of Rth and Zth measurements (PCB FR4 area= 78mm x 78mm, PCB
thickness=2mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm
Figure 29.
RTHj_a mb(°C/W )
R
vs PCB copper area in open box
thj-amb
60
55
50
45
40
0123456789
2
).
PCB Cu heatsink are a (cm^2)
Doc ID 10826 Rev 5 19/25
Page 20
Package and PC board thermal data VND830PEP-E
Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse
ZTH (°C/W)
100
Footprint
2
8 cm
10
1
0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24
Equation 1
Z
THδ
: pulse calculation formula
RTHδ Z
THtp
1 δ–()+⋅=
where δ = tP/T
20/25 Doc ID 10826 Rev 5
Page 21
VND830PEP-E Package and PC board thermal data
Table 16. Thermal parameters
Area/island (cm2)Footprint8
R1 = R7 (°C/W) 0.1
R2 = R8 (°C/W) 0.9
R3 (°C/W) 1
R4 (°C/W) 4
R5 (°C/W) 13.5
R6 (°C/W) 37 22
C1 = C7 (W.s/°C) 0.0006
C2 = C8 (W.s/°C) 0.0025
C3 (W.s/°C) 0.025
C4 (W.s/°C) 0.08
C5 (W.s/°C) 0.7
C6 (W.s/°C) 3 5
Doc ID 10826 Rev 5 21/25
Page 22
Package information VND830PEP-E
5 Package information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
®
is an ST trademark.
5.2 PowerSSO-24 mechanical data
Figure 32. PowerSSO-24 package dimensions
.
22/25 Doc ID 10826 Rev 5
Page 23
VND830PEP-E Package information
Table 17. PowerSSO-24 mechanical data
Millimeters
Symbol
Min. Typ. Max.
A 2.45
A2 2.15 2.35
a1 0 0.10
b0.33 0.51
c0.23 0.32
D 10.10 10.50
E7.40 7.60
e0.8
e3 8.8
F2.3
G 0.1
G1 0.06
H 10.1 10.5
h 0.4
k0° 8°
L0.55 0.85
N 10º
X4.1 4.7
Y6.5 7.1
Doc ID 10826 Rev 5 23/25
Page 24
Revision history VND830PEP-E
6 Revision history
Table 18. Document revision history
Date Revision Changes
04-Oct-2004 1 Initial release.
15-Nov-2004 2
Mechanical data updating.
PowerSSO-24 thermal characteristics insertion
27-Nov-2004 3 PC board copper area correction.
12-Dec-2005 4
Electrical characteristics insertion.
Absolute maximum ratings modification.
Updated Figure 17: PowerSSO-24 mechanical data:
– Deleted A (min) value
01-Jul-2009 5
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Inserted F and k rows
24/25 Doc ID 10826 Rev 5
Page 25
VND830PEP-E
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Doc ID 10826 Rev 5 25/25
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