Datasheet VND830LSP-E Datasheet (ST)

Features

Typ e R

DS(on)

VND830LSP-E 60 mΩ 18 A

1. Per channel

■ ECOPACK

■ Automotive Grade: compliance with AEC

®

: lead free and RoHS compliant

guidelines

■ Very low standby current

■ CMOS compatible input

■ On-state open-load detection

■ Off-state open-load detection

■ Thermal shutdown protection and diagnosis

■ Undervoltage shutdown

■ Overvoltage clamp

■ Output stuck to V

■ Load current limitation

■ Reverse battery protection

■ Electrostatic discharge protection

detection

CC

I

OUT

(1)

V

36 V

CC

(1)

VND830LSP-E

Double channel high-side driver

Description

The VND830LSP-E is a monolithic device made
using STMicroelectronics™ VIPower™ M0-3
technology. It is intended for driving any kind of
load with one side connected to ground. Active
V

pin voltage clamp protects the device against

CC

low energy spikes (see ISO7637 transient
compatibility table).

Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload.

The device detects open-load condition both in
on-state and off-state. The open-load threshold is
aimed at detecting the 5 W/12 V standard bulb as
an open-load fault in the on-state.

Device automatically turns off in case of ground
pin disconnection.

10

1

PowerSO-10

Table 1. Device summary

Order codes

Package

Tube Tape and reel

Power-SO-10™ VND830LSP-E VND830LSPTR-E

February 2011 Doc ID 10882 Rev 3 1/27

www.st.com

1

Contents VND830LSP-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16

3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 16

3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 17

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.5 PowerSO-10 maximum demagnetization energy
(V

= 13.5 V) 19

CC

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 PowerSO-10 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2 PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3 PowerSO-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/27 Doc ID 10882 Rev 3

VND830LSP-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7. V

Table 8. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 9. Switching (V

Table 10. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 11. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 13. Electrical transient requirements on V
Table 14. Electrical transient requirements on V
Table 15. Electrical transient requirements on V

Table 16. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 17. PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

- output diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

CC

= 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

pin (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CC

pin (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CC

pin (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CC

Doc ID 10882 Rev 3 3/27

List of figures VND830LSP-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11. Status low output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12. Satus clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 13. On-state resistance vs T
Figure 14. On-state resistance vs V

Figure 15. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 16. Open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 17. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 19. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 20. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 23. I

LIM

vs T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

case

Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 25. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 26. Maximum turn- off current versus load inductance
Figure 27. PowerSO-10 PC board

Figure 28. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 29. PowerSO-10 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . 21

Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10 . . . . . . . . . . . . . . . . . . . . 21

Figure 31. PowerSO-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 32. PowerSO-10 suggested pad layout and tube shipment (no suffix). . . . . . . . . . . . . . . . . . . 25

Figure 33. Tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CC

(1)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4/27 Doc ID 10882 Rev 3

VND830LSP-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

cc

V

GND

INPUT1

STATUS1

INPUT2

STATUS2

cc

CLAMP

OVER TEMP. 1

OVER TEMP. 2

LOGIC

OVERVO LTAGE

UNDERVOLTAGE

CLAMP 1

DRIVER 1

CURRENT LIMITER 1

OPEN LOAD ON 1

OPEN LOAD OFF 1

CLAMP 2

DRIVER 2

CURRENT LIMITER 2

OPEN LOAD ON 2

OPEN LOAD OFF 2

OUTPUT1

OUTPUT2

Figure 2. Configuration diagram (top view)

GROUND
INPUT 1

STATUS 1
STAT US 2
INPUT 2

6
7

8
9

10

5
4
3

2

1

11

V

CC

OUTPUT 1
OUTPUT 1
N.C.
OUTPUT 2
OUTPUT 2

PowerSO-10

Table 2. Suggested connections for unused and not connected pins

Connection / pin Status N.C. Output Input

Floating X X X X

To ground X

Through 10KΩ

resistor

Doc ID 10882 Rev 3 5/27

Electrical specifications VND830LSP-E

2 Electrical specifications

Figure 3. Current and voltage conventions

I

S

V

CC

I

IN1

V

IN1

V

STAT1

I

STAT1

I

IN2

V

IN2

I

STAT2

V

STAT2

INPUT1

STATUS 1

INPUT2

STATUS 2

GND

OUTPUT1

OUTPUT2

I

GND

I

OUT1

I

OUT2

V

OUT2

(1)

V

F1

V

OUT1

V

CC

1. VFn = V

CCn

- V

during reverse battery condition.

OUTn

2.1 Absolute maximum ratings

Stressing the device above the rating listed in Ta bl e 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics sure program and other relevant quality
document.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

-V

- I

I

-I

I

V

CC

GND

OUT

OUT

I

IN

STAT

ESD

P

DC supply voltage 41 V

Reverse DC supply voltage -0.3 V

CC

DC reverse ground pin current -200 mA

DC output current Internally limited A

Reverse DC output current -6 A

DC input current +/- 10 mA

CD status current +/- 10 mA

Electrostatic discharge (Human Body Model:
R=1.5KΩ; C=100pF)

– INPUT
–STATUS
–OUTPUT
–V

CC

Power dissipation at Tc=25°C 74 W

tot

4000
4000
5000
5000

V
V
V
V

6/27 Doc ID 10882 Rev 3

VND830LSP-E Electrical specifications

Table 3. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Maximum switching energy

E

T

MAX

T

j

T

c

STG

(L = 0.14 mH; R
T

= 150 °C; IL=14A)

jstart

=0Ω; V

L

=13.5V;

bat

Junction operating temperature Internally limited °C

Case operating temperature -40 to 150 °C

Storage temperature -55 to 150 °C

52 mJ

2.2 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

R

thj-case

R

thj-amb

1. When mounted on a standard single sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick). Horizontal

mounting and no artificial air flow.

2. When mounted on a standard single sided FR-4 board with 6 cm2 of Cu (at least 35 µm thick). Horizontal

mounting and no artificial air flow.

Thermal resistance junction-case 2 °C/W

Thermal resistance junction-ambient 52

(1)

37

(2)

°C/W

Doc ID 10882 Rev 3 7/27

Electrical specifications VND830LSP-E

2.3 Electrical characteristics

Values specified in this section are for 8 V < V

< 36 V; -40 °C < Tj < 150 °C, unless

CC

otherwise specified. (Per each channel).

Table 5. Power output

Symbol Parameter Test conditions Min. Typ. Max. Unit

(1)

V

V

USD

V

R

I

I

L(off1)

I

L(off2)

I

L(off3)

I

L(off4)

Operating supply voltage 5.5 13 36 V

CC

(1)

Undervoltage shutdown 3 4 5.5 V

(1)

Overvoltage shutdown 36 V

OV

I

=2A; Tj=25°C 60 mΩ

On-state resistance

ON

(1)

Supply current

S

Off-state output current

Off-state output current VIN=0V; V

Off-state output current

Off-state output current

OUT

=2A; V

I

OUT

Off-state; V
V

IN=VOUT

Off-state; V
V

IN=VOUT

On-state; V

V

IN=VOUT

= 125 °C

T

j

V

IN=VOUT

=125°C

T

j

V

IN=VOUT

Tj =25°C

8V 120 mΩ

CC >

=13V;

CC

=0V

=13V;

CC

=0V; Tj=25°C

=13V 5 7 mA

CC

=0V; VCC=36V;

=3.5V -75 0 µA

OUT

12 40 µA

12 25 µA

050µA

=0V; VCC=13V;

=0V; VCC=13V;

5µA

3µA

1. Per device.

Table 6. Protection

(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

T

T

V

demag

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related

Tabl e 7. V

Shutdown temperature 150 175 200 °C

TSD

Reset temperature 135 °C

T

R

Thermal hysteresis 7 15 °C

hyst

V

= 13 V 18 23 29 A

I

Current limitation

lim

Turn-off output clamp
voltage

diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

- output diode

CC

CC

5.5 V < V

I

OUT

<36 V 29 A

CC

=2A; L=6mH VCC-41 VCC-48 VCC-55 V

Symbol Parameter Test conditions Min Typ Max Unit

V

Forward on voltage -I

F

= 1.3 A; Tj= 150 °C — — 0.6 V

OUT

8/27 Doc ID 10882 Rev 3

VND830LSP-E Electrical specifications

Table 8. Status pin

Symbol Parameter Test conditions Min Typ Max Unit

V

Status low output voltage I

STAT

I

LSTAT

C

V

Table 9. Switching (VCC=13V)

Status leakage current Normal operation; V

Status pin input

STAT

capacitance

Status clamp voltage

SCL

Symbol Parameter Test conditions Min Typ Max Unit

(dV

(dV

t

d(on)

t

d(off)

OUT

OUT

Turn-on delay time

Turn-on delay time

/dt)onTurn-on voltage slope

/dt)

Turn-off voltage slope

off

= 1.6 mA 0.5 V

STAT

= 5 V 10 mA

STAT

Normal operation; V

I

= 1 mA 6 6.8 8 V

STAT

= -1 mA -0.7 V

I

STAT

=13Ω from VIN rising edge

R

L

to V

R
to V

R
V

R
to V

=1.3V

OUT

=13Ω from VIN falling edge

L

= 11.7 V

OUT

=13Ω from V

L

=10.4V

OUT

=13Ω from V

L

=1.3V

OUT

= 5 V 100 pF

STAT

—30—µs

—30—µs

OUT

OUT

= 1.3 V to

=11.7V

—

—

See

Figure 21

See

Figure 22

—V/µs

—V/µs

Table 10. Open-load detection

Symbol Parameter Test conditions Min Typ Max Unit

Open-load on-state detection

I

OL

threshold

t

T

Table 11. Logic input

Open-load on-state detection delay I

DOL(on)

Openload off-state voltage detection

V

OL

threshold

DOL(off)

Open-load detection delay at turn-off 1000 µs

V

= 5 V 0.6 0.9 1.2 A

IN

= 0 A 200 µs

OUT

VIN= 0 V 1.5 2.5 3.5 V

Symbol Parameter Test conditions Min Typ Max Unit

V

V

V

I

V

I

I(hyst)

Input low level 1.25 V

IL

Low level input current VIN=1.25V 1 µA

IL

Input high level 3.25 V

IH

High level input current VIN= 3.25 V 10 µA

IH

Input hysteresis voltage 0.5 V

I

=1mA 6 6.8 8 V

Input clamp voltage

ICL

IN

I

=-1mA -0.7 V

IN

Doc ID 10882 Rev 3 9/27

Electrical specifications VND830LSP-E

Figure 4. Status timings

OPEN LOAD STATUS TIMING (with external pull-up)

V

> V

OUT

V

INn

V

STATn

t

DOL(off)

Table 12. Truth table

I

< I

OUT

t

DOL(on)

OL

OL

Conditions Input Output Sense

OVER TEMP STATUS TIMING

V

INn

V

STATn

t

SDL

Tj > T

TSD

t

SDL

Normal operation

L

H

L

Current limitation

H
H

Overtemperature

Undervoltage

Overvoltage

Output voltage > V

Output current < I

OL

OL

L

H

L

H

L

H

L

H

L

H

Figure 5. Switching time waveforms

L
H

L
X
X

(Tj<T
(Tj>T

L
L

L
L

L
L

H
H

L
H

TSD

TSD

H
H

H

)H
)L

H
L

X
X

H
H

L
H

H
L

10/27 Doc ID 10882 Rev 3

VND830LSP-E Electrical specifications

Table 13. Electrical transient requirements on VCC pin (part 1)

ISO T/R 7637/1

Test levels

test pulse

I II III IV

1 -25 V -50 V -75 V -100 V 2 ms, 10 Ω

2 +25 V +50 V +75 V +100 V 0.2 ms, 10 Ω

3a -25 V -50 V -100 V -150 V 0.1 µs, 50 Ω

3b +25 V +50 V +75 V +100 V 0.1 µs, 50 Ω

4 -4 V -5 V -6 V -7 V 100 ms, 0.01

5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2

Table 14. Electrical transient requirements on VCC pin (part 2)

ISO T/R 7637/1

Test pulse

I II III IV

Test levels results

1CCCC

2CCCC

3aCCCC

3bCCCC

4CCCC

Delays and
impedance

Ω

Ω

5C E E E

Table 15. Electrical transient requirements on VCC pin (part 3)

Class Contents

C

All functions of the device are performed as designed after exposure to
disturbance.

One or more functions of the device is not performed as designed after exposure

E

to disturbance and cannot be returned to proper operation without replacing the
device.

Doc ID 10882 Rev 3 11/27

Electrical specifications VND830LSP-E

Figure 6. Waveforms

NORMAL OPERATION

INPUT

n

OUTPUT VOLTAGE

STATUS

V

INPUT

n

CC

n

OUTPUT VOLTAGE

STATUS

V

CC

INPUT

n

OUTPUT VOLTAGE

STATUS

n

n

UNDERVOLTAGE

V

USDhyst

V

USD

n

undefined

OVERVOLTAGE

VCC<V

OV

n

V

> V

CC

OV

INPUT

n

OUTPUT VOLTAGE

STATUS

INPUT

n

n

OUTPUT VOLTAGE

STATUS

T

INPUT

n

j

n

OUTPUT CURRENT

STATUS

n

OPEN LOAD with external pull-up

V

> V

n

V

OL

OUT

OL

OPEN LOAD without external pull-up

n

T

TSD

T

R

n

OVERTEMPERATURE

12/27 Doc ID 10882 Rev 3

VND830LSP-E Electrical specifications

2.4 Electrical characteristics curves

Figure 7. Off-state output current Figure 8. High level input current

IL(off1)

1.35

1.2

1.05

0.9

0.75

0.6

0.45

0.3

0.15

0

-50 -25 0 25 50 75 100 125 150 175

Off State
Vcc=13V

Vin=Vout=0V

Tc ( ºC )

Figure 9. Input clamp voltage Figure 10. Status leakage current

Vicl (V)

8

7.75

7.5

7.25

7

6.75

6.5

6.25

6

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Iih (µA)

6

5.25

4.5

3.75

2.25

1.5

0.75

Vin=3.25V

3

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Ilstat (µA)

0.07

0.06

Vstat=5V

0.05

0.04

0.03

0.02

0.01

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Figure 11. Status low output current Figure 12. Satus clamp voltage

Vstat (V)

0.8

0.7

Istat=1.6mA

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Vscl (V)

8

7.75

7.5

7.25

6.75

6.5

6.25

Istat=1mA

7

6

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Doc ID 10882 Rev 3 13/27

Electrical specifications VND830LSP-E

Figure 13. On-state resistance vs T

case

Ron (mOhm)

100

90

80

70

60

50

40

30

20

10

0

Iout=2A

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Figure 15. Open-load on-state detection

threshold

Iol (A)

2

1.75

Vin=5V

1.5

1.25

1

0.75

0.5

0.25

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Figure 14. On-state resistance vs V

CC

Ron (mOhm)

160

140

120

100

80

60

40

20

0

Iout=2A

Tc=150ºC

Tc=25ºC

Tc= -40ºC

0 5 10 15 20 25 30 35 40

Vcc (V)

Figure 16. Open-load off-state detection

threshold

Vol (V)

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

Vin=0V

-50 -25 0 25 50 75 100 125 150 175

Tc (º C)

Figure 17. Input high level Figure 18. Input low level

Vih (V)

4

3.8

3.6

3.4

3.2

3

2.8

2.6

2.4

2.2

2

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Vil (V)

2.25

2.125

2

1.875

1.75

1.625

1.5

1.375

1.25

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

14/27 Doc ID 10882 Rev 3

VND830LSP-E Electrical specifications

Figure 19. Input hysteresis voltage Figure 20. Overvoltage shutdown

Vihyst (V)

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope

dVout/dt(on) (V/ms)

800

700

600

500

400

300

200

100

Vcc=13V

Rl=6.5Ohm

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Figure 23. I

LIM

vs T

case

Ilim (A)

35

32.5

30

27.5

25

22.5

20

17.5

15

12.5

10

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Vov

50

47.5

45

42.5

40

37.5

35

32.5

30

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

dVout/dt(off) (V/ms)

800

700

600

500

400

300

200

100

0

Vcc=13V

Rl=6.5Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc ( ºC )

Doc ID 10882 Rev 3 15/27

Application information VND830LSP-E

3 Application information

Figure 24. Application schematic

+5V

+5V

+5V

μ

R

prot

C

R

prot

R

prot

R

prot

STATUS1

INPUT1

STATUS2

INPUT2

V

CC

D

ld

OUTPUT1

D

OUTPUT2

GND

GND

R

V

GND

GND

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (R

This can be used with any type of load.

The following is an indication on how to dimension the R

1. R

2. R

where -I
maximum rating section of the device’s datasheet.

Power dissipation in R

P

= (-VCC)2/ R

D

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.

≤ 600 mV / I

GND

≥ (-VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

GND

S(on)max

)

GND

(when V

GND

< 0: during reverse battery situations) is:

CC

GND

only)

resistor.

GND

S(on)max

becomes the sum of the

Please note that if the microprocessor ground is not shared by the device ground then the
R

produces a shift (I

GND

S(on)max

16/27 Doc ID 10882 Rev 3

* R

) in the input thresholds and the status output

GND

VND830LSP-E Application information

values. This shift varies depending on how many devices are ON in the case of several
high-side drivers sharing the same R

GND

.

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize solution 2 (see Section 3.1.2).

3.1.2 Solution 2: diode (D

A resistor (R

= 1 kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (∼600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.

Series resistor in INPUT and STATUS lines are also required to prevent that, during battery
voltage transient, the current exceeds the absolute maximum rating.

Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V

max DC rating. The same applies if the device is subject to transients on the VCC line

CC

that are greater than the ones shown in Ta b le 1 3 .

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (R
the microcontroller I/Os pins to latch-up.

if the device drives an

GND

) in line to prevent

prot

The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.

-V

CCpeak/Ilatchup

≤ R

prot

≤ (V

OHµC-VIH-VGND

) / I

Calculation example:

For V

CCpeak

5kΩ ≤ R

= -100 V and I

≤ 65 kΩ.

prot

latchup

≥ 20 mA; V

OHµC

Recommended values:

R

=10 kΩ.

prot

3.4 Open-load detection in off-state

Off-state open-load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (V
microprocessor.

Doc ID 10882 Rev 3 17/27

PU

IHmax

≥ 4.5 V

) like the +5 V line used to supply the

Application information VND830LSP-E

The external resistor has to be selected according to the following requirements:

1. No false open-load indication when load is connected:

in this case we have to avoid V
condition V

=(VPU/(RL+RPU))RL<V

OUT

to be higher than V

OUT

Olmin

; this results in the following

Olmin

.

2. No misdetection when load is disconnected:

in this case the V
condition R

Because I
up resistor R

PU

may significantly increase if V

s(OFF)

should be connected to a supply that is switched OFF when the module is in

PU

standby. The values of V

has to be higher than V

OUT

<(VPU–V

OLmin

OLmax

, V

OLmax

)/I

L(off2)

and I

; this results in the following

OLmax

.

is pulled high (up to several mA), the pull-

OUT

are available in Section 2.3: Electrical

L(off2)

characteristics.

Figure 25. Open-load detection in off-state

V batt. VPU

V

CC

R

PU

INPUT

STATUS

DRIVER

+

LOGIC

+

R

-

VOL

OUT

I

L(off2)

R

L

GROUND

18/27 Doc ID 10882 Rev 3

VND830LSP-E Application information

3.5 PowerSO-10 maximum demagnetization energy
(V

= 13.5 V)

CC

Figure 26. Maximum turn- off current versus load inductance

I

LM AX (A)

100

10

1

0,01 0,1 1 10 100

L( mH)

(1)

A

B

C

A: Single pulse at T

B: Repetitive pulse at T

C: Repetitive pulse at T

jstart

= 150 °C

= 100 °C

jstart

=125°C

jstart

Condition:
V

= 13.5 V

CC

VIN, I

L

1. Values are generated with R

In case of repetitive pulses, T
the temperature specified above for curves B and C.

Demagnetization

=0Ω

L

(at beginning of each demagnetization) of every pulse must not exceed

jstart

Demagnetization

Demagnetization

t

Doc ID 10882 Rev 3 19/27

Package and PCB thermal data VND830LSP-E

4 Package and PCB thermal data

4.1 PowerSO-10 thermal data

Figure 27. PowerSO-10 PC board

1. Layout condition of R

Cu thickness = 35 µm, Copper areas: from minimum pad lay-out to 8 cm2).

Figure 28. R

thj-amb

RTHj_amb (°C/W)

and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm,

th

vs PCB copper area in open box free air condition

(1)

55

50

Tj-Tamb=50°C

45

40

35

30

0246810

PCB Cu heatsink area (cm^2)

20/27 Doc ID 10882 Rev 3

VND830LSP-E Package and PCB thermal data

Figure 29. PowerSO-10 thermal impedance junction ambient single pulse

ZTH (°C/W)

1000

100

10

1

0.1

0.0001 0.001 0.01 0.1 1 10 100 1000

Time (s)

Equation 1

Z

THδ

where

: pulse calculation formula

RTHδ Z

THtp

1 δ–()+⋅=

δ tpT⁄=

0.5 cm

6 cm

2

2

Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10

Tj_1

Pd1

Tj_2

C1

C1 C2

R1

Pd2

C3 C4

R3R1 R6R5R2

R2

R4

T_amb

C5 C6C2

Doc ID 10882 Rev 3 21/27

Package and PCB thermal data VND830LSP-E

Table 16. Thermal parameter

Area/island (cm2) Footprint 6

R1 (°C/ W) 0.15

R2 (°C/ W) 0.8

R3 (°C/ W) 0.7

R4 (°C/ W) 0.8

R5 (°C/ W) 12

R6 (°C/ W) 37 22

C1 (W.s/ °C) 0.0006

C2 (W.s /°C) 2.1E-03

C3 (W.s/ °C) 0.013

C4 (W.s/ °C) 0.3

C5 (W.s/ °C) 0.75

C6 (W.s/ °C) 3 5

22/27 Doc ID 10882 Rev 3

VND830LSP-E Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

5.2 PowerSO-10 mechanical data

Figure 31. PowerSO-10 package dimensions

10

HE

h

A

F

A1

1

eB

0.25

D

= =

D1

= =

E2

DETAIL "A"

B

0.10 A

E

SEATING

PLANE

A

C

B

E4

SEATING

PLANE

A1

DETAIL "A"

L

α

Doc ID 10882 Rev 3 23/27

Package and packing information VND830LSP-E

Table 17. PowerSO-10 mechanical data

Millimeters

Dim.

Min. Typ. Max.

A 3.35 3.65

(1)

A

A1 0 0.10

B 0.40 0.60

(1)

B

C 0.35 0.55

(1)

C

D 9.40 9.60

D1 7.40 7.60

E 9.30 9.50

3.4 3.6

0.37 0.53

0.23 0.32

E2 7.20 7.60

(1)

E2

E4 5.90 6.10

(1)

E4

e1.27

F 1.25 1.35

(1)

F

H 13.80 14.40

(1)

H

h0.50

L 1.20 1.80

(1)

L

α 0° 8°

(1)

α

1. Muar only POA P013P.

7.30 7.50

5.90 6.30

1.20 1.40

13.85 14.35

0.80 1.10

2° 8°

24/27 Doc ID 10882 Rev 3

VND830LSP-E Package and packing information

5.3 PowerSO-10 packing information

Figure 32. PowerSO-10 suggested pad layout and tube shipment (no suffix)

14.6 - 14.9

10.8 - 11

6.30

0.67 - 0.73

1

2

3

9.5
4

5

10

0.54 - 0. 6

9

8

7

1.27

6

C

A

All dimensions are in mm.

Casablanca 50 1000 532 10.4 16.4 0.8

Muar 50 1000 532 4.9 17.2 0.8

Figure 33. Tape and reel shipment (suffix “TR”)

B

Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1)

REEL DIMENSIONS

Base Q.ty 600
Bulk Q.ty 600
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 24.4
N (min) 60
T (max) 30.4

All dimensions are in mm.

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 24
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 11.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Doc ID 10882 Rev 3 25/27

Top

cover

tape

End

500mm min

Empty components pockets
saled with cover tape.

User directio n of feed

Start

No componentsNo components Components

500mm min

Revision history VND830LSP-E

6 Revision history

Table 18. Document revision history

Date Revision Changes

1-Oct-2004 1 Initial release.

19-Jul-2010 2

25-Feb-2011 3

Changed Features list.
Reformatted entire document. No content change.

Updated I
Updated Table 16: Thermal parameter.

value in Features list.

OUT

26/27 Doc ID 10882 Rev 3

VND830LSP-E

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Doc ID 10882 Rev 3 27/27