Datasheet VND5E160AJ-E Datasheet (ST)

Double channel high side driver with analog current sense

Features

Max transient supply voltage V

Operating voltage range V

Max On-state resistance (per ch.) R

Current limitation (typ.) I

Off state supply current I

1. Typical value with all loads connected.

■ General

– Inrush current active management by

power limitation
– Very low stand-by current
– 3.0 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC

european directive
– Very low current sense leakage

■ Diagnostic functions

– Proportional load current sense
– High current sense precision for wide

currents range
– Current sense disable
– Off state openload detection
– Output short to V

detection

CC

– Overload and short to ground (power

limitation) indication
– Thermal shutdown indication

■ Protections

– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss

of V

CC

– Over-temperature shutdown with

autorestart (thermal shutdown)

CC

CC

ON

LIMH

S

4.5 to 28V

41 V

160 mΩ

10 A

(1)

2 µA

VND5E160AJ-E

for automotive applications

PowerSSO-12

– Reverse battery protected (see Application

schematic)

– Electrostatic discharge protection

Application

■ All types of resistive, inductive and capacitive

loads

■ Suitable as LED driver

Description

The VND5E160AJ-E is a single channel high-side
driver manufactured in the ST proprietary
VIPower M0-5 technology and housed in the tiny
PowerSSO-12 package. The VND5E160AJ-E is
designed to drive 12V automotive grounded loads
delivering protection, diagnostics and easy 3V
and 5V CMOS compatible interface with any
microcontroller.

The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, over-temperature shut-off with
auto-restart and over-voltage active clamp. A
dedicated analog current sense pin is associated
with every output channel in order to provide
Ehnanced diagnostic functions including fast
detection of overload and short-circuit to ground
through power limitation indication, over­temperature indication, short-circuit to Vcc
diagnosis and ON & OFF state open load
detection. The current sensing and diagnostic
feedback of the whole device can be disabled by
pulling the CS_DIS pin high to allow sharing of
the external sense resistor with other similar
devices.

March 2008 Rev 2 1/37

www.st.com

37

Contents VND5E160AJ-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24

3.1.1 Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 24

3.1.2 Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 25

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.4.1 Short to VCC and OFF state open load detection . . . . . . . . . . . . . . . . . 27

3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 28

4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/37

VND5E160AJ-E List of tables

List of tables

Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Switching (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9. Current sense (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10. Openload detection (8V<V

Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 13. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 15. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CC

3/37

List of figures VND5E160AJ-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5. Openload Off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Delay response time between rising edge of ouput current and rising edge of current sense

(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Iout/ Isense vs. Iout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14. OFF-State Open Load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15. Short to V
Figure 16. T

evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

J

Figure 17. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 18. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 19. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 20. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 21. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 23. On state resistance vs. T
Figure 24. On state resistance vs. V

Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 26. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 27. I

LIMH

vs. T

Figure 28. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 29. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 30. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 31. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 32. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 33. Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 34. Maximum turn-Off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 28

Figure 35. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 36. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 29

Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 30

Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 30

Figure 39. PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 40. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

case

4/37

VND5E160AJ-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

CC

Signal Clamp

IN 1

IN 2

CS_
DIS

CS1

CS2

Undervoltage

C ontrol & Diagnostic 1

DRIVER

Over

temp .

V

SENSEH

LOGIC

Table 1. Pin function

Name Function

V

CC

Battery connection.

L imi tation

Current

Li mitati on

OFF State
Open load

Current

Sense

OVER LOAD PR OTEC TION

(A C TIVE PO WE R L IMIT A TIO N)

Power
Clamp

V

ON

CH 1

GND

C hannels 2

CH 2

CONTROL & DIAGNOSTIC

OUT2

OUT1

OUTPUT

n

GND

INPUT

n

CURRENT SENSE

Power output.

Ground connection. Must be reverse battery protected by an external
diode/resistor network.

Voltage controlled input pin with hysteresis, CMOS compatible. Controls
output switch state.

Analog current sense pin, delivers a current proportional to the load current.

n

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

5/37

Block diagram and pin description VND5E160AJ-E

Figure 2. Configuration diagram (top view)

GND

INPUT2

INPUT1

CURRENT SENSE1
CURRENT SENSE2

CS_DIS

TAB = V

1
2

3
4

5
6

12
11
10

9
8
7

N.C.
OUTPUT2

OUTPUT2
OUTPUT1

OUTPUT1
N.C.

cc

PowerSSO-12

Table 2. Suggested connections for unused and not connected pins

Connection / pin Current sense N.C. Output Input CS_DIS

Floating Not allowed X X X X

To ground

Through 1kΩ

resistor

X

Through 22kΩ

resistor

Through 10kΩ

resistor

Through 10kΩ

resistor

6/37

VND5E160AJ-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I

S

V

V

CSD

CC

V

V

SENSE1

Fn

V

OUT1

I

I

CSD

I

IN1

V

IN1

I

IN2

V

IN2

CS_DIS

INPUT1

INPUT2

GND

OUTPUT1

CURRENT
SENSE1

OUTPUT2

CURRENT
SENSE2

I

GND

OUT1

I

SENSE1

I

OUT2

I

SENSE2

V

SENSE2

V

OUT2

V

CC

Note: V

Fn

= V

- VCC during reverse battery condition.

OUTn

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

-V

- I

I

- I

I

-I

CSENSE

V

CSENSE

DC supply voltage 41 V

CC

Reverse DC supply voltage 0.3 V

CC

DC reverse ground pin current 200 mA

GND

DC output current Internally limited A

OUT

Reverse DC output current 6 A

OUT

I

DC input current -1 to 10 mA

IN

DC current sense disable input current -1 to 10 mA

CSD

DC reverse CS pin current 200 mA

Current sense maximum voltage

VCC-41

+V

CC

V
V

7/37

Electrical specifications VND5E160AJ-E

Table 3. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

E

Maximum switching energy (single pulse)

MAX

(L=12mH; R

Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)

- INPUT

V

- CURRENT SENSE

ESD

- CS_DIS

- OUTPUT

- V

CC

V

T

Charge device model (CDM-AEC-Q100-011) 750 V

ESD

Junction operating temperature -40 to 150 °C

T

j

Storage temperature -55 to 150 °C

stg

2.2 Thermal data

Table 4. Thermal data

Symbol Parameter Max. value Unit

Thermal resistance junction-case (With one channel ON) 8 °C/W

Thermal resistance junction-ambient See Figure 36 °C/W

R

thj-case

R

thj-amb

=0Ω; V

L

=13.5V; T

bat

jstart

=150ºC; I

OUT

= I

limL

(Typ.) )

34 mJ

4000
2000
4000
5000
5000

V
V
V
V
V

8/37

VND5E160AJ-E Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8V<VCC<28V; -40°C<Tj<150°C, unless otherwise
stated.

Table 5. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

USDhyst

R

V

I

L(off1)

1. For each channel.

2. PowerMOS leakage included.

Operating supply voltage 4.5 13 28 V

CC

Undervoltage shutdown 3.5 4.5 V

USD

Undervoltage shutdown
hysteresis

I

= 1A; Tj= 25°C

OUT

On state resistance

ON

Clamp voltage IS= 20 mA 41 46 52 V

clamp

I

Supply current

S

Off state output
current

Output - VCC diode

V

F

voltage

(1)

(1)

(1)

= 1A; Tj= 150°C

I

OUT

I

= 1A; VCC= 5V; Tj= 25°C

OUT

Off State; V
VIN=V

OUT=VSENSE=VCSD

On State; V

VIN=V

OUT

V

IN=VOUT

-I

= 0.6A; Tj=150°C 0.7 V

OUT

= 13V; Tj= 25°C;

CC

=0V

=13V; VIN=5V; I

CC

OUT

=0V; VCC=13V; Tj=25°C
=0V; VCC=13V; Tj=125°C

=0A

000.01 3

0.5 V

160
320
210

(2)

(2)

5

2

3

6µAmA

5

Table 6. Switching (VCC=13V, Tj=25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

mΩ
mΩ
mΩ

µA

(dV

(dV

t

d(on)

t

d(off)

OUT

OUT

W

W

ON

OFF

Turn- On delay time RL= 13Ω (see Figure 6.)10 µs

Turn- Off delay time RL= 13Ω (see Figure 6.)15 µs

Turn- On voltage

/dt)

on

slope

Turn- Off voltage

/dt)

off

slope

Switching energy
losses during twon

Switching energy
losses during t

woff

= 13Ω

R

L

R

= 13Ω

L

RL= 13Ω (see Figure 6.)0.03 mJ

RL= 13Ω (see Figure 6.)0.02 mJ

See

Figure 26.

See

Figure 28.

V/µs

V/µs

9/37

Electrical specifications VND5E160AJ-E

Table 7. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

V

I

V

I(hyst)

V

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

V

CSCL

Table 8. Protections and diagnostics

Input low level voltage 0.9 V

IL

Low level input current VIN= 0.9V 1 µA

IL

Input high level voltage 2.1 V

IH

High level input current VIN= 2.1V 10 µA

IH

Input hysteresis voltage 0.25 V

Input clamp voltage

ICL

I

IN

= -1mA

I

IN

= 1mA

5.5

-0.7

CS_DIS low level voltage 0.9 V

Low level CS_DIS current V

= 0.9V 1 µA

CSD

CS_DIS high level voltage 2.1 V

High level CS_DIS current V

= 2.1V 10 µA

CSD

CS_DIS hysteresis voltage 0.25 V

CS_DIS clamp voltage

(1)

I

CSD

I

CSD

= 1mA

= -1mA

5.5

-0.7

7V

7V

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

limH

DC short circuit current

VCC= 13V

5V<VCC<28V

7101414A

V

V

A

= 13V;

I

T

T

T

V

DEMAG

V

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related

Short circuit current

limL

during thermal cycling

Shutdown temperature 150 175 200 °C

TSD

Reset temperature TRS + 1 TRS + 5 °C

T

R

Thermal reset of STATUS 135 °C

RS

Thermal hysteresis

HYST

(T

Turn-Off output voltage
clamp

TSD-TR

)

I

OUT

Output voltage drop

ON

limitation

diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

V

CC

TR<Tj<T

TSD

2.5 A

7°C

= 1A; VIN= 0; L= 20mH VCC-41 VCC-46 VCC-52 V

I

= 0.03A;

OUT

= -40°C...150°C

T

j

25 mV

(see Figure 8.)

10/37

VND5E160AJ-E Electrical specifications

Table 9. Current sense (8V<VCC<18V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

K

K

dK

1/K1

K

dK

2/K2

K

dK

3/K3

I

SENSE0

I

OL

I

0

1

OUT/ISENSE

I

OUT/ISENSE

Current sense ratio

(1)

drift

I

2

OUT/ISENSE

Current sense ratio

(1)

drift

I

3

OUT/ISENSE

Current sense ratio

(1)

drift

Analog sense
leakage current

Openload ON state
current detection
threshold

= 0.025A; V

OUT

Tj= -40°C...150°C 270 520 730

I

= 0.35A; V

OUT

Tj= -40°C...150°C

=0.35A; V

I

OUT

= 25°C...150°C

T

j

= 0.35A; V

I

OUT

=0V;

V

CSD

SENSE

TJ= -40 °C to 150 °C

I

= 0.5A; V

OUT

SENSE

Tj= -40°C...150°C

= 0.5A; V

I

OUT

= 25°C...150°C

T

j

= 0.5 A; V

I

OUT

= 0V;

V

CSD

= -40 °C to 150 °C

T

J

I

= 1.5A; V

OUT

= -40°C...150°C

T

j

I

=1.5A; V

OUT

= 25°C...150°C

T

j

= 1.5 A; V

I

OUT

=0V;

V

CSD

= -40 °C to 150 °C

T

J

I

=0A; V

OUT

=5V; VIN=0V; Tj=-40°C...150°C

V

CSD

V

=0V; VIN=5V; Tj=-40°C...150°C

CSD

I

=0.6A; V

OUT

V

=5V; VIN=5V; Tj= -40°C...150°C

CSD

V

= 5V, 8V<VCC<18V

IN

I

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

= 5 µA

SENSE

SENSE

SENSE

=0V;

= 0.5V; V

=0.5V; V

=0.5V; V

= 0.5V;

= 4V; V

= 4V; V

= 4 V;

=4V; V

=4V; V

= 4 V;

=0V;

CSD

CSD

CSD

CSD

CSD

CSD

=0V;

=0V;

CSD

=0V;

=0V;

= 0V;

= 0V;

=0V;

345

370

-13 13 %

370

390

-8 8 %

400

410

-4 4 %

0
0

0

15mA

470

470

460

460

430

430

610

540

550

510

470

460

1
2

1

µA
µA

µA

V

SENSE

V

SENSEH

I

SENSEH

Max analog
senseoutput
voltage

Analog sense

(2)

output voltage in
fault condition

Analog sense

(2)

output current in
fault condition

I

=1.5A; V

OUT

VCC=13V; R

VCC=13V; V

=0V; 5 V

CSD

= 3.9KΩ; 8V

SENSE

= 5V; 9 mA

SENSE

11/37

Electrical specifications VND5E160AJ-E

Table 9. Current sense (8V<VCC<18V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

DSENSE1H

t

DSENSE1L

t

DSENSE2H

Delay response
time from falling
edge of CS_DIS
pin

Delay response
time from rising
edge of CS_DIS
pin

Delay response
time from rising
edge of INPUT pin

<4V, 0.08A<Iout<1.5A

V

SENSE

I

=90% of I

SENSE

(see Figure 4.)

<4V, 0.08A<Iout<1.5A

V

SENSE

=10% of I

I

SENSE

(see Figure 4.)

<4V, 0.08A<Iout<1.5A

V

SENSE

I

=90% of I

SENSE

(see Figure 4.)

SENSE max

SENSE max

SENSE max

40 100 µs

520µs

30 150 µs

Delay response
time between rising

∆t

DSENSE2H

edge of output
current and rising
edge of current
sense

Delay response

t

DSENSE2L

time from falling
edge of INPUT pin

1. Parameter guaranteed by design; it is not tested.

2. Fault condition includes: power limitation, overtemperature and open load OFF state detection.

Table 10. Openload detection (8V<VCC<18V)

V
I

SENSE

I

OUT

I

OUTMAX

V
I

SENSE

(see Figure 4.)

<4V,

SENSE

=90% of I

= 90% of I

OUTMAX

= 1.5A (see Figure 7)

<4V, 0.08A<Iout<1.5A

SENSE

=10% of I

SENSEMAX,

SENSE max

80 250 µs

110 µs

Symbol Parameter Test conditions Min. Typ. Max. Unit

Openload Off state

V

OL

voltage detection

VIN = 0 V 2

threshold

See

Figure 5

4V

Output short circuit to

t

DSTKON

VCC detection delay at

See Figure 5 180 1200 µs

turn Off

I

L(off2)r

I

L(off2)f

Off state output current
at V

OUT

= 4V

Off state output current
at V

OUT

= 2V

=0V; V

V

IN

rising from 0V to 4V

V

OUT

=0V; V

V

IN

V

falling from VCC to 2V

OUT

=0V

SENSE

SENSE=VSENSEH

-120 0 µA

-50 90 µA

Delay response from

= 4 V; VIN= 0V

V

OUT

V

SENSE

= 90% of V

SENSEH

20 µs

td_vol

output rising edge to

SENSE

rising edge in

V
open-load

12/37

VND5E160AJ-E Electrical specifications

Figure 4. Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

t

DSENSE2H

t

DSENSE1L

t

DSENSE1H

t

DSENSE2L

Figure 5. Openload Off-state delay timing

OUTPUT STUCK TO V

V

IN

V

CS

Figure 6. Switching characteristics

V

OUT

dV

OUT

/dt

(on)

t

Won

80%

t

r

10%

CC

t

DSTKON

t

Woff

90%

t

f

V

OUT

V

> V

SENSEH

dV

OUT

/dt

OL

(off)

t

INPUT

t

d(on)

t

d(off)

t

13/37

Electrical specifications VND5E160AJ-E

Figure 7. Delay response time between rising edge of ouput current and rising

edge of current sense (CS enabled)

V

IN

∆

t

DSENSE2H

t

I

OUT

I

SENSE

90% I

OUTMAX

I

OUTMAX

I

SENSEMAX

t

90% I

Figure 8. Output voltage drop limitation

Vcc-Vout

Tj=150oC

Von

Von/Ron(T)

SENSEMAX

Tj=25

Tj=-40

t

o

C

o

C

Iout

14/37

VND5E160AJ-E Electrical specifications

Figure 9. I

I

/ I

out

sense

700

650

max Tj = -40 °C to 150 °C

600

550

500

450

400

350

min Tj = -40 °C to 150 °C

300

250

200

0,35 0,58 0,81 1,04 1,27 1,5

out

/ I

vs. I

sense

max Tj = 25 °C to 150 °C

min Tj = 25 °C to 150 °C

out

typical value

I

(A)

OUT

Figure 10. Maximum current sense ratio drift vs load current

dk/k(%)

15

10

5

0

-5

-10

-15
0,35 0,58 0,81 1,04 1,27 1,5

I

(A)

OUT

Note: Parameter guaranteed by design; it is not tested.

15/37

Electrical specifications VND5E160AJ-E

Table 11. Truth table

Conditions Input Output Sense (V

Normal operation

L

H

L

H

CSD

0

Nominal

=0V)

(1)

Overtemperature

Undervoltage

Overload

Short circuit to GND
(Power limitation)

Open load OFF State
(with external pull up)

Short circuit to V

CC

(external pull up
disconnected)

Negative output voltage
clamp

1. If the V
and external circuit.

is high, the SENSE output is at a high impedance, its potential depends on leakage currents

CSD

L

H

L

H

H

L
L

L
L

X

0

V

SENSEH

0
0

Nominal

(no power limitation)

H

Cycling

V

SENSEH

(power limitation)

L

H

LHV

L

H

L
L

H
H

0

V

SENSEH

SENSEH

V

SENSEH

< Nominal

LL0

16/37

VND5E160AJ-E Electrical specifications

Table 12. Electrical transient requirements

ISO 7637-2:

2004(E)

Test pulse

Test levels

(1)

Number of

pulses or

III IV Min. Max.

test times

Burst cycle/pulse

repetition time

Delays and
Impedance

1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω

2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω

3a -100V -150V 1h 90ms 100ms 0.1µs, 50Ω

3b +75V +100V 1h 90ms 100ms 0.1µs, 50Ω

4 -6V -7V 1 pulse 100ms, 0.01Ω

(2)

5b

ISO 7637-2:

+65V +87V 1 pulse 400ms, 2Ω

Test level results

2004E

Test pulse

III VI

1C C

2a C C

3a C C

3b C C

4C C

5b

(2)

CC

Class Contents

C All functions of the device performed as designed after exposure to disturbance.

E

1. The above test levels must be considered referred to VCC= 13.5V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

One or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.

17/37

Electrical specifications VND5E160AJ-E

2.4 Waveforms

Figure 11. Normal operation

Normal operation

INPUT

Nominal load Nominal load

I

OUT

V

SENSE

V

CS_DIS

Figure 12. Overload or Short to GND

Overload or Short to GND

INPUT

I

OUT

V

SENSE

V

CS_DIS

I

LimH

>

Power Limitation

I

LimL

Thermal cycling

>

18/37

VND5E160AJ-E Electrical specifications

Figure 13. Intermittent Overload

Intermittent Overload

INPUT

Overload

I

>

LimH

I

>

LimL

I

OUT

V

>

SENSEH

V

SENSE

V

CS_DIS

Figure 14. OFF-State Open Load with external circuitry

OFF-State Open Load

with external circuitry

Nominal load

INPUT

V

OUT

I

OUT

V

SENSE

V

CS_DIS

V

t

DSTK(on)

OL

V

SENSEH

V

> V

OUT

OL

>

19/37

Electrical specifications VND5E160AJ-E

Figure 15. Short to V

V

OUT

I

OUT

V

CS_DIS

CC

Resistive

Short to V

V

OL

t

DSTK(on)

CC

Short to V

CC

Hard

Short to V

V

> V

OUT

t

DSTK(on)

CC

OL

Figure 16. TJ evolution in Overload or Short to GND

TJ evolution in

Overload or Short to GND

INPUT

I

OUT

T

J

I

LimH

Self-limitation of fast thermal transients

T

J_START

Power Limitation

>

T

TSD

T

R

< I

T

HYST

LimL

20/37

VND5E160AJ-E Electrical specifications

2.5 Electrical characteristics curves

Figure 17. Off state output current Figure 18. High level input current

Iloff (nA)

300

250

200

150

100

50

0

-50 -25 0 25 50 75 100 125 150 175

Off State
Vcc=13V

Vin=Vout=0V

Tc (°C)

Iih (µA)

5

4,5

3,5

2,5

1,5

0,5

Vin=2.1V

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 19. Input clamp voltage Figure 20. Input low level

Vicl (V)

7

6,8

6,6

6,4

6,2

6

5,8

5,6

5,4

5,2

5

lin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vil (V)

2

1,8

1,6

1,4

1,2

1

0,8

0,6

0,4

0,2

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 21. Input high level Figure 22. Input hysteresis voltage

Vih (V)

4

3,5

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vihyst (V)

1

0,9

0,8

0,7

0,6

0,5

0,4

0,3

0,2

0,1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

21/37

Electrical specifications VND5E160AJ-E

Figure 23. On state resistance vs. T

Ron (mOhm)

300

250

200

150

100

50

Iout= 1A
Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

case

Figure 24. On state resistance vs. V

Ron (mOhm)

300

250

200

150

100

50

0 5 10 15 20 25 30 35 40

Vcc (V)

Figure 25. Undervoltage shutdown Figure 26. Turn-On voltage slope

Vusd (V)

16

14

12

10

8

6

4

2

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

(dVout/dt )On (V/ms)

1000

900

800

700

600

500

400

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

RI=13 Ohm

Tc (°C)

CC

Tc=150°C

Tc=125°C

Tc=25°C

Tc=-40°C

Figure 27. I

Ilimh (A)

20

15

10

5

0

-50 -25 0 25 50 75 100 125 150

LIMH

Vcc=13V

vs. T

case

Tc (°C)

22/37

Figure 28. Turn-Off voltage slope

(dVout/dt )Off (V/ms)

1400

1300

1200

1100

1000

900

800

700

600

500

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

RI= 13 Ohm

Tc (°C)

VND5E160AJ-E Electrical specifications

Figure 29. CS_DIS high level voltage Figure 30. CS_DIS clamp voltage

Vcsdh (V)

4

3,5

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 31. CS_DIS low level voltage

Vcsdl (V)

3

2,5

2

1,5

Vcsdcl(V)

10

9

8

7

6

5

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Iin = 1 mA

Tc (°C)

1

0,5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

23/37

Application information VND5E160AJ-E

3 Application information

Figure 32. Application schematic

+5V

V

CC

R

prot

Μ

CU

R

prot

R

prot

R

SENSE

C

EXT

CS_DIS

INPUT

CURRENT SENSE

D

ld

OUTPUT

GND

R

GND

GND

D

GND

V

Note: Channel 2 has the same internal circuit as channel 1.

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against
reverse battery.

3.1.1 Solution 1 : resistor in the ground line (R

This can be used with any type of load.

The following is an indication on how to dimension the R

1. R

2. R

where -I
maximum rating section of the device datasheet.

Power dissipation in R

P

= (-VCC)2/R

D

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum On-state currents of the different devices.

≤ 600mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

GND

S(on)max

GND

GND

)

)

(when VCC<0: during reverse battery situations) is:

GND

only)

resistor.

GND

S(on)max

becomes the sum of the

Please note that if the microprocessor ground is not shared by the device ground then the
R

will produce a shift (I

GND

S(on)max

* R
values. This shift will vary depending on how many devices are On in the case of several
high side drivers sharing the same R

24/37

GND

) in the input thresholds and the status output

GND

.

VND5E160AJ-E Application information

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).

3.1.2 Solution 2 : diode (D

A resistor (R

=1kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V

max DC rating. The same applies if the device is subject to transients on the VCC line

CC

that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os:

if the device drives an

GND

prot

) in line to

-V

CCpeak/Ilatchup

≤ R

prot

≤ (V

Calculation example:

For V

5kΩ ≤ R

= - 100V and I

CCpeak

≤ 180kΩ

prot

Recommended values: R

OHµC-VIH-VGND

≥ 20mA; V

latchup

=10kΩ, C

prot

EXT

) / I

IHmax

OHµC

=10nF.

≥ 4.5V

25/37

Application information VND5E160AJ-E

3.4 Current sense and diagnostic

The current sense pin performs a double function (see Figure 33: Current sense and

diagnostic):

● Current mirror of the load current in normal operation, delivering a current

proportional to the load one according to a know ratio K
The current I
external resistor R
minimum (see parameter V

can be easily converted to a voltage V

SENSE

. Linearity between I

SENSE

SENSE

in Table 9: Current sense (8V<VCC<18V)). The

OUT

and V

current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 9: Current sense (8V<VCC<18V)).

● Diagnostic flag in fault conditions, delivering a fixed voltage V

maximum current I

SENSEH

in case of the following fault conditions (refer to Tr u th ta bl e ):

– Power limitation activation

– Over-temperature

–Short to V

in OFF state

CC

– Open load in OFF state with additional external components.

A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.

.

X

SENSE

by means of an

SENSE

is ensured up to 5V

SENSEH

up to a

Figure 33. Current sense and diagnostic

41V

Overtemperature

Pwr_Lim

SENSEH

CS_DIS

To uC ADC

I

OUT/KX

R

PROT

R

SENSE

I

SENSEH

CURRENT

SENSEn

V

SENSE

V

OL OFF

INPUTn

Main MOSn

+

-

V

GND

V

PU_CMD

R

I

Loff2r

I

Loff2f

R

PU

PU

Load

PD

V

BAT

V

CC

OL

OUTn

26/37

VND5E160AJ-E Application information

−

3.4.1 Short to VCC and OFF state open load detection

Short to V

A short circuit between V
V

SENSEH

during the on state depending on the nature of the short circuit.

OFF state open load with external circuitry

CC

and output is indicated by the relevant current sense pin set to

CC

during the device off state. Small or no current is delivered by the current sense

Detection of an open load in off mode requires an external pull-up resistor R
the output to a positive supply voltage V

It is preferable V

to be switched off during the module stand-by mode in order to avoid the

PU

PU

.

connecting

PU

overall stand-by current consumption to increase in normal conditions, i.e. when load is
connected.

An external pull down resistor R

connected between output and GND is mandatory to

PD

avoid misdetection in case of floating outputs in off state (see Figure 33: Current sense and

diagnostic).

R

must be selected in order to ensure V

PD

OUT < VOLmin

unless pulled up by the external

circuitry:

OLfoffLPD

min)2(

R

≤ 22 KΩ is recommended.

PD

OUT

−

OFFupPull

_

VVIRV

2

=<⋅=

For proper open load detection in off state, the external pull-up resistor must be selected
according to the following formula:

⋅

V

OUT

−

=

ONupPull

_

+

IRRVR

⋅⋅

RR

PDPU

roffLPDPUPUPD

)2(

OL

max

VV

4

=>

For the values of V

(8V<V

CC

<18V).

OLmin ,VOLmax, IL(off2)r

and I

see Table 10: Openload detection

L(off2)f

27/37

Application information VND5E160AJ-E

3.5 Maximum demagnetization energy (VCC= 13.5V)

Figure 34. Maximum turn-Off current versus inductance (for each channel)

100

10

A

B

C

1

I (A)

0,1

0,1 1 10 100L (mH)

A:

T

= 150°C single pulse

jstart

B: T

C:

VIN, I

= 100°C repetitive pulse

jstart

T

= 125°C repetitive pulse

jstart

L

Demagnetization Demagnetization Demagnetization

Note: Values are generated with R

In case of repetitive pulses, T
must not exceed the temperature specified above for curves A and B.

=0 Ω.

L

(at beginning of each demagnetization) of every pulse

jstart

t

28/37

VND5E160AJ-E Package and PC board thermal data

4 Package and PC board thermal data

4.1 PowerSSO-12 thermal data

Figure 35. PowerSSO-12 PC board

Note: Layout condition of R

area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm

Figure 36.

RTHj_amb(°C/W)

R

thj-amb

70

65

60

55

50

45

40

0246810

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

vs. PCB copper area in open box free air condition (one channel ON)

PCB Cu heatsink area (cm^2)

29/37

Package and PC board thermal data VND5E160AJ-E

Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one

channel ON)

ZTH (°C/W)

100

Footprint

2

2 cm

8 cm

2

10

1

0,001 0,01 0,1 1 10 100 1000

Time (s)

Equation 1: pulse calculation formula

Z

THδ

R

TH

δ Z

THtp

1 δ–()+⋅=

where δ = tP/T

Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12

(a)

a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

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VND5E160AJ-E Package and PC board thermal data

Table 13. Thermal parameters

Area/island (cm2)Footprint28

R1= R7 (°C/W) 1.2

R2= R8 (°C/W) 6

R3 (°C/W) 3

R4 (°C/W) 8 8 7

R5 (°C/W) 22 15 10

R6 (°C/W) 26 20 15

C1= C7 (W.s/°C) 0.0008

C2= C8 (W.s/°C) 0.0016

C3 (W.s/°C) 0.0166

C4 (W.s/°C) 0.2 0.1 0.1

C5 (W.s/°C) 0.27 0.8 1

C6 (W.s/°C) 3 6 9

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Package and packing information VND5E160AJ-E

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.2 Package mechanical data

Figure 39. PowerSSO-12 package dimensions

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VND5E160AJ-E Package and packing information

Table 14. PowerSSO-12 mechanical data

Symbol

Min. Typ. Max.

A 1.250 1.620

A1 0.000 0.100

A2 1.100 1.650

B 0.230 0.410

C 0.190 0.250

D 4.800 5.000

E 3.800 4.000

e0.800

H 5.800 6.200

h 0.250 0.500

L 0.400 1.270

Millimeters

k0° 8°

X 2.200 2.800

Y 2.900 3.500

ddd 0.100

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Package and packing information VND5E160AJ-E

5.3 Packing information

Figure 40. PowerSSO-12 tube shipment (no suffix)

B

A

Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”)

Base Q.ty 100

C

Bulk Q.ty 2000

Tube length (± 0.5) 532

A 1.85

B 6.75

C (± 0.1) 0.6

All dimensions are in mm.

REEL DIMENSIONS

Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm min

No componentsNo components Components

Empty components pockets
saled with cover tape.

User direction of feed

Start

500mm min

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VND5E160AJ-E Order codes

6 Order codes

Table 15. Device summary

Package

Tube Tape and reel

PowerSSO-12 VND5E160AJ-E VND5E160AJTR-E

Order codes

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Revision history VND5E160AJ-E

7 Revision history

Table 16. Document revision history

Date Revision Changes

13-Sep-2004 1 Initial release.

Document reformatted and restructured.
Updated Figure 2: Configuration diagram (top view) : pins 7-12 left

unconnected (N.C) .
Updated Table 9: Current sense (8V<VCC<18V):

CC

, ∆t

<18V):

DSENSE2H,

14-Mar-2008 2

– added k, dk/k, t

t

DSENSE2L

DSENSE1H, tDSENSE1L, tDSENSE2H

values
Updated Table 10: Openload detection (8V<V
– added I

L(off2)r

, I

and td_vol parameters

L(off2)f

Added Figure 7: Delay response time between rising edge of ouput

current and rising edge of current sense (CS enabled).

Added Figure 9: Iout/ Isense vs. Iout.
Added Figure 10: Maximum current sense ratio drift vs load current.

Table 12: Electrical transient requirements : updated test level values

III and IV for test pulse 5b and notes.
Added Section 2.4: Waveforms.
Added Section 2.5: Electrical characteristics curves.
Updated Section 3: Application information:
– added Section 3.4: Current sense and diagnostic
Updated Section 4.1: PowerSSO-12 thermal data:
– changed Figure 36: Rthj-amb vs. PCB copper area in open box

free air condition (one channel ON).

– added Figure 37: PowerSSO-12 thermal impedance junction

ambient single pulse (one channel ON).

– Figure 38: Thermal fitting model of a double channel HSD in

PowerSSO-12 : added note.

– updated Table 13: Thermal parameters:

R3 value changed from 7 to 3 °C/W.
R4 values changed from 10 /10 /9 to 8 /8 /7 °C/W.
C3 value changed from 0.05 to 0.0166 W.s/°C.

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VND5E160AJ-E

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