Datasheet VND5E050ASO-E Datasheet (ST)

Features

("1($'5

VND5E050ASO-E

Double channel high-side driver with analog current sense

for automotive applications

Datasheet − production data

Max transient supply voltage V

Operating voltage range VCC4.5 to 28 V

Max on-state resistance (per ch.) R

Current limitation (typ) I

Off-state supply current I

1. Typical value with all loads connected.

■ General

CC

ON

LIMH

S

41 V

50 mΩ

27 A

(1)

2 µA

– Inrush current active management by

power limitation
– Very low standby current
– 3.0 V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– Compliant with European directive

2002/95/EC
– Very low current sense leakage
– AEC-Q100 qualified

■ Diagnostic functions

– Proportional load current sense
– High current sense precision for wide

currents range
– Current sense disable
– Off-state open load detection
– Output short to V

detection

CC

– Overload and short to ground (power

limitation) indication
– Thermal shutdown indication

■ Protections

– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss

of V

CC

SO-16L

– Overtemperature shutdown with auto

restart (thermal shutdown)
– Reverse battery protected
– Electrostatic discharge protection

Applications

■ All types of resistive, inductive and capacitive

loads

■ Suitable as LED driver

Description

The VND5E050ASO-E is a double channel high­side driver manufactured using ST proprietary
VIPower
SO-16L package. The device is designed to drive
12 V automotive grounded loads, and to provide
protection and diagnostics. It also implements a
3 V and 5 V CMOS-compatible interface for the
use with any microcontroller.

The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, overtemperature shut-off with
auto-restart and overvoltage active clamp. A
dedicated analog current sense pin is associated
with every output channel providing enhanced
diagnostic functions including fast detection of
overload and short-circuit to ground through
power limitation indication, overtemperature
indication, short-circuit to V
state and off-state open-load detection. The
current sensing and diagnostic feedback of the
whole device can be disabled by pulling the
CS_DIS pin high to share the external sense
resistor with similar devices.

®

M0-5 technology and housed in

diagnosis and on-

CC

June 2012 Doc ID 022473 Rev 4 1/37

This is information on a product in full production.

www.st.com

1

Contents VND5E050ASO-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24

3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 24

3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 25

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4.1 Short to VCC and off-state open-load detection . . . . . . . . . . . . . . . . . . 26

3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 28

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1 SO-16L thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/37 Doc ID 022473 Rev 4

VND5E050ASO-E List of tables

List of tables

Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Switching (VCC = 13 V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9. Current sense (8 V < V
Table 10. Open load detection (8 V < V

Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 12. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 13. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 14. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 15. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 16. SO-16L mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 17. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

< 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CC

< 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CC

Doc ID 022473 Rev 4 3/37

List of figures VND5E050ASO-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Delay response time between rising edge of output current and rising edge of current sense

(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. I

OUT/ISENSE

Figure 10. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14. Off-state open-load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15. Short to V
Figure 16. T

evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

J

Figure 17. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 18. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 19. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 20. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 21. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 23. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 24. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 26. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 27. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 28. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 29. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 30. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 31. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 32. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 33. Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 34. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 28

Figure 35. SO-16L PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 36. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 29

Figure 37. SO-16L thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 38. Thermal fitting model of a single channel HSD in SO-16L . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 39. SO-16L package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 40. SO-16L tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 41. SO-16L tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

vs I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

OUT

4/37 Doc ID 022473 Rev 4

VND5E050ASO-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

CC

Signal Clamp

IN1

IN2

CS_
DIS

CS1

CS2

Undervoltage

Control & Diagnostic 1

DRIVER

Over

temp.

V

SENSEH

LOGIC

Table 1. Pin function

Name Function

V

CC

OUTPUT

GND

1,2

Battery connection.

Power output .

Ground connection. Must be reverse battery protected by an external
diode/resistor network.

Limitation

Current

Limitation

OFF State
Open load

Current

Sense

OVERLOAD PROTECTION

(ACTIVE POWER LIMITATION)

Power
Clamp

V

ON

CH 1

GND

Channels 2

CH 2

CONTROL & DIAGNOSTIC

OUT2

OUT1

INPUT

1,2

CURRENT SENSE

Voltage controlled input pin with hysteresis, CMOS compatible. Controls
output switch state.

Analog current sense pin, delivers a current proportional to the load current.

1,2

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

Doc ID 022473 Rev 4 5/37

Block diagram and pin description VND5E050ASO-E

Figure 2. Configuration diagram (top view)



*1'

,1387

,1387

&6(16(

&6(16(

&6',6



Table 2. Suggested connections for unused and not connected pins

Connection / pin Current sense N.C. Output Input CS_DIS

Floating Not allowed X X X X

To ground

Through 1 KΩ

resistor

X

 9FF9FF



Through

22 KΩ resistor

287387

287387

287387

287387

287387

287387

9FF9FF

("1($'5

Through 10 KΩ

resistor

Through 10 KΩ

resistor

6/37 Doc ID 022473 Rev 4

VND5E050ASO-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I

S

V

V

CSD

CC

V

V

SENSE1

Fn

V

OUT1

I

I

CSD

I

IN1

V

IN1

I

IN2

V

IN2

CS_DIS

INPUT1

INPUT2

GND

OUTPUT1

CURRENT
SENSE1

OUTPUT2

CURRENT
SENSE2

I

GND

OUT1

I

SENSE1

I

OUT2

I

SENSE2

V

SENSE2

V

OUT2

V

CC

Note: V

Fn

= V

- VCC during reverse battery condition.

OUTn

2.1 Absolute maximum ratings

Stressing the device above the rating listed in Table 3: Absolute maximum ratings may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to the conditions in table below for extended

periods may affect device reliability.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

-V

-I

I

-I

I

CC

GND

OUT

OUT

I

IN

CSD

DC supply voltage 41 V

Reverse DC supply voltage 0.3 V

CC

DC reverse ground pin current 200 mA

DC output current Internally limited A

Reverse DC output current 20 A

DC input current -1 to 10 mA

DC current sense disable input current -1 to 10 mA

-I

CSENSE

V

CSENSE

DC reverse CS pin current 200 mA

- 41 to

V

Current sense maximum voltage

CC

+V

CC

V

Doc ID 022473 Rev 4 7/37

Electrical specifications VND5E050ASO-E

Table 3. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Maximum switching energy (single pulse)

E

V

V

MAX

ESD

ESD

(L = 3 mH; R
I

OUT=IlimL

=0Ω; V

L

(Typ.))

=13.5V; T

bat

jstart

=150°C;

Electrostatic discharge
(human body model: R = 1.5 KΩ; C=100pF)
– Input
– Current sense
–CS_DIS
–Output
–V

CC

Charge device model (CDM-AEC-Q100-011) 750 V

104 mJ

4000
2000
4000
5000
5000

V
V
V
V
V

T

T

stg

Junction operating temperature -40 to 150 °C

j

Storage temperature -55 to 150 °C

2.2 Thermal data

Table 4. Thermal data

Symbol Parameter Typical value Unit

R

th j-pcb

R

thj-amb

1. The measure is done in accordance with the JESD 51-8.

Thermal resistance junction-pcb (with one channel

(1)

ON)

Thermal resistance junction-ambient See Figure 36 °C/W

2.3 Electrical characteristics

Values specified in this section are for 8 V<VCC<28V; -40°C<Tj<150 °C, unless otherwise

stated.

Table 5. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

20 °C/W

V

V

V

USDhyst

R

V

clamp

Operating supply voltage 4.5 13 28 V

CC

Undervoltage shutdown 3.5 4.5 V

USD

Undervoltage shutdown
hysteresis

I

=2A; Tj=25°C 50

OUT

On-state resistance

ON

(1)

=2A; Tj= 150°C 100

OUT

I

=2A; VCC=5V; Tj= 25°C 65

OUT

Clamp voltage IS=20mA 41 46 52 V

8/37 Doc ID 022473 Rev 4

0.5 V

mΩI

VND5E050ASO-E Electrical specifications

Table 5. Power section (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Off-state; V
V

I

S

Supply current

IN=VOUT=VSENSE=VCSD

On-state; V
I

=0A

OUT

VIN=V

=25°C

T

I

L(off1)

1. For each channel.

2. PowerMOS leakage included.

Table 6. Switching (VCC=13V; Tj= 25°C)

Off-state output current

(1)

Output - VCC diode

V

F

voltage

(1)

j

VIN=V

=125°C

T

j

-I

=4A; Tj= 150°C 0.7 V

OUT

=13V; Tj= 25°C;

CC

=13V; VIN=5V;

CC

=0V; VCC=13V;

OUT

=0V; VCC=13V;

OUT

=0V

(2)5(2)

2

36mA

00.013

05

Symbol Parameter Test conditions Min. Typ. Max. Unit

Turn-on delay time RL=6.5Ω (see Figure 6)— 20 — µs

Turn-off delay time RL=6.5Ω (see Figure 6)— 45 — µs

/dt

Turn-on voltage slope RL=6.5Ω —

(on)

/dt

Turn-off voltage slope RL=6.5Ω —

(off)

Switching energy
losses during t

won

Switching energy
losses during t

woff

RL=6.5Ω (see Figure 6)— 0.15 — mJ

RL=6.5Ω (see Figure 6)— 0.3 — mJ

See

Figure 26

See

Figure 28

—V/µs

—V/µs

dV

dV

t

d(on)

t

d(off)

OUT

OUT

W

W

ON

OFF

µA

µA

Table 7. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

I(hyst)

V

V

CSDL

I

CSDL

V

CSDH

I

I

IH

ICL

Input low level voltage 0.9 V

IL

Low level input current VIN=0.9V 1 µA

IL

Input high level voltage 2.1 V

IH

High level input current VIN=2.1V 10 µA

Input hysteresis voltage 0.25 V

I

=1mA 5.5 7

Input clamp voltage

IN

IIN=-1mA -0.7

CS_DIS low level voltage 0.9 V

Low level CS_DIS current V

=0.9V 1 µA

CSD

CS_DIS high level voltage 2.1 V

Doc ID 022473 Rev 4 9/37

V

Electrical specifications VND5E050ASO-E

Table 7. Logic inputs (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

CSDH

V

CSD(hyst)

V

CSCL

Table 8. Protections and diagnostics

High level CS_DIS current V

=2.1V 10 µA

CSD

CS_DIS hysteresis voltage 0.25 V

I

=1mA 5.5 7

CS_DIS clamp voltage

CSD

I

=-1mA -0.7

CSD

(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

= 13 V 19 27 38 A

I

limH

I

limL

T

TSD

T

T

T

HYST

V

DEMAG

RS

DC short circuit current

Short circuit current
during thermal cycling

Shutdown temperature 150 175 200 °C

Reset temperature TRS+1 TRS+5 °C

R

Thermal reset of status 135 °C

Thermal hysteresis

TSD -TR

)

(T

Turn-off output voltage
clamp

CC

5V < V

<28V 38 A

CC

VCC=13V;
T

R<Tj<TTSD

I

=2A; VIN=0;

OUT

L=6mH

7A

7°C

-41 VCC-46 VCC-52 V

V

CC

V

I

=0.1A;

V

ON

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

T able 9. Current sense (8 V < VCC<18V)

Output voltage drop
limitation

OUT

T

= -40°C...+150°C

j

(see Figure 8)

25 mV

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

dK

K

0

K

1

1/K1

K

2

I

OUT/ISENSE

I

OUT/ISENSE

Current sense ratio

(1)

drift

I

OUT/ISENSE

= 0.05 A; V

OUT

=0V; Tj= -40°C...150°C

V

CSD

I

=1A; V

OUT

V

CSD

= -40°C...150°C

T

j

SENSE

=0V;

Tj= 25°C...150°C

I

=1A; V

OUT

V

CSD

SENSE

=0V;

TJ= -40 °C to 150 °C

I

=2A; V

OUT

V

CSD

T

= -40°C...150°C

j

= 25°C...150°C

T

j

SENSE

=0V;

SENSE

=4V;

=4V;

=4V;

=0.5V;

1440 2250 3630

1740

2070

2820

1750

2070

2562

-15 15 %

1900

2000

2395

1899

2000

2282

10/37 Doc ID 022473 Rev 4

VND5E050ASO-E Electrical specifications

T able 9. Current sense (8 V < VCC< 18 V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

dK

2/K2

K

dK

3/K3

I

SENSE0

I

OL

Current sense ratio

(1)

drift

I

3

OUT/ISENSE

Current sense ratio

(1)

drift

Analog sense leakage
current

Open load on-state
current detection
threshold

=2 A; V

OUT

=0V;

V

CSD

TJ= -40 °C to 150 °C

I

=4A;

OUT

V
T
T

I
V

=4V;V

SENSE

= -40°C...150°C

j

= 25°C...150°C

j

=4 A; V

OUT

=0V;

CSD

TJ= -40 °C to 150 °C

I

=0A; V

OUT

V

=5V; VIN=0V;

CSD

= -40°C...150°C

T

j

I

=0A; V

OUT

=0V; VIN=5V;

V

CSD

T

= -40°C...150°C

j

=2A; V

I

OUT

=5V; VIN=5V;

V

CSD

T

= -40°C...150°C

j

V

=5V; 8V<VCC<18V;

IN

I

=5µA

SENSE

SENSE

CSD

SENSE

SENSE

SENSE

SENSE

=4 V;

=0V;

=4 V;

=0V;

=0V;

=0V;

-9 9 %

1969

1990

2210

1950

1990

2153

-6 6 %

01

02

µA

01

420mA

V

SENSE

V

SENSEH

I

SENSEH

t

DSENSE1H

t

DSENSE1L

t

DSENSE2H

Max analog sense
output voltage

Analog sense output
voltage in fault
condition

(2)

Analog sense output
current in fault
condition

(2)

Delay response time
from falling edge of
CS_DIS pin

Delay response time
from rising edge of
CS_DIS pin

Delay response time
from rising edge of
INPUT pin

=4A; V

I

OUT

VCC=13V; R

VCC=13V; V

SENSE

SENSE

<4V; 0.5A<I

= 90% of I

V
I

(see Figure 4)

SENSE

SENSE

<4V; 0.5A<I

= 10% of I

V
I

(see Figure 4)

V
I

SENSE

SENSE

<4V; 0.5A<I

= 90% of I

(see Figure 4)

=0V 5 V

CSD

=3.9KΩ 8V

SENSE

=5V 9 mA

SENSE

<4A;

OUT

SENSEMAX

OUT

SENSEMAX

OUT

SENSEMAX

<4A;

<4A;

40 100 µs

520µs

80 250 µs

Doc ID 022473 Rev 4 11/37

Electrical specifications VND5E050ASO-E

T able 9. Current sense (8 V < VCC< 18 V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Delay response time
between rising edge of

Δt

DSENSE2H

output current and
rising edge of current
sense

Delay response time

t

DSENSE2L

from falling edge of
INPUT pin

1. Parameter guaranteed by design; it is not tested.

2. Fault condition includes: power limitation, overtemperature and open-load off-state detection.

Table 10. Open load detection (8 V < VCC<18V)

V
I

I
I

V
I

(see Figure 4)

SENSE

SENSE

= 90% of I

OUT

OUTMAX

SENSE

SENSE

= 90% of I

=10% of I

<4V;

SENSEMAX,

OUTMAX

=2A (see Figure 7)

<4V; 0.5A<I

OUT

SENSEMAX

40 µs

<4A;

80 250 µs

Symbol Parameter Test conditions Min. Typ. Max. Unit

Open load off-state

V

OL

voltage detection

=0V 2

V

IN

threshold

See

Figure 5

4V

Output short circuit to

t

DSTKON

detection delay at

V

CC

See Figure 5 180 1200 µs

turn-off

I

L(off2)r

I

L(off2)f

Off-state output current

OUT

=4V

at V

Off-state output current
at V

OUT

=2V

V

=0V; V

V

V
V

IN

OUT

IN

OUT

SENSE

rising from 0 V to 4 V

=0V; V

SENSE=VSENSEH

falling from VCC to 2 V

=0V;

-120 0 µA

;

-50 90 µA

Delay response from

td_vol

output rising edge to
V

SENSE

rising edge in

=4 V; VIN=0V;

V

OUT

V

SENSE

= 90% of V

SENSEH

20 µs

open load

Figure 4. Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

t

DSENSE2H

12/37 Doc ID 022473 Rev 4

t

DSENSE1L

t

DSENSE1H

t

DSENSE2L

VND5E050ASO-E Electrical specifications

Figure 5. Open-load off-state delay timing

OUTPUT STUCK TO V

V

IN

V

CS

Figure 6. Switching characteristics

V

OUT

dV

OUT

INPUT

/dt

(on)

t

d(on)

t

Won

80%

t

r

10%

t

d(off)

CC

V

t

DSTKON

t

Woff

90%

t

f

OUT

V

SENSEH

> V

dV

OL

OUT

/dt

(off)

t

t

Doc ID 022473 Rev 4 13/37

Electrical specifications VND5E050ASO-E

Figure 7. Delay response time between rising edge of output current and rising

edge of current sense (CS enabled)

V

IN

Δ

t

DSENSE2H

t

I

OUT

I

SENSE

90% I

OUTMAX

I

OUTMAX

I

SENSEMAX

t

90% I

Figure 8. Output voltage drop limitation

Vcc-V

out

Tj=150oC

V

on

Von/R

on(T)

SENSEMAX

=25oC

T

j

T

=-40oC

j

t

I

out

14/37 Doc ID 022473 Rev 4

VND5E050ASO-E Electrical specifications

Figure 9. I

I

/ I

out

sense

3000

2800

2600

2400

max Tj = 25 °C to 15 0 ° C

2200

2000

1800

1600

1400

1200

11,522,533,54

OUT/ISENSE

max Tj = -40 °C to 150 °C

min Tj = 25 °C to 150 °C

min Tj = -40 °C to 150 °C

vs I

OUT

typical value

I

(A)

OUT

Figure 10. Maximum current sense ratio drift vs load current

dk/k(%)

20

15

10

5

0

-5

-10

-15

-20
1234

I

OUT

Note: Parameter guaranteed by design; it is not tested.

(A)

Doc ID 022473 Rev 4 15/37

Electrical specifications VND5E050ASO-E

Table 11. Truth table

Conditions Input Output Sense (V

Normal operation

CSD

L

H

L

H

0

Nominal

=0V)

(1)

Overtemperature

Undervoltage

Overload

Short circuit to GND
(power limitation)

Open load off-state
(with external pull-up)

Short circuit to V

CC

(external pull-up
disconnected)

Negative output voltage
clamp

1. If the V
and external circuit.

is high, the SENSE output is at a high impedance, its potential depends on leakage currents

CSD

L

H

L

H

H

L
L

L
L

X

0

V

SENSEH

0
0

Nominal

(no power limitation)

H

Cycling

V

SENSEH

(power limitation)

L

H

LHV

L

H

L
L

H
H

0

V

SENSEH

SENSEH

V

SENSEH

< Nominal

LL0

16/37 Doc ID 022473 Rev 4

VND5E050ASO-E Electrical specifications

T able 12. Electrical transient requirements (part 1)

ISO 7637-2:

2004(E)

test pulse

Test levels

(1)

Number of

pulses or

III IV Min. Max.

test times

Burst cycle/pulse

repetition time

1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω

2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω

3a -100V -150V 1h 90ms 100ms 0.1µs, 50Ω

3b +75V +100V 1h 90ms 100ms 0.1µs, 50Ω

4 -6V -7V 1 pulse 100ms, 0.01Ω

(2)

5b

1. The above test levels must be considered referred to VCC= 13.5V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

T able 13. Electrical transient requirements (part 2)

ISO 7637-2:

+65V +87V 1 pulse 400ms, 2Ω

T est leve l results

2004E

test pulse

III VI

1C C

2a C C

3a C C

3b C C

Delays and
Impedance

4C C

(1)

5b

1. Valid in case of external load dump clamp: 40V maximum referred to ground.

T able 14. Electrical transient requirements (part 3)

CC

Class Contents

C All functions of the device performed as designed after exposure to disturbance.

One or more functions of the device did not perform as designed after exposure to

E

disturbance and cannot be returned to proper operation without replacing the
device.

Doc ID 022473 Rev 4 17/37

Electrical specifications VND5E050ASO-E

2.4 Waveforms

Figure 11. Normal operation

Normal operation

INPUT

Nominal load Nominal load

I

OUT

V

SENSE

V

CS_DIS

Figure 12. Overload or short to GND

Overload or Short to GND

INPUT

I

>

LimH

I

OUT

V

SENSE

V

CS_DIS

Power Limitation

I

LimL

Thermal cycling

>

18/37 Doc ID 022473 Rev 4

VND5E050ASO-E Electrical specifications

Figure 13. Intermittent overload

Intermittent Overload

INPUT

Overload

I

>

LimH

I

>

LimL

I

OUT

V

>

SENSEH

V

SENSE

V

CS_DIS

Figure 14. Off-state open-load with external circuitry

OFF-State Open Load

with external circuitry

Nominal load

INPUT

V

OUT

I

OUT

V

SENSE

V

CS_DIS

V

> V

OUT

OL

V

OL

t

DSTK(on)

V

SENSEH

>

Doc ID 022473 Rev 4 19/37

Electrical specifications VND5E050ASO-E

Figure 15. Short to V

V

OUT

I

OUT

V

CS_DIS

CC

Resistive

Short to V

V

OL

t

DSTK(on)

CC

Short to V

CC

Hard

Short to V

V

> V

OUT

t

DSTK(on)

CC

OL

Figure 16. TJ evolution in overload or short to GND

TJ evolution in

Overload or Short to GND

INPUT

I

OUT

T

J

Self-limitation of fast thermal transients

T

J_START

Power Limitation

I

>

LimH

T

T

TSD

R

< I

T

HYST

LimL

20/37 Doc ID 022473 Rev 4

VND5E050ASO-E Electrical specifications

2.5 Electrical characteristics curves

Figure 17. Off-state output current Figure 18. High level input current

Iloff (nA)

550

500

450

400

350

300

250

200

150

100

50

0

-50 -25 0 25 50 75 100 125 150 175

Off State
Vcc=13V

Vin=Vout=0V

Tc (°C)

Iih (µA)

5

4,5

3,5

2,5

1,5

0,5

Vin=2.1V

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 19. Input clamp voltage Figure 20. Input low level

Vicl (V)

7

6,8

6,6

6,4

6,2

6

5,8

5,6

5,4

5,2

5

lin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vil (V)

2

1,8

1,6

1,4

1,2

1

0,8

0,6

0,4

0,2

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 21. Input high level Figure 22. Input hysteresis voltage

Vih (V)

4

3,5

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vihyst (V)

1

0,9

0,8

0,7

0,6

0,5

0,4

0,3

0,2

0,1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Doc ID 022473 Rev 4 21/37

Electrical specifications VND5E050ASO-E

Figure 23. On-state resistance vs T

Ron (mOhm)

300

250

200

150

100

50

Iout= 2A
Vcc=13V

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

case

Figure 24. On-state resistance vs V

Ron (mOhm)

100

80

60

40

20

0

0 5 10 15 20 25 30 35 40

Vcc (V)

Figure 25. Undervoltage shutdown Figure 26. Turn-on voltage slope

Vusd (V)

16

14

12

10

8

6

4

2

0

-50 -25 0 25 50 75 100 125 150 175

Figure 27. I

Ilimh (A)

40

35

30

25

20

15

10

-50 -25 0 25 50 75 100 125 150 175

LIMH

Vcc=13V

vs T

Tc (°C)

case

Tc (°C)

(dVout/dt )On (V/ms)

1000

900

800

700

600

500

400

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

RI=6.5 Ohm

Tc (°C)

Figure 28. Turn-off voltage slope

(dVout/dt )Off (V/m s)

600

550

500

450

400

350

300

250

200

150

100

50

0

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

RI= 6.5 Ohm

Tc (°C)

CC

Tc=150°C

Tc=125°C

Tc=25°C

Tc=-40°C

22/37 Doc ID 022473 Rev 4

VND5E050ASO-E Electrical specifications

Figure 29. CS_DIS high level voltage Figure 30. CS_DIS clamp voltage

Vcsdh (V)

4

3,5

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vcsdcl(V)

10

9

8

7

6

5

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Icsd = 1 mA

Tc (°C)

Figure 31. CS_DIS low level voltage

Vcsdl (V)

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Doc ID 022473 Rev 4 23/37

Application information VND5E050ASO-E

3 Application information

Figure 32. Application schematic

+5V

V

CC

R

prot

Μ

CU

R

prot

R

prot

R

SENSE

C

EXT

CS_DIS

INPUT

CURRENT SENSE

D

ld

OUTPUT

GND

R

GND

GND

D

GND

V

Note: Channel 2 has the same internal circuit as channel 1.

3.1 GND protection network against reverse battery

This section provides two solutions to implement a ground protection network against
reverse battery.

3.1.1 Solution 1: resistor in the ground line (R

This can be used with any type of load.

The following description shows an indication on how to size the R

1. R

2. R

where -I
maximum rating section of the device datasheet.

Power dissipation in R

P

=(-VCC)2/R

D

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.

≤ 600mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

GND

S(on)max

GND

GND

)

)

(when VCC< 0: during reverse battery situations) is:

GND

only)

S(on)max

GND

becomes the sum of the

resistor.

Please note that if the microprocessor ground is not shared by the device ground then the
R

produces a shift (I

GND

S(on)max

* R

) in the input thresholds and the status output

GND

values. This shift varies depending on how many devices are on in case of several high-side
drivers sharing the same R

24/37 Doc ID 022473 Rev 4

GND

.

VND5E050ASO-E Application information

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Section 3.1.2: Solution 2: diode (DGND) in the

ground line.

3.1.2 Solution 2: diode (D

A resistor (R

=1kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600 mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift does not vary if more than one HSD share the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V

maximum DC rating. The same applies if the device is subject to transients on the VCC

CC

line which are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (R
the microcontroller I/O pins from latching-up.

The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:

if the device drives an

GND

) in line to prevent

prot

-V

CCpeak/Ilatchup

≤ R

prot

≤ (V

OHμC-VIH-VGND

Calculation example:

For V

CCpeak

5kΩ ≤ R

Recommended values: R

= - 100V and I

≤ 180kΩ

prot

latchup

=10kΩ, C

prot

≥ 20mA; V

EXT

3.4 Current sense and diagnostic

The current sense pin performs a double function (see Figure 33: Current sense and

diagnostic):

● Current mirror of the load current in normal operation, delivering a current

proportional to the load current according to a known ratio K

The current I
external resistor R
minimum (see parameter V

can be easily converted to a voltage V

SENSE

. Linearity between I

SENSE

Doc ID 022473 Rev 4 25/37

in Table 9: Current sense (8 V < VCC<18V)). The

SENSE

) / I

IHmax

≥ 4.5V

OHµC

= 10nF.

OUT

and V

.

X

by means of an

SENSE

is ensured up to 5V

SENSE

Application information VND5E050ASO-E

current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 9: Current sense (8 V < V

● Diagnostic flag in fault conditions, delivering a fixed voltage V

maximum current I

SENSEH

in case of the following fault conditions (refer to

<18V)).

CC

SENSEH

up to a

Table 11: Truth table):

– Power limitation activation

–Overtemperature

– Short to V

in off-state

CC

– Open-load in off-state with additional external components.

A logic level high on the CS_DIS pin simultaneously sets all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing
the sense resistance and ADC line among different devices.

Figure 33. Current sense and diagnostic

V

V

BAT

V

CC

PU

Main MOSn

+

-

INPUTn

GND

CS_DIS

To uC ADC

I

OUT/KX

R

PROT

R

SENSE

41V

I

SENSEH

CURRENT

SENSEn

V

SENSE

V

SENSEH

Overtemperature

OL OFF

Pwr_Lim

3.4.1 Short to VCC and off-state open-load detection

Short to V

A short circuit between V
V

SENSEH

during the on-state depending on the nature of the short circuit.

CC

and output is indicated by the relevant current sense pin set to

CC

during the device off-state. Little or no current is delivered by the current sense

PU_CMD

R

PU

V

OL

OUTn

I

Loff2r

I

Loff2f

Load

R

PD

Off-state open load with external circuitry

Detection of an open-load in off mode requires an external pull-up resistor (R
the output to a positive supply voltage (V

26/37 Doc ID 022473 Rev 4

PU

).

) connecting

PU

VND5E050ASO-E Application information

It is preferable that VPU is switched off during the module standby mode to avoid an increase
in overall standby current consumption in normal conditions, that is, when the load is
connected.

An external pull-down resistor (R

) connected between output and GND is mandatory to

PD

avoid misdetection in case of floating outputs in off-state (see Figure 33: Current sense and

diagnostic).

R

must be selected in order to ensure V

PD

OUT < VOLmin

unless pulled up by the external

circuitry:

VVIRV

2

=<⋅=

OLfoffLPD

min)2(

R

≤ 22 KΩ is recommended.

PD

OUT

OFFupPull

_

−

For proper open load detection in off-state, the external pull-up resistor must be selected
according to the following formula:

IRRVR

V

OUT

For the values of V

(8 V < V

CC

<18V).

−

OLmin,VOLmax, IL(off2)r

=

ONupPull

_

and I

⋅⋅−⋅

RR

+

PDPU

see Table 10: Open load detection

L(off2)f

roffLPDPUPUPD

)2(

OL

max

VV

4

=>

Doc ID 022473 Rev 4 27/37

Application information VND5E050ASO-E

3.5 Maximum demagnetization energy (VCC = 13.5V)

Figure 34. Maximum turn-off current versus inductance (for each channel)

100

A

B

C

10

I (A)

1

0,1 1 10 100L (mH)

A: T

B: T

C: T

, I

V

IN

= 150°C single pulse

jstart

= 100°C repetitive pulse

jstart

= 125°C repetitive pulse

jstart

L

Demagnetization Demagnetization Demagnetization

Note: Values are generated with R

each demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.

=0 Ω.In case of repetitive pulses, T

L

(at the beginning of

jstart

t

28/37 Doc ID 022473 Rev 4

VND5E050ASO-E Package and PCB thermal data

4 Package and PCB thermal data

4.1 SO-16L thermal data

Figure 35. SO-16L PC board

("1($'5

Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4

area = 77 mm x 86 mm, PCB thickness = 1.6 mm, Cu thickness = 70 µm (front and back
side), Copper areas: from minimum pad lay-out to 8 cm2).

Figure 36. R















      

vs PCB copper area in open box free air condition

thj-amb

57+MDPE

57+MDPE

'!0'2)

Doc ID 022473 Rev 4 29/37

Package and PCB thermal data VND5E050ASO-E

Figure 37. SO-16L thermal impedance junction ambient single pulse

=7+ & :



&X FP

&X FP

&X IRRWSULQW





     

7LPHV

'!0'2)

Equation 1: pulse calculation formula

Z

THδ

where δ =t

R

P

TH

/T

δ Z

THtp

1 δ–()+⋅=

Figure 38. Thermal fitting model of a single channel HSD in SO-16L

(a)

'!0'2)

a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

30/37 Doc ID 022473 Rev 4

VND5E050ASO-E Package and PCB thermal data

Table 15. Thermal parameter

Area/island (cm2)Footprint28

R1 (°C/W) 0.7

R2 (°C/W) 2.1

R3 (°C/W) 4

R4 (°C/W) 8 6 6

R5 (°C/W) 14 13 13

R6 (°C/W) 28 20 14.5

R7 (°C/W) 0.7

R8 (°C/W) 2.1

C1 (W.s/°C) 0.001

C2 (W.s/°C) 0.005

C3 (W.s/°C) 0.1

C4 (W.s/°C) 0.5

C5 (W.s/°C) 1 1.5 1.5

C6 (W.s/°C) 3 9 12

C7 (W.s/°C) 0.001

C8 (W.s/°C) 0.005

Doc ID 022473 Rev 4 31/37

Package information VND5E050ASO-E

5 Package information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

5.2 Package mechanical data

Figure 39. SO-16L package dimensions

.

32/37 Doc ID 022473 Rev 4

("1($'5

VND5E050ASO-E Package information

T able 16. SO-16L mechanical data

Millimeters

Symbol

Min Typ Max

A 2.35 2.65

A1 0.10 0.30

B 0.33 0.51

C 0.23 0.32

D 10.10 10.50

E 7.40 7.60

e1.27

H 10.00 10.65

h 0.25 0.75

L 0.40 1.27

k0° 8°

ddd 0.10

Doc ID 022473 Rev 4 33/37

Package information VND5E050ASO-E

5.3 Packing information

Figure 40. SO-16L tube shipment (no suffix)

"ASE1TY 

K1T Y 

"UL

#

"

4UBELE NGTH  
! 
" 
# 

!

!LLDIMENSIONSAREINMM

Figure 41. SO-16L tape and reel shipment (suffix “TR”)

("1($'5

34/37 Doc ID 022473 Rev 4

VND5E050ASO-E Order codes

6 Order codes

T a ble 17. Device summary

Order codes

Package

Tube Tape and reel

SO-16L VND5E050ASO-E VND5E050ASOTR-E

Doc ID 022473 Rev 4 35/37

Revision history VND5E050ASO-E

7 Revision history

Table 18. Document revision history

Date Revision Changes

10-Nov-2011 1 Initial release.

19-Dec-2011 2 Updated Figure 2.

15-Mar-2012 3

26-June-2012 4 Update Table 4.

Added Section 4: Package and PCB thermal data and update

Ta b l e 5 .

36/37 Doc ID 022473 Rev 4

VND5E050ASO-E

U

D

W

D

W

S

O
U

T

R

G

A

Y,

D

E

G

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