Datasheet VND5E025MK-E Datasheet (ST)

Features

VND5E025MK-E

Double-channel high-side driver with analog current sense

for automotive applications

Max transient supply voltage V

Operating voltage range V

Max on-state resistance (per ch.) R

Current limitation (typ) I

Off-state supply current I

1. Typical value with all loads connected.

■ General

CC

CC

ON

LIMH

S

4.5 to 28 V

25 mΩ

2µA

– Inrush current active management by

power limitation
– Very low standby current
– 3.0V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC

european directive
– Very low current sense leakage

■ Diagnostic functions

– Proportional load current sense
– High current sense precision for wide

currents range
– Current sense disable
– Overload and short to ground (power

limitation) indication
– Thermal shutdown indication

■ Protections

– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss

of V

CC

– Overtemperature shutdown with auto

restart (thermal shutdown)

41 V

60 A

(1)

Powe rSSO- 24

– Reverse battery protected (see Figure 29:

Application schematic

(1)

)

– Electrostatic discharge protection

Applications

■ All types of resistive, inductive and capacitive

loads

■ Suitable as LED driver

Description

The VND5E025MK-E is a double-channel high­side drivers manufactured in the ST proprietary
VIPower™ M0-5 technology and housed in the
tiny PowerSSO-24 package.
The VND5E025MK-E is designed to drive 12V
automotive grounded loads delivering protection,
diagnostics and easy 3V and 5V CMOS
compatible interface with any microcontroller.

The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, overtemperature shut-off with
auto-restart and overvoltage active clamp.

A dedicated analog current sense pin is
associated with every output channel in order to
provide Enhanced diagnostic functions including
fast detection of overload and short-circuit to
ground through power limitation indication and
overtemperature indication.

The current sensing and diagnostic feedback of
the whole device can be disabled by pulling the
CS_DIS pin high to allow sharing of the external
sense resistor with other similar devices.

October 2009 Doc ID 16471 Rev 1 1/35

www.st.com

1

Contents VND5E025MK-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 23

3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 23

3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 24

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 26

4 Package and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2/35 Doc ID 16471 Rev 1

VND5E025MK-E List of tables

List of tables

Table 1. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9. Current sense (8V < VCC < 18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 11. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 12. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 13. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 14. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 15. PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 16. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Doc ID 16471 Rev 1 3/35

List of figures VND5E025MK-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions

Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Delay response time between rising edge of output current and rising edge of current sense

(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. I

OUT/ISENSE

vs I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

OUT

Figure 9. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11. Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13. T

evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

J

Figure 14. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 15. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 16. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 17. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 19. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 20. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 21. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 22. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 23. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 24. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 25. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 26. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 27. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 28. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 29. Application schematic

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 30. Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 31. Maximum turn-off current versus inductance (for each channel)
Figure 32. PowerSSO-24 PC board

(1)

Figure 33. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 27

Figure 34. PowerSSO-24 thermal impedance junction to ambient single pulse (one channel ON). . . 28
Figure 35. Thermal fitting model of a double-channel HSD in PowerSSO-24

Figure 36. PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 37. PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 38. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

(1)

. . . . . . . . . . . . . . . . . . 26

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

(1)

. . . . . . . . . . . . . . . . . 28

4/35 Doc ID 16471 Rev 1

VND5E025MK-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

CC

Signal Clamp

IN1

IN2

CS_
DIS

CS1

CS2

Undervoltage

Control & Diagnostic 1

DRIVER

Over

temp.

V

SENSEH

LOGIC

Table 1. Pin functions

Name Function

V

CC

Battery connection.

Limitation

Current

Limitation

Current

Sense

OVERLOAD PROTECTION

(ACTIVE POWER LIMITATION)

Power
Clamp

V

ON

CH 1

GND

CONTROL & DIAGNOSTIC

Channels 2

CH 2

OUT2

OUT1

OUTPUT

1,2

GND

INPUT

1,2

CURRENT SENSE

Power output.

Ground connection. Must be reverse battery protected by an external
diode / resistor network.

Voltage controlled input pin with hysteresis, CMOS compatible. Controls
output switch state.

Analog current sense pin; delivers a current proportional to the load

1,2

current.

CS_DIS Active high CMOS compatible pin to disable the current sense pin.

Doc ID 16471 Rev 1 5/35

Block diagram and pin description VND5E025MK-E

Figure 2. Configuration diagram (top view)

V

CC

GND

N.C.

INPUT2

N.C.

INPUT1

N.C.

CURRENT SENSE1

N.C.

CURRENT SENSE2

CS_DIS.

V

CC

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1

TAB = V

CC

Table 2. Suggested connections for unused and not connected pins

Connection / pin Current sense N.C. Output Input CS_DIS

Floating Not allowed X X X X

To ground

Through 1kΩ

resistor

X

Through 22kΩ

resistor

Through 10kΩ

resistor

Through 10kΩ

resistor

6/35 Doc ID 16471 Rev 1

VND5E025MK-E Electrical specification

2 Electrical specification

Figure 3. Current and voltage conventions

I

CSD

CS_DIS

INPUT1

INPUT2

1. V

V

Fn

CSD

= V

V

IN1

V

- VCC during reverse battery condition.

OUTn

IN2

I

I

IN1

IN2

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.

Table 3. Absolute maximum ratings

GND

(1)

V

CC

OUTPUT1

CURRENT
SENSE1

OUTPUT2

CURRENT
SENSE2

I

GND

I

OUT1

I

SENSE1

I

OUT2

I

SENSE2

V

SENSE2

V

I

S

OUT2

V

SENSE1

V

Fn

V

OUT1

V

CC

Symbol Parameter Value Unit

V

-V

-I

GND

I

OUT

- I

OUT

I

CSD

-I

CSENSE

V

CSENSE

DC supply voltage 41

CC

Reverse DC supply voltage 0.3

CC

DC reverse ground pin current 200 mA

DC output current Internally limited

Reverse DC output current 24

DC input current

IN

-1 to 10

DC current sense disable input current

DC reverse CS pin current 200

Current sense maximum voltage VCC- 41 to +V

CC

V

A

mAI

V

Maximum switching energy (single pulse)

E

MAX

(L = 0.8 mH; R

= I

I

OUT

limL

(Typ.))

=0Ω; V

L

=13.5V; T

bat

jstart

= 150°C;

140 mJ

Doc ID 16471 Rev 1 7/35

Electrical specification VND5E025MK-E

Table 3. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Electrostatic discharge
(Human Body Model: R = 1.5kΩ; C = 100pF)

4000
2000
4000
5000
5000

V
V
V
V
V

°C

V

V

ESD

ESD

T

T

– INPUT
– CURRENT SENSE
–CS_DIS
–OUTPUT
–V

CC

Charge device model (CDM-AEC-Q100-011) 750 V

Junction operating temperature - 40 to 150

j

Storage temperature - 55 to 150

stg

2.2 Thermal data

Table 4. Thermal data

Symbol Parameter Max. value Unit

R

thj-case

R

thj-amb

Thermal resistance junction-case (with one channel ON) 1.35

°C/W

Thermal resistance junction-ambient See Figure 33

8/35 Doc ID 16471 Rev 1

VND5E025MK-E Electrical specification

2.3 Electrical characteristics

Values specified in this section are for 8V<VCC<28V; -40°C<Tj<150°C, unless otherwise
stated.

Table 5. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

USDhyst

R

V

clamp

I

L(off1)

1. For each channel.

2. PowerMOS leakage included.

Operating supply

CC

voltage

Undervoltage shutdown 3.5 4.5

USD

Undervoltage shutdown
hysteresis

On-state resistance

ON

Clamp voltage IS= 20 mA 41 46 52 V

I

Supply current

S

Off-state output

(1)

current

Output - VCC diode

V

F

voltage

(1)

I

=3A; Tj= 25°C 25

OUT

(1)

=3A; Tj= 150°C 50

OUT

=3A; VCC=5V; Tj= 25°C 35

I

OUT

Off-state; V
VIN=V

OUT=VSENSE=VCSD

=13V; Tj=25°C;

CC

On-state; VCC=13V; VIN=5V;
I

=0A

OUT

VIN=V

= 25°C

T

j

V

IN=VOUT

=0V; VCC=13V;

OUT

=0V; VCC=13V;

Tj= 125°C

-I

=4 A; Tj=150°C 0.7 V

OUT

=0V

4.5 13 28

VV

0.5

mΩI

(2)

2

(2)

5

µA

36mA

00.013

µA

05

Table 6. Switching (VCC=13V; Tj= 25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

d(on)

t

d(off)

(dV

/dt)onTurn-on voltage slope

OUT

/dt)

(dV

OUT

W

ON

W

OFF

Turn-on delay time

Turn-off delay time 40

Turn-off voltage slope

off

R

=4.3 Ω

L

(see Figure 5)

=4.3 Ω

R

L

Switching energy losses
during t

Switching energy losses
during t

ON

W

RL=4.3 Ω
(see Figure 5)

OFF

W

20

See

Figure 24

See

Figure 25

0.6

0.35

Doc ID 16471 Rev 1 9/35

µs

V/µs

mJ

Electrical specification VND5E025MK-E

Table 7. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

IL

I

IL

V

IH

I

IH

V

I(hyst)

ICL

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

V

CSCL

Table 8. Protections and diagnostics

Input low level voltage 0.9 V

Low level input current VIN=0.9V 1 µA

Input high level voltage 2.1 V

High level input current VIN=2.1V 10 µA

Input hysteresis voltage 0.25

I

=1mA 5.5 7

Input clamp voltage

IN

I

= -1mA -0.7

IN

CS_DIS low level voltage 0.9

Low level CS_DIS current V

=0.9V 1 µA

CSD

CS_DIS high level voltage 2.1 V

High level CS_DIS current V

=2.1V 10 µA

CSD

CS_DIS hysteresis voltage 0.25

I

=1mA 5.5 7

CS_DIS clamp voltage

CSD

= -1mA -0.7

I

CSD

(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

= 13V 43 60

I

LIMH

I

LIML

T

TSD

T

T

RS

T

HYST

V

DEMAG

V

ON

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

DC short circuit current

Short circuit current
during thermal cycling

Shutdown temperature 150 175 200

Reset temperature TRS+1 TRS+5

R

Thermal reset of STATUS 135

Thermal hysteresis
(T

TSD-TR

)

Turn-Off output voltage
clamp

Output voltage drop
limitation

CC

5V < V

CC

< 28V

VCC= 13V;
TR<Tj<T

I

OUT

TSD

=2A; VIN=0;

L=6 mH

=0.1A;

I

OUT

= -40°C to +150°C

T

j

(see Figure 6)

15

7

-41 VCC-46 VCC-52 V

V

CC

25 mV

85

VV

V

A

°C

10/35 Doc ID 16471 Rev 1

VND5E025MK-E Electrical specification

Table 9. Current sense (8V < VCC< 18V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

dK

K

LED

K

K

1/K1

K

= 0.05A; V

I

OUT/ISENSE

0

1

I

OUT/ISENSE

I

OUT/ISENSE

Current sense

(1)

ratio drift

2

I

OUT/ISENSE

OUT

Tj= -40°C to 150°C

I

=0.5A; V

OUT

= -40°C to 150°C

T

j

I

=2 A; V

OUT

=0V;

V

CSD

SENSE

SENSE

Tj= -40°C to 150°C

= 25°C to 150°C

T

j

=2 A; V

I

OUT

V

CSD

= -40°C to 150°C

T

j

I

=3 A; V

OUT

V

CSD

= -40°C to 150°C

T

j

SENSE

=0V;

SENSE

=0V;

Tj= 25°C to150°C

SENSE

=0.5V; V

=0.5V; V

=4 V;

=4 V;

=4V;

CSD

CSD

=0V;

=0V;

1240 3350 4960

1860 3150 4600

2100

3100

4400

2250

3100

3850

-13 13 %

2200

3000

4100

2450

3000

3550

dK

2/K2

K

dK

3/K3

I

SENSE

I

OL

V

SENSE

V

SENSEH

I

SENSEH

=3 A; V

Current sense

(1)

ratio drift

3

I

OUT/ISENSE

Current sense

(1)

ratio drift

Analog sense

0

leakage current

I

OUT

Tj= -40°C to 150°C

I

=10 A; V

OUT

V

=0V;

CSD

= -40°C to 150°C

T

j

= 25°C to 150°C

T

j

=10 A; V

I

OUT

= -40°C to 150°C

T

j

I

=0A; V

OUT

=5V; VIN=0V; Tj= -40°C to 150°C

V

CSD

V

=0V; VIN=5V; Tj= -40°C to 150°C

CSD

I

=2A; V

OUT

V

=5V; VIN=5V; Tj= -40°C to 150°C

CSD

SENSE

SENSE

SENSE

SENSE

SENSE

=4V; V

=4V;

=4V; V

=0V;

=0V;

CSD

CSD

=0V;

=0V;

-12 12 %

2550

2850

3280

2650

2850

3180

-6 +6 %

0
0

0

1
2

1

µA
µA

µA

Open-load on-

= 5V, 8V<VCC<18V

state current
detection
threshold

V

IN

I

SENSE

= 5 µA

530mA

Max analog
sense output

I

OUT

=3 A; V

=0V 5

CSD

voltage

V

Analog sense
output voltage in
fault condition

VCC= 13V; R

(2)

=3.9kΩ 8

SENSE

Analog sense
output current in
fault condition

VCC= 13V; V

(2)

=5V 9 mA

SENSE

Doc ID 16471 Rev 1 11/35

Electrical specification VND5E025MK-E

Table 9. Current sense (8V < VCC< 18V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

DSENSE1H

t

DSENSE1L

t

DSENSE2H

Delay response
time from falling
edge of CS_DIS
pin

Delay response
time from rising
edge of CS_DIS
pin

Delay response
time from rising
edge of INPUT
pin

V
I

SENSE

SENSE

<4V, 0.5<I

= 90% of I

(see Figure 4)

V
I

SENSE

SENSE

<4V, 0.5<I

= 10% of I

(see Figure 4)

V
I

SENSE

SENSE

<4V, 0.5<I

= 90% of I

(see Figure 4)

OUT

SENSEMAX

OUT

SENSEMAX

OUT

SENSEMAX

Delay response

SENSE

= 90% of I

<4V,

= 90% of I

OUTMAX

SENSEMAX,

, I

Δt

DSENSE2H

time between
rising edge of
output current
and rising edge

V
I

SENSE

I

OUT

(see Figure 7)

of current sense

Delay response

t

DSENSE2L

time from falling
edge of INPUT
pin

1. Parameter guaranteed by design; it is not tested.

2. Fault condition includes: power limitation and overtemperature.

V
I

SENSE

SENSE

<4V, 0.5<I

= 10% of I

(see Figure 4)

OUT

SENSEMAX

<10A

<10A

<10A

OUTMAX

<10A

=3A

30 100

520

80 300

µs

110

70 250

12/35 Doc ID 16471 Rev 1

VND5E025MK-E Electrical specification

Figure 4. Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

t

DSENSE2H

t

DSENSE1L

Figure 5. Switching characteristics

/dt

(on)

t

d(on)

t

Won

80%

t

r

V

OUT

dV

OUT

INPUT

10%

t

d(off)

t

Woff

90%

t

f

t

DSENSE1H

dV

OUT

/dt

(off)

t

DSENSE2L

t

t

Figure 6. Output voltage drop limitation

VCC-V

OUT

Tj=150oC

V

on

V

on/Ron(T)

Doc ID 16471 Rev 1 13/35

Tj=25oC

T

=-40oC

j

I

OUT

Electrical specification VND5E025MK-E

Figure 7. Delay response time between rising edge of output current and rising

edge of current sense (CS enabled)

V

IN

Δ

t

DSENSE2H

t

I

OUT

90% I

OUTMAX

I

OUTMAX

t

I

SENSE

I

90% I

SENSEMAX

SENSEMAX

t

14/35 Doc ID 16471 Rev 1

VND5E025MK-E Electrical specification

Figure 8. I

I

/ I

out

sense

4700

4200

3700

3200

2700

2200

1700

1200

2345678910

OUT/ISENSE

max Tj = -40 °C to 150 °C

max Tj = 25 °C to 150 °C

min Tj = 25 °C to 150 °C

min Tj = -40 °C to 150 °C

vs I

OUT

typical value

I

(A)

OUT

Figure 9. Maximum current sense ratio drift vs load current

dk/k(%)

20

15

10

5

0

-5

-10

-15

-20

2345678 910

I

OUT

(A)

Note: Parameter guaranteed by design; it is not tested.

Doc ID 16471 Rev 1 15/35

Electrical specification VND5E025MK-E

Table 10. Truth table

Conditions Input Output Sense (V

Normal operation

L

H

L

H

CSD

0

Nominal

=0V)

(1)

Overtemperature

Undervoltage

Overload

Short circuit to GND
(Power limitation)

Negative output voltage
clamp

1. If the V
and external circuit.

is high, the SENSE output is at a high impedance, its potential depends on leakage currents

CSD

L

H

L

H

H

L
L

L
L

X

0

V

SENSEH

0
0

Nominal

(no power limitation)

H

Cycling

V

SENSEH

(power limitation)

L

H

L
L

V

SENSEH

0

LL0

16/35 Doc ID 16471 Rev 1

VND5E025MK-E Electrical specification

Table 11. Electrical transient requirements (part 1/3)

ISO 7637-2:

2004(E) Test

pulse

Test levels

(1)

Number of

pulses or

III IV Min. Max.

test times

Burst cycle / pulse

repetition time

Delays and
Impedance

1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω

2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω

3a -100V -150V 1h 90ms 100ms 0.1µs, 50Ω

3b +75V +100V 1h 90ms 100ms 0.1µs, 50Ω

4 -6V -7V 1 pulse 100ms, 0.01Ω

(2)

5b

1. The above test levels must be considered referred to VCC= 13.5V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

Table 12. Electrical transient requirements (part 2/3)

ISO 7637-2:

+65V +87V 1 pulse 400ms, 2Ω

Test level results

2004E

Test pulse

III VI

1C C

2a C C

3a C C

3b C C

4C C

(1)

5b

1. Valid in case of external load dump clamp: 40V maximum referred to ground.

Table 13. Electrical transient requirements (part 3/3)

CC

Class Contents

C All functions of the device performed as designed after exposure to disturbance.

E

One or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.

Doc ID 16471 Rev 1 17/35

Electrical specification VND5E025MK-E

2.4 Waveforms

Figure 10. Normal operation

Normal operation

INPUT

Nominal load Nominal load

I

OUT

V

SENSE

V

CS_DIS

Figure 11. Overload or short to GND

Overload or Short to GND

INPUT

I

OUT

V

SENSE

V

CS_DIS

I

LimH

>

Power Limitation

I

LimL

Thermal cycling

>

18/35 Doc ID 16471 Rev 1

VND5E025MK-E Electrical specification

Figure 12. Intermittent overload

Intermittent Overload

INPUT

Overload

I

>

LimH

I

>

LimL

I

OUT

V

>

SENSEH

V

SENSE

V

CS_DIS

Figure 13. TJ evolution in overload or short to GND

TJ evolution in

Overload or Short to GND

Nominal load

INPUT

Self-limitation of fast thermal transients

T

J_START

T

J

I

>

LimH

I

OUT

Power Limitation

T

T

TSD

R

< I

T

HYST

LimL

Doc ID 16471 Rev 1 19/35

Electrical specification VND5E025MK-E

2.5 Electrical characteristics curves

Figure 14. Off-state output current Figure 15. High level input current

Iloff (nA)

1000

900

800

700

600

500

400

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Off State
Vcc=13V

Vin=Vout=0V

Tc (°C)

Iih (µA)

5

4,5

3,5

2,5

1,5

0,5

Vin = 2.1V

CC = 8 V

V

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 16. Input clamp voltage Figure 17. Input high level

Vicl (V)

7

6,8

6,6

6,4

6,2

5,8

5,6

5,4

5,2

lin=1mA

6

5

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vih (V)

4

3,5

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 18. Input low level Figure 19. Input hysteresis voltage

Vil (V)

2

1,8

1,6

1,4

1,2

1

0,8

0,6

0,4

0,2

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

20/35 Doc ID 16471 Rev 1

Vihyst (V)

1

0,9

0,8

0,7

0,6

0,5

0,4

0,3

0,2

0,1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

VND5E025MK-E Electrical specification

Figure 20. On-state resistance vs T

case

Ron (mOhm)

70

60

50

40

30

20

10

0

Iout= 3A

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Figure 21. On-state resistance vs V

Ron (mOhm)

60

50

40

30

20

10

0

0 5 10 15 20 25 30 35 40

Tc (°C)

Figure 22. Undervoltage shutdown Figure 23. I

Vusd (V)

16

14

12

10

8

6

4

2

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Ilimh (A)

70

65

60

55

50

45

40

-50 -25 0 25 50 75 100 125 150 175

LIMH

Vcc=13V

vs T

CC

Tc=150°C

Tc=125°C

Tc=25°C

Tc=-40°C

Vcc (V)

case

Tc (°C)

Figure 24. Turn-on voltage slope Figure 25. Turn-off voltage slope

(dVout/dt )On (V/ms)

700

600

500

400

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

RI=4.3 Ohm

Tc (°C)

Doc ID 16471 Rev 1 21/35

(dVout/dt )Off (V/ms)

600

500

400

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

RI= 4.3 Ohm

Tc (°C)

Electrical specification VND5E025MK-E

Figure 26. CS_DIS high level voltage Figure 27. CS_DIS low level voltage

Vcsdh (V)

4

3,5

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vcsdl (V)

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 28. CS_DIS clamp voltage

Vcsdcl(V)

10

9

8

7

6

5

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Icsd = 1 mA

Tc (°C)

22/35 Doc ID 16471 Rev 1

VND5E025MK-E Application information

3 Application information

Figure 29. Application schematic

+5V

R

prot

Μ

CU

1. Channel 2 has the same internal circuit as channel 1.

R

prot

R

prot

R

SENSE

C

EXT

(1)

CS_DIS

INPUT

CURRENT SENSE

V

CC

OUTPUT

GND

R

GND

GND

D

GND

V

3.1 GND protection network against reverse battery

D

ld

This section provides two solutions for implementing a ground protection network against
reverse battery.

3.1.1 Solution 1: resistor in the ground line (R

This can be used with any type of load.

The following is an indication on how to dimension the R

1. R

2. R

where -I
maximum rating section of the device datasheet.

Power dissipation in R

P

= (-VCC)2/R

D

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum On-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the
R

GND

values. This shift varies depending on how many devices are On in the case of several high
side drivers sharing the same R

≤ 600mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

GND

produces a shift (I

S(on)max

GND

GND

S(on)max

)

)

(when VCC<0: during reverse battery situations) is:

* R

GND

) in the input thresholds and the status output

GND

.

GND

only)

resistor.

GND

S(on)max

becomes the sum of the

Doc ID 16471 Rev 1 23/35

Application information VND5E025MK-E

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).

3.1.2 Solution 2: diode (D

A resistor (R

=1kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift not varies if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V

max DC rating. The same applies if the device is subject to transients on the VCC line

CC

that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins is pulled negative. ST suggests to insert a resistor (R
the MCU I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of MCU and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of MCU
I/Os:

if the device drives an

GND

) in line to prevent

prot

-V

CCpeak/Ilatchup

≤ R

prot

Calculation example:

For V

5kΩ ≤ R

CCpeak

prot

≤ 180kΩ

= - 100V and I

Recommended values: R

≤ (V

OHμC-VIH-VGND

≥ 20mA; V

latchup

=10kΩ, C

prot

EXT

) / I

IHmax

OHµC

=10nF.

≥ 4.5V

24/35 Doc ID 16471 Rev 1

VND5E025MK-E Application information

3.4 Current sense and diagnostic

The current sense pin performs a double function (see Figure 30: Current sense and

diagnostic):

● Current mirror of the load current in normal operation, delivering a current

proportional to the load one according to a know ratio K
The current I
external resistor R
minimum (see parameter V

can be easily converted to a voltage V

SENSE

. Linearity between I

SENSE

SENSE

in Table 9: Current sense (8V < VCC < 18V)). The

OUT

and V

current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 9: Current sense (8V < VCC < 18V)).

● Diagnostic flag in fault conditions, delivering a fixed voltage V

maximum current I

SENSEH

in case of the following fault conditions (refer to Tr ut h t a bl e):

– Power limitation activation

–Overtemperature

A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.

.

X

SENSE

by means of an

SENSE

is ensured up to 5V

SENSEH

up to a

Figure 30. Current sense and diagnostic

41V

I

OUT/KX

I

SENSEH

CS_DIS

V

SENSEH

CURRENT

SENSEn

R

PROT

To uC ADC

R

SENSE

V

SENSE

Overtemperature

Pwr_Lim

GND

V

CC

Main MOSn

V

BAT

OUTn

Load

Doc ID 16471 Rev 1 25/35

Application information VND5E025MK-E

3.5 Maximum demagnetization energy (VCC=13.5V)

Figure 31. Maximum turn-off current versus inductance (for each channel)

100

A

B

C

10

I (A)

1

0,1 1 10 100L (mH)

A:

T

= 150°C single pulse

jstart

B: T

C:

= 100°C repetitive pulse

jstart

T

= 125°C repetitive pulse

jstart

(1)

VIN, I

L

Demagnetization Demagnetization Demagnetization

1. Values are generated with R
In case of repetitive pulses, T
the temperature specified above for curves A and B.

=0 Ω.

L

(at beginning of each demagnetization) of every pulse must not exceed

jstart

26/35 Doc ID 16471 Rev 1

t

VND5E025MK-E Package and thermal data

4 Package and thermal data

4.1 PowerSSO-24 thermal data

Figure 32. PowerSSO-24 PC board

1. Layout condition of R
area = 77mm x 86mm, PCB thickness = 1.6mm, Cu thickness = 70µm (front and back side), Copper areas:
from minimum pad layout to 8cm

Figure 33. R

thj-amb

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

vs PCB copper area in open box free air condition (one channel

(1)

ON)

RTHj_amb(°C/W)

55

50

45

40

35

30

0246810

PCB Cu heatsink area (cm^2)

Doc ID 16471 Rev 1 27/35

Package and thermal data VND5E025MK-E

Figure 34. PowerSSO-24 thermal impedance junction to ambient single pulse (one

channel ON)

ZTH (°C/W)

1000

100

Footprint

2 cm

8 cm

10

1

0.1

0.0001 0.001 0.01 0.1 1 10 100 1000

Time (s)

Equation 1: pulse calculation formula

Z

THδ

R

TH

δ Z

THtp

1 δ–()+⋅=

where δ = tP/T

Figure 35. Thermal fitting model of a double-channel HSD in PowerSSO-24

2

2

(1)

1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

28/35 Doc ID 16471 Rev 1

VND5E025MK-E Package and thermal data

Table 14. Thermal parameters

Area/Island (cm2) Footprint 2 8

R1 (°C/W) 0.28

R2 (°C/W) 0.9

R3 (°C/W) 6

R4 (°C/W) 7.7

R5 (°C/W) 9 9 8

R6 (°C/W) 28 17 10

R7 (°C/W) 0.28

R8 (°C/W) 0.9

C1 (W.s/°C) 0.001

C2 (W.s/°C) 0.003

C3 (W.s/°C) 0.025

C4 (W.s/°C) 0.75

C5 (W.s/°C) 1 4 9

C6 (W.s/°C) 2.2 5 17

C7 (W.s/°C) 0.001

C8 (W.s/°C) 0.003

Doc ID 16471 Rev 1 29/35

Package and packing information VND5E025MK-E

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

5.2 Package mechanical data

Figure 36. PowerSSO-24 package dimensions

.

30/35 Doc ID 16471 Rev 1

VND5E025MK-E Package and packing information

Table 15. PowerSSO-24 mechanical data

Millimeters

Symbol

Min. Typ. Max.

A 2.15 2.47

A2 2.15 2.40

a1 0 0.075

b 0.33 0.51

c 0.23 0.32

D 10.10 10.50

E7.4 7.6

e0.8

e3 8.8

G 0.1

G1 0.06

H 10.1 10.5

h 0.4

k5°

L 0.55 0.85

N 10°

X4.1 4.7

Y6.5 7.1

Doc ID 16471 Rev 1 31/35

Package and packing information VND5E025MK-E

5.3 Packing information

Figure 37. PowerSSO-24 tube shipment (no suffix)

Base Qty 49
Bulk Qty 1225

C

B

Tube length (±0.5) 532
A 3.5
B 13.8
C (±0.1) 0.6

A

All dimensions are in mm.

Figure 38. PowerSSO-24 tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F 20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 24
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 12
Hole Diameter D (±0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (±0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (±0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm min

Empty components pockets
sealed with cover tape.

User direction of feed

Start

No componentsNo components Components

500mm min

32/35 Doc ID 16471 Rev 1

VND5E025MK-E Order codes

6 Order codes

Table 16. Device summary

Order codes

Package

Tube Tape and reel

PowerSSO-24 VND5E025MK-E VND5E025MKTR-E

Doc ID 16471 Rev 1 33/35

Revision history VND5E025MK-E

7 Revision history

Table 17. Document revision history

Date Revision Changes

07-Oct-2009 1 Initial release

34/35 Doc ID 16471 Rev 1

VND5E025MK-E

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

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