Datasheet VND5160AJ-E Datasheet (ST)

Double channel high side driver with analog current sense

Features

Max supply voltage V

Operating voltage range V

Max on-state resistance (per ch.) R

Current limitation (typ) I

Off state supply current I

1. Typical value with all loads connected.

■ General features

– Inrush current active management by

power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC

European directive

■ Diagnostic functions

– Proportional load current sense
– High current sense precision for wide range

currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage

■ Protection

– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss

of V

cc

– Thermal shut down

Table 1. Device summary

Package

CC

CC

ON

LIMH

S

4.5 to 36V

160 mΩ

2 µA

41 V

5 A

VND5160AJ-E

for automotive applications

PowerSSO-12

– Reverse battery protection (see Application

(1)

Tube Tape and Reel

schematic)

– Electrostatic discharge protection

Application

■ All types of resistive, inductive and capacitive

loads

■ Suitable as LED driver

Description

The VND5160AJ-E is a monolithic device made
using STMicroelectronics VIPower technology. It
is intended for driving resistive or inductive loads
with one side connected to ground. Active V
voltage clamp protects the device against low
energy spikes (see ISO7637 transient
compatibility table). This device integrates an
analog current sense which delivers a current
proportional to the load current (according to a
known ratio) when CS_DIS is driven low or left
open. When CS_DIS is driven high, the
CURRENT SENSE pin is in a high impedance
condition. Output current limitation protects the
device in overload condition. In case of long
overload duration, the device limits the dissipated
power to safe level up to thermal shut-down
intervention. Thermal shut-down with automatic
restart allows the device to recover normal
operation as soon as fault condition disappears.

Order codes

CC

pin

PowerSSO-12 VND5160AJ-E VND5160AJTR-E

February 2008 Rev 5 1/31

www.st.com

31

Contents VND5160AJ-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21

3.1.1 Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 21

3.1.2 Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 22

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23

4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31

VND5160AJ-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7. Switching (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 8. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9. Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10. Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 13. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/31

List of figures VND5160AJ-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Delay response time between rising edge of ouput current and rising edge of current sense

(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Iout/isense vs. Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 17. On state resistance vs. T
Figure 18. On state resistance vs. V

Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 20. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 21. I

LIMH

vs. T

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 22. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 27. Maximum turn-Off current versus inductance (for each channel). . . . . . . . . . . . . . . . . . . . 23

Figure 28. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 29. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 24

Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one channel ON) . . . 25

Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25

Figure 32. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 33. PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4/31

VND5160AJ-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

CC

V

CC

CLAMP

GND

INPUT1

INPUT2

CS_DIS

Table 2. Pin function

LOGIC

Name Function

V

CC

OUTPUT

GND

INPUT

n

n

Battery connection.

Power output.

Ground connection. Must be reverse battery protected by an external
diode/resistor network.

Voltage controlled input pin with hysteresis, CMOS compatible. Controls
output switch state.

Pwr

LIM

UNDERVOLTAGE

DRIVER 1

Pwr

1

LIM

OVERTEMP. 1

I

OUT1

2

PwCLAMP 1

V

K 1

I

LIM

DSLIM

OUTPUT1

CURRENT
SENSE1

1

1

DRIVER 2

I

OUT2

PwCLAMP 2

I

LIM

V

DSLIM

OVERTEMP. 2

K 2

OUTPUT2

2

2

CURRENT
SENSE2

CURRENT SENSE

Analog current sense pin, delivers a current proportional to the load current.

n

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

5/31

Block diagram and pin description VND5160AJ-E

Figure 2. Configuration diagram (top view)

GND

INPUT2

INPUT1

CURRENT SENSE1
CURRENT SENSE2

CS_DIS

TAB = V

1
2

3
4

5
6

12
11
10

9
8
7

N.C.
OUTPUT2

OUTPUT2
OUTPUT1

OUTPUT1
N.C.

cc

PowerSSO-12

Note: The above pin configuration reflects the changes notified with PCN-APG-BOD/07/2886. The

new pinout is backaward compatible with existing PCB layouts where pins #7 and 12 are
connected to Vcc. For new PCB designs, these pins should be left unconnected.

Table 3. Suggested connections for unused and N.C. pins

Connection / Pin Current Sense N.C. Output Input CS_DIS

Floating N.R.

To ground Through 1kΩ resistor X N.R.

1. Not recommended.

(1)

XX X X

(1)

Through 10kΩ

resistor

Through 10kΩ

resistor

6/31

VND5160AJ-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I

S

I

SENSEn

V

SENSEn

(1)

V

Fn

I

OUTn

V

OUTn

V

CC

V

CC

I

CSD

V

CSD

I

INn

V

INn

CS_DIS

INPUTn

GND

OUTPUTn

CURRENT
S

ENSEn

I

GND

Note: V

Fn

= V

- VCC during reverse battery condition.

OUTn

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

V

-V

- I

I

OUT

- I

I

CSD

-I

CSENSE

V

CSENSE

E

DC supply voltage 41 V

CC

Reverse DC supply voltage 0.3 V

CC

DC reverse ground pin current 200 mA

GND

DC output current Internally limited A

Reverse DC output current 6 A

OUT

I

DC input current -1 to 10 mA

IN

DC current sense disable input current -1 to 10 mA

DC reverse CS pin current 200 mA

Current sense maximum voltage

Maximum switching energy (single pulse)

MAX

(L=12mH; R

=0Ω; V

L

=13.5V; T

bat

jstart

=150ºC; I

OUT

= I

limL

(Typ.) )

VCC-41

+V

CC

34 mJ

V
V

7/31

Electrical specifications VND5160AJ-E

Table 4. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)

V

V

ESD

ESD

T

- INPUT

- CURRENT SENSE

- CS_DIS

- OUTPUT

- V

CC

Charge device model (CDM-AEC-Q100-011) 750 V

Junction operating temperature -40 to 150 °C

T

j

Storage temperature -55 to 150 °C

stg

4000
2000
4000
5000
5000

V
V
V
V
V

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter Max value Unit

R

thj-case

R

thj-amb

Thermal resistance junction-case (MAX) (With one channel ON) 8 °C/W

Thermal resistance junction-ambient (MAX) See Figure 29 °C/W

8/31

VND5160AJ-E Electrical specifications

2.3 Electrical characteristics

The values specified in this section are for 8V<VCC<36V; -40°C<Tj<150°C, unless otherwise
stated.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

USDhyst

R

V

I

L(off)

1. For each channel.

2. PowerMOS leakage included.

Operating supply voltage 4.5 13 36 V

CC

Undervoltage shutdown 3.5 4.5 V

USD

Undervoltage shut-down
hysteresis

I

= 0.5A; Tj= 25°C

OUT

On state resistance

ON

Clamp voltage IS= 20 mA 41 46 52 V

clamp

I

Supply current

S

Off state output
current

Output - VCC diode

V

F

voltage

(1)

(1)

(1)

= 0.5A; Tj= 150°C

I

OUT

I

= 0.5A; VCC= 5V; Tj= 25°C

OUT

Off State; V
VIN=V

OUT=VSENSE=VCSD

On State; V

VIN=V

OUT

V

IN=VOUT

-I

= 0.6A; Tj=150°C 0.7 V

OUT

= 13V; Tj= 25°C;

CC

=0V

=13V; VIN=5V; I

CC

OUT

=0V; VCC=13V; Tj=25°C
=0V; VCC=13V; Tj=125°C

=0A

000.01 3

0.5 V

160
320
210

(2)

(2)

5

2

3

6µAmA

5

Table 7. Switching (VCC=13V, Tj=25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

mΩ
mΩ
mΩ

µA

(dV

(dV

t

d(on)

t

d(off)

OUT

OUT

W

W

ON

OFF

Turn- On delay time RL= 26Ω (see Figure 8.)10 µs

Turn- Off delay time RL= 26Ω (see Figure 8.)15 µs

Turn- On voltage

/dt)

on

slope

Turn- Off voltage

/dt)

off

slope

Switching energy
losses during twon

Switching energy
losses during t

woff

= 26Ω

R

L

R

= 26Ω

L

RL= 26Ω (see Figure 8.)0.03 mJ

RL= 26Ω (see Figure 8.)0.02 mJ

See

Figure 20.

See

Figure 22.

V/µs

V/µs

9/31

Electrical specifications VND5160AJ-E

Table 8. Logic input

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

V

I

V

I(hyst)

V

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

V

CSCL

Table 9. Protection and diagnostics

Input low level voltage 0.9 V

IL

Low level input current VIN= 0.9V 1 µA

IL

Input high level voltage 2.1 V

IH

High level input current VIN= 2.1V 10 µA

IH

Input hysteresis voltage 0.25 V

Input clamp voltage

ICL

I

IN

= -1mA

I

IN

= 1mA

5.5

-0.7

CS_DIS low level voltage 0.9 V

Low level CS_DIS current V

= 0.9V 1 µA

CSD

CS_DIS high level voltage 2.1 V

High level CS_DIS current V

= 2.1V 10 µA

CSD

CS_DIS hysteresis voltage 0.25 V

CS_DIS clamp voltage

(1)

I

I

CSD

CSD

= 1mA

= -1mA

5.5

-0.7

7V

7V

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

limH

DC short circuit current

VCC= 13V
5V<VCC<36V

3.8 5 7.5

7.5

V

V

A
A

I

T

T

T

V

DEMAG

V

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related

Short circuit current during

limL

thermal cycling

Shutdown temperature 150 175 200 °C

TSD

T

Reset temperature TRS + 1 TRS + 5 °C

R

Thermal reset of STATUS 135 °C

RS

Thermal hysteresis (T

HYST

TSD-TR

Turn-Off output voltage clamp

Output voltage drop

ON

limitation

diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

= 13V; TR<Tj<T

V

CC

TSD

2A

)7°C

I

= 1A; VIN= 0;

OUT

L= 20mH

I

= 0.03A;

OUT

Tj= -40°C...150°C

VCC-41 VCC-46 VCC-52 V

25 mV

(see Figure 9.)

10/31

VND5160AJ-E Electrical specifications

Table 10. Current sense (8V<VCC<16V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

K

K

dK

1/K1

K

dK

2/K2

K

dK

3/K3

I

SENSE0

I

OL

I

0

1

OUT/ISENSE

I

OUT/ISENSE

Current sense ratio

(1)

drift

I

2

OUT/ISENSE

Current sense ratio

(1)

drift

I

3

OUT/ISENSE

Current sense ratio

(1)

drift

Analog sense
leakage current

Openload ON state
current detection
threshold

= 0.025A; V

OUT

Tj= -40°C...150°C 260 500 750

I

= 0.35A; V

OUT

Tj= -40°C...150°C

=0.35A; V

I

OUT

= 25°C...150°C

T

j

= 0.35A; V

I

OUT

=0V;

V

CSD

SENSE

TJ= -40 °C to 150 °C

I

= 0.5A; V

OUT

SENSE

Tj= -40°C...150°C

= 0.5A; V

I

OUT

= 25°C...150°C

T

j

= 0.5 A; V

I

OUT

= 0V;

V

CSD

= -40 °C to 150 °C

T

J

I

= 1.5A; V

OUT

= -40°C...150°C

T

j

I

=1.5A; V

OUT

= 25°C...150°C

T

j

= 1.5 A; V

I

OUT

=0V;

V

CSD

= -40 °C to 150 °C

T

J

I

=0A; V

OUT

=5V; VIN=0V; Tj=-40°C...150°C

V

CSD

V

=0V; VIN=5V; Tj=-40°C...150°C

CSD

I

=0.6A; V

OUT

V

=5V; VIN=5V; Tj= -40°C...150°C

CSD

V

= 5V, I

IN

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

= 0.5V; V

=0.5V; V

=0.5V; V

= 0.5V;

CSD

CSD

CSD

=0V;

=0V;

=0V;

320

360

450

450

590

540

-13 +13 %

= 4V; V

= 4V; V

CSD

CSD

= 0V;

= 0V;

360

380

440

440

540

510

= 4 V;

-8 +8 %

=4V; V

=4V; V

CSD

CSD

=0V;

=0V;

410

420

440

440

480

460

= 4 V;

-4 +4 %

=0V;

0
0

1
2

=0V;

0

1

= 5 µA 1 5 mA

µA
µA

µA

V

SENSE

V

SENSEH

I

SENSEH

Max analog
senseoutput
voltage

Analog sense
output voltage in
overtemperature
condition

Analog sense
output current in
overtemperature
condition

I

OUT

V

V

CC

CC

=1.5A; V

=13V; R

=13V; V

=0V; 5 V

CSD

= 3.9KΩ; 9V

SENSE

= 5V; 8 mA

SENSE

11/31

Electrical specifications VND5160AJ-E

Table 10. Current sense (8V<VCC<16V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

DSENSE1H

t

DSENSE1L

t

DSENSE2H

Delay response
time from falling
edge of CS_DIS
pin

Delay response
time from rising
edge of CS_DIS
pin

Delay response
time from rising
edge of INPUT pin

V
I
(see Figure 4.)

V
I
(see Figure 4.)

V
I

(see Figure 4.)

<4V, 0.08A<Iout<1.5A

SENSE

=90% of I

SENSE

<4V, 0.08A<Iout<1.5A

SENSE

=10% of I

SENSE

<4V, 0.08A<Iout<1.5A

SENSE

=90% of I

SENSE

Delay response
time between rising

∆t

DSENSE2H

edge of output
current and rising
edge of current
sense

Delay response

t

DSENSE2L

time from falling
edge of INPUT pin

1. Parameter guaranteed by design; it is not tested.

V
I

SENSE

I

OUT

I

OUTMAX

V
I

SENSE

(see Figure 4.)

<4V,

SENSE

=90% of I

= 90% of I

=2A (see Figure 5)

<4V, 0.08A<Iout<1.5A

SENSE

=10% of I

SENSE max

SENSE max

SENSE max

SENSEMAX,

OUTMAX

SENSE max

50 100 µs

520µs

80 150 µs

20 µs

100 250 µs

Figure 4. Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

t

DSENSE2H

t

DSENSE1L

t

DSENSE1H

t

DSENSE2L

12/31

VND5160AJ-E Electrical specifications

Figure 5. Delay response time between rising edge of ouput current and rising

edge of current sense (CS enabled)

V

IN

∆

t

DSENSE2H

t

I

OUT

I

SENSE

90% I

OUTMAX

I

OUTMAX

I

SENSEMAX

t

90% I

SENSEMAX

t

13/31

Electrical specifications VND5160AJ-E

Figure 6. I

I

/ I

out

sense

700

650

600

550

500

450

400

350

300

250

200

0,35 0,58 0,81 1,04 1,27 1,5

/ I

out

max Tj = -40 °C to 150 °C

min Tj = -40 °C to 150 °C

vs. I

sense

max Tj = 25 °C to 150 °C

min Tj = 25 °C to 150 °C

out

(see Table 10 for details)

typical value

I

(A)

OUT

Figure 7. Maximum current sense ratio drift vs load current

dk/k(%)

15

10

5

0

-5

-10

-15
0,1 0,3 0,5 0,7 0,9 1,1 1,3 1,5 1,7

I

(A)

OUT

Note: Parameter guaranteed by design; it is not tested.

14/31

VND5160AJ-E Electrical specifications

Table 11. Truth table

Conditions INPUT OUTPUT SENSE (V

Normal operation

CSD

L
H

L

H

0

Nominal

=0V)

(1)

Overtemperature

Undervoltage

Short circuit to GND
(R

≤ 10 mΩ)

sc

Short circuit to V

CC

L
H

L
H

L
H
H

L
H

L
L

V

SENSEH

L
L

L
L
L

V

SENSEH

0 if T

H
H

< Nominal

Negative output voltage clamp L L 0

1. If the V
and external circuit.

is high, the SENSE output is at a high impedance, its potential depends on leakage currents

CSD

Figure 8. Switching characteristics

V

OUT

dV

OUT

INPUT

t

Won

80%

/dt

t

d(on)

(on)

t

r

10%

t

d(off)

t

Woff

90%

t

dV

/dt

OUT

(off)

f

t

0

0
0

0

< T

j

TSD

if Tj > T

0

TSD

Figure 9. Output voltage drop limitation

Vcc-Vout

Tj=150oC

Von

Von/Ron(T)

Tj=25

o

C

Tj=-40

o

C

Iout

t

15/31

Electrical specifications VND5160AJ-E

Table 12. Electrical transient requirements

ISO 7637-2:

Test levels

2004(E)

Test pulse

III IV

1 -75V -100V

2a +37V +50V

3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω

3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω

4-6V-7V1 pulse

(2)

5b

+65V +87V 1 pulse 400 ms, 2 Ω

(1)

Number of

pulses or

test times

5000

pulses

5000

pulses

Burst cycle/pulse

repetition time

Delays and
impedance

0.5 s 5 s 2 ms, 10 Ω

0.2 s 5 s 50 µs, 2 Ω

100 ms, 0.01

Ω

ISO 7637-2:

Test level results

(1)

2004(E)

Tes t puls e

III IV

1C C

2a C C

3a C C

3b C C

4C C

(2)

5b

1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

CC

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

E

One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.

16/31

VND5160AJ-E Electrical specifications

Figure 10. Waveforms

NORMAL OPERATION

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

UNDERVOLTAGE

V

V

CC

INPUT
CS_DIS

LOAD CURRENT

SENSE CURRENT

V

USD

USDhyst

INPUT

CS_DIS

LOAD VOLTAGE

LOAD CURRENT

SENSE CURRENT

T

j

T

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

T

R

T

RS

TSD

current

limitation

SHORT TO V

<Nominal

OVERLOAD OPERATION

power
limitation

CC

<Nominal

I

LIMH

I

LIML

V

SENSEH

thermal cycling

SHORTED LOAD NORMAL LOAD

17/31

Electrical specifications VND5160AJ-E

2.4 Electrical characteristics curves

Figure 11. Off state output current Figure 12. High level input current

Iloff (uA )

0.3

0.25

0.2

0.15

0.1

0.05

0

-50 -25 0 25 50 75 100 125 150 175

Off State
Vcc=13V

Vin=Vout=0V

Tc (°C )

Iih (uA )

5

4.5

4

3.5

3

2.5

2

1.5

0.5

0

Vin=2.1V

1

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

Figure 13. Input clamp voltage Figure 14. Input low level

Vicl (V)

7

6.8

6.6

6.4

6.2

6

5.8

5.6

5.4

5.2

5

lin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

Vil (V)

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

Figure 15. Input high level Figure 16. Input hysteresis voltage

Vih (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

18/31

Vihyst (V)

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

VND5160AJ-E Electrical specifications

Figure 17. On state resistance vs. T

Ron (mOhm)

300

280

260

240

220

200

180

160

140

120

100

80

Io u t=0 . 5A

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

case

Figure 18. On state resistance vs. V

Ron (mOhm)

300

275

250

225

200

175

150

125

100

75

0 5 10 15 20 25 30 35 40

Vcc (V)

Figure 19. Undervoltage shutdown Figure 20. Turn-On voltage slope

Vusd (V)

16

14

12

10

8

6

4

2

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

(dV ou t/dt)on (V /ms)

1000

900

800

700

600

500

400

300

200

100

Vcc=13V

RI=26O hm

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

CC

Tc=150°C

Tc=125°C

Tc=25°C

Tc=-40°C

Figure 21. I

Ili mh (A )

16

14

12

10

8

6

4

2

0

-50 -25 0 25 50 75 100 125 150 175

LIMH

Vcc=13V

vs. T

case

Tc (°C )

Figure 22. Turn-Off voltage slope

(dV ou t/dt)off (V/ms)

1000

900

800

700

600

500

400

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Vcc=13V

RI=26O hm

Tc (°C )

19/31

Electrical specifications VND5160AJ-E

Figure 23. CS_DIS high level voltage Figure 24. CS_DIS clamp voltage

Vcsdh (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

Figure 25. CS_DIS low level voltage

Vcsdl (V)

4

3.5

3

2.5

2

Vcsdcl (V)

8

7.5

6.5

5.5

4.5

Ic s d =1m A

7

6

5

4

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

20/31

VND5160AJ-E Application information

3 Application information

Figure 26. Application schematic

+5V

V

CC

R

prot

µ

C

R

prot

CS_DIS

IINPUT

OUTPUT

D

ld

R

prot

C

EXT

CURRENT SENSE

R

SENSE

GND

R

GND

GND

D

GND

V

Note: Channel 2 has the same internal circuit as channel 1.

3.1 GND protection network against reverse battery

3.1.1 Solution 1 : resistor in the ground line (R

This can be used with any type of load.

The following is an indication on how to dimension the R

1. R

2. R

where -I
maximum rating section of the device datasheet.

≤ 600mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

S(on)max

GND

).

)

GND

only)

GND

resistor.

Power Dissipation in R

P

= (-VCC)2/R

D

GND

(when VCC<0: during reverse battery situations) is:

GND

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I

S(on)max

becomes the sum of the

maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the
R

will produce a shift (I

GND

S(on)max

* R

) in the input thresholds and the status output

GND

values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R

GND

.

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).

21/31

Application information VND5160AJ-E

3.1.2 Solution 2 : diode (D

A resistor (R

=1kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V

max DC rating. The same applies if the device is subject to transients on the VCC line

CC

that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the MCU I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of MCU and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of MCU
I/Os.

if the device drives an

GND

prot

) in line to

-V

CCpeak/Ilatchup

≤ R

prot

≤ (V

Calculation example:

For V

5kΩ ≤ R

CCpeak

prot

≤ 180kΩ.

= - 100V and I

Recommended values: R

OHµC-VIH-VGND

≥ 20mA; V

latchup

=10kΩ, C

prot

EXT

) / I

IHmax

OHµC

=10nF.

≥ 4.5V

22/31

VND5160AJ-E Application information

3.4 Maximum demagnetization energy (VCC= 13.5V)

Figure 27. Maximum turn-Off current versus inductance (for each channel)

10

A

B

C

1

I (A)

0,1

0,1 1 10 100L (mH)

A:

T

= 150°C single pulse

jstart

B: T

C:

VIN, I

= 100°C repetitive pulse

jstart

T

= 125°C repetitive pulse

jstart

L

Demagnetization Demagnetization Demagnetization

Note: Values are generated with R

In case of repetitive pulses, T
must not exceed the temperature specified above for curves A and B.

=0 Ω.

L

(at beginning of each demagnetization) of every pulse

jstart

t

23/31

Package and PC board thermal data VND5160AJ-E

4 Package and PC board thermal data

4.1 PowerSSO-12™ thermal data

Figure 28. PowerSSO-12™ PC board

Note: Layout condition of R

area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm

Figure 29.

RTHj_amb(°C/W)

R

thj-amb

70

65

60

55

50

45

40

0246810

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

vs. PCB copper area in open box free air condition (one channel ON)

PCB Cu heatsink area (cm^2)

24/31

VND5160AJ-E Package and PC board thermal data

Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one

channel ON)

ZTH (°C/W)

100

Footprint

2

2 cm

8 cm

2

10

1

0,001 0,01 0,1 1 10 100 1000

Time (s)

Equation 1: pulse calculation formula

Z

THδ

R

TH

δ Z

THtp

1 δ–()+⋅=

where δ = tP/T

Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™

(a)

a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

25/31

Package and PC board thermal data VND5160AJ-E

Table 13. Thermal parameters

Area/island (cm2)Footprint28

R1= R7 (°C/W) 1.2

R2= R8 (°C/W) 6

R3 (°C/W) 3

R4 (°C/W) 8 8 7

R5 (°C/W) 22 15 10

R6 (°C/W) 26 20 15

C1= C7 (W.s/°C) 0.0008

C2= C8 (W.s/°C) 0.0016

C3 (W.s/°C) 0.0166

C4 (W.s/°C) 0.2 0.1 0.1

C5 (W.s/°C) 0.27 0.8 1

C6 (W.s/°C) 3 6 9

26/31

VND5160AJ-E Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.2 Package mechanical data

Figure 32. PowerSSO-12™ package dimensions

27/31

Package and packing information VND5160AJ-E

Table 14. PowerSSO-12™ mechanical data

Symbol

Min. Typ. Max.

A 1.250 1.620

A1 0.000 0.100

A2 1.100 1.650

B 0.230 0.410

C 0.190 0.250

D 4.800 5.000

E 3.800 4.000

e0.800

H 5.800 6.200

h 0.250 0.500

L 0.400 1.270

Millimeters

k0° 8°

X 2.200 2.800

Y 2.900 3.500

ddd 0.100

28/31

VND5160AJ-E Package and packing information

5.3 Packing information

Figure 33. PowerSSO-12™ tube shipment (no suffix)

B

A

Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”)

Base Q.ty 100

C

Bulk Q.ty 2000

Tube length (± 0.5) 532

A 1.85

B 6.75

C (± 0.1) 0.6

All dimensions are in mm.

REEL DIMENSIONS

Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm min

No componentsNo components Components

Empty components pockets
saled with cover tape.

User direction of feed

Start

500mm min

29/31

Revision history VND5160AJ-E

6 Revision history

Table 15. Document revision history

Date Revision Changes

13-Sep-2004 1 Initial release.

10-Apr-2006 2

01-Mar-2007 3

10-Dec-2007 4

12-Feb-2008 5

Layout changed.
Major update to Section 2: Electrical specifications.

Reformatted.
Contents, List of tables and List of figures added.
Added Section 3.4: Maximum demagnetization energy

(VCC = 13.5V).

®

ECOPACK

package information added.

Document reformatted and restructured.
Updated Figure 2: Configuration diagram (top view) : pins 7-12 left

unconnected (N.C) and added note.

Table 4: Absolute maximum ratings : corrected E

value from 14

MAX

to 34 mJ.
Added Figure 5: Delay response time between rising edge of ouput

current and rising edge of current sense (CS enabled).

Updated Figure 6: Iout/ Isense vs. Iout (see Table 10 for details).
Added Figure 7: Maximum current sense ratio drift vs load current.
Updated Table 10: Current sense (8V<VCC<16V) :
– changed t

DSENSE2H

– added dk1/k1, dk2/k2, dk3/k3, ∆t

max value from 300 µs to 150 µs.

, I

DSENSE2H

parameters.

OL

Table 12: Electrical transient requirements : updated test level values

III and IV for test pulse 5b and notes.
Updated Section 4.1: PowerSSO-12™ thermal data:
– changed Figure 29: Rthj-amb vs. PCB copper area in open box

free air condition (one channel ON).

– changed Figure 30: PowerSSO-12™ thermal impedance junction

ambient single pulse (one channel ON).

– Figure 31: Thermal fitting model of a double channel HSD in

PowerSSO-12™: added note.

– updated Table 13: Thermal parameters:

R3 value changed from 7 to 3 °C/W.
R4 values changed from 10 /10 /9 to 8 /8 /7 °C/W.
C3 value changed from 0.05 to 0.0166 W.s/°C.

Corrected typing error in Table 10: Current sense (8V<VCC<16V) :
changed I

test condition from VIN = 0V to VIN = 5V.

OL

30/31

VND5160AJ-E

Please Read Carefully:

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31/31