Datasheet VND5050J-E, VND5050K-E Datasheet (ST)

Features

VND5050J-E

VND5050K-E

Double channel high side driver

for automotive applications

Max supply voltage V

Operating voltage range V

Max on-State resistance (per ch.)

Current limitation (typ) I

Off-state supply current I

1. Typical value with all loads connected.

■ Main

– Inrush current active management by

power limitation
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC

European directive

■ Diagnostic functions

– Open drain status output
– On-state open load detection
– Off-state open load detection
– Thermal shutdown indication

■ Protections

– Undervoltage shutdown
– Overvoltage clamp
– Output stuck to V
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss

of V

CC

– Thermal shutdown

Table 1. Device summary

Package

detection

CC

CC

CC

R

ON

LIMH

S

41 V

4.5 to 36 V

50 mΩ

18 A

(1)

2µA

PowerSSO-24PowerSSO-12

– Reverse battery protection (see Figure 28)
– Electrostatic discharge protection

Applications

■ All types of resistive, inductive and capacitive

loads

Description

The VND5050K-E and VND5050J-E are
monolithic devices made using
STMicroelectronics VIPower M0-5 technology.
they are intended for driving resistive or inductive
loads with one side connected to ground. Active
V

pin voltage clamp protects the devices

CC

against low energy spikes (see ISO7637 transient
compatibility table). The devices detect open load
condition both in on and off-state, when
STAT_DIS is left open or driven low. Output
shorted to V

When STAT_DIS is driven high, STATUS pin is in
high impedance state.

Output current limitation protects the devices in
overload condition. In case of long overload
duration, the devices limit the dissipated power to
a safe level up to thermal shutdown intervention.
Thermal shutdown with automatic restart allows
the devices to recover normal operation as soon
as fault conditions disappear.

Tub e Tap e a nd reel

is detected in the off-state.

CC

Order code

PowerSSO-12 VND5050J-E VND5050JTR-E

PowerSSO-24 VND5050K-E VND5050KTR-E

July 2009 Doc ID 12266 Rev 6 1/37

www.st.com

1

Contents VND5050J-E / VND5050K-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20

3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20

3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3 PowerSSO-24™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.4 PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.5 PowerSSO-24™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E List of tables

List of tables

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7. Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 8. Status pin (V

Table 9. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10. Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 11. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 13. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 14. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 15. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 16. PowerSSO-12™ thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 17. PowerSSO-24™ thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 18. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 19. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

=0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SD

Doc ID 12266 Rev 6 3/37

List of figures VND5050J-E / VND5050K-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 14. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 15. On-state resistance vs T

Figure 16. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 17. On-state resistance vs V

Figure 18. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 19. Openload on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 20. Openload off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 21. I

LIM

vs T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

case

Figure 22. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 23. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 24. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 25. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 26. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 27. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 28. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 29. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 30. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23

Figure 31. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 32. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 24

Figure 33. PowerSSO-12™ thermal impedance junction ambient single pulse (one channel on). . . . 25

Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25

Figure 35. PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 36. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 27

Figure 37. PowerSSO-24™ thermal impedance junction ambient single pulse (one channel on). . . . 28

Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 28

Figure 39. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 40. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 41. PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 42. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 43. PowerSS0-24™
Figure 44. PowerSSO-24™

tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CC

4/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

CC

V

GND

INPUT1

STATUS1

STAT_DIS

INPUT2

STATUS2

CC

CLAMP

OVE RTE MP. 1

LOGIC

UNDERVOLTAGE

CLAMP 1

DRIVER 1

CURRENT LIMITER 1

OPENLOAD ON 1

OUTPUT1

OPENLOAD OFF 1

PWR

1

LIM

Table 2. Pin function

Name Function

V

CC

Battery connection.

OUTPUTn Power output.

GND

INPUTn

Ground connection. Must be reverse battery protected by an external diode/resistor
network.

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.

STATUSn Open drain digital diagnostic pin.

STAT_DIS

Active high CMOS compatible pin, to disable the STATUS pin.

INPUT2

CONTROL & PROTECTION
EQUIVALENT TO

STATUS2

CHANNEL1

V

CC

OUTPUT2

Doc ID 12266 Rev 6 5/37

Block diagram and pin description VND5050J-E / VND5050K-E

Figure 2. Configuration diagram (top view)

TA B = V

GND

STAT_DIS

INPUT 1

STATUS 1
STATUS 2

INPUT 2

cc

1
2
3
4
5

6

12
11
10

9
8
7

V

cc

OUTPUT 1
OUTPUT 1
OUTPUT 2
OUTPUT 2
V

cc

V

GND.

N.C.

STAT_DIS

INPUT1

STATUS1

N.C.

STATUS2

N.C.

INPUT2

N.C.

V

CC

CC

OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2

TAB = V

CC

PowerSSO-12

Table 3. Suggested connections for unused and not connected pins

PowerSSO-24

Connection/pin STATUS N.C. OUTPUT INPUT STAT_DIS

Floating X X X X X

To ground N.R.

1. Not recommended.

(1)

XN.R.

Through 10KΩ

resistor

Through 10KΩ

resistor

6/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I

S

V

CC

V

CC

Fn

V

I

SD

V

SD

I

INn

INPUTn

V

INn

Note: V

Fn

= V

OUTn

- V

during reverse battery condition.

CCn

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

GND

OUTPUTnSTAT_DIS

STATUSn

I

GND

I

OUTn

I

STATn

V

STATn

V

OUTn

V

- V

- I

I

OUT

- I

I

STAT

I

STAT_DIS

E

DC supply voltage 41 V

CC

Reverse DC supply voltage 0.3 V

CC

DC reverse ground pin current 200 mA

GND

DC output current Internally limited A

Reverse dc output current 15 A

OUT

DC input current +10 / -1 mA

I

IN

DC status current +10 / -1 mA

DC status disable current +10 / -1 mA

Maximum switching energy

MAX

(L=3mH; RL=0Ω; V

=13.5V; T

bat

jstart

=150ºC; I

OUT

= I

limL

(Typ.))

104 mJ

Doc ID 12266 Rev 6 7/37

Electrical specifications VND5050J-E / VND5050K-E

Table 4. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)

– Input

ESD

– Status

V

–STAT_DIS
– Output
–V

CC

V

Charge device model (CDM-AEC-Q100-011) 750 V

ESD

T

Junction operating temperature -40 to 150 °C

j

4000
4000
4000
5000
5000

V
V
V
V
V

T

Storage temperature - 55 to 150 °C

stg

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter

R

thj-case

R

thj-amb

Thermal resistance junction case (max)
(with one channel on)

Thermal resistance junction ambient
(max)

2.3 Electrical characteristics

8V<VCC<36 V; -40 °C<Tj<150 °C, unless otherwise specified.

.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

USD

V

USDhyst

Operating supply voltage 4.5 13 36 V

CC

Undervoltage shutdown 3.5 4.5 V

Undervoltage shutdown
hysteresis

Value

Unit

PowerSSO-12 PowerSSO-24

2.8 2.8 °C/W

See Figure 32 See Figure 36 °C/W

0.5 V

I

R

On-state resistance

ON

(2)

I
I

V

clamp

Clamp voltage IS=20mA 41 46 52 V

Off-state; V

S

Supply current

I

VIN=V
On-state; V

I

8/37 Doc ID 12266 Rev 6

=2A; Tj=25°C

OUT

=2A; Tj=150°C

OUT

=2A; VCC=5V; Tj=25°C

OUT

=13V; Tj=25°C;

CC

OUT=VSENSE=VCSD

=13V; VIN=5V;

CC

=0A

OUT

=0V

50

mΩ

100

mΩ

65

mΩ

(1)

(1)

5

2

3

6µAmA

VND5050J-E / VND5050K-E Electrical specifications

Table 6. Power section (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

L(off1)

I

L(off2)

V

Off-state output
current

Off-state output
current

Output - VCC diode

F

voltage

(2)

(2)

(2)

VIN=V

=25°C

T

j

VIN=V

=125°C

T

j

VIN=0V; V

-I

OUT

=0V; VCC=13V;

OUT

000.01 3

=0V; VCC=13V;

OUT

=4V -75 0

OUT

5

=4A; Tj=150°C 0.7 V

1. PowerMOS leakage included.

2. For each channel.

Table 7. Switching (VCC=13V; Tj= 25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

dV

dV

t

d(on)

t

d(off)

OUT

OUT

W

W

/dt

/dt

ON

OFF

Turn-on delay time RL= 6.5Ω (see Figure 5)20µs

Turn-off delay time RL= 6.5Ω (see Figure 5)40µs

Turn-on voltage slope RL= 6.5Ω See Figure 22 V/µs

(on)

Turn-off voltage slope RL= 6.5Ω See Figure 24 V/µs

(off)

Switching energy losses
during t

won

Switching energy losses
during t

woff

RL= 6.5Ω (see Figure 5)0.21mJ

RL= 6.5Ω (see Figure 5)0.28mJ

µA

Table 8. Status pin (VSD=0V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

STAT

I

LSTAT

C

STAT

V

Status low output
voltage

Status leakage current

Status pin input
capacitance

Status clamp voltage

SCL

= 1.6 mA, VSD=0V 0.5 V

I

STAT

Normal operation or V

= 5V

V

STAT

SD

=5V,

Normal operation or VSD=5V,
V

= 5V

STAT

= 1mA

I

STAT

I

STAT

= -1mA

5.5

-0.7

10 µA

100 pF

7V

V

Doc ID 12266 Rev 6 9/37

Electrical specifications VND5050J-E / VND5050K-E

Table 9. Protections

(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

limH

I

limL

T

TSD

T

T

RS

T

HYST

t

SDL

V

DEMAG

V

ON

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

DC short circuit current

Short circuit current
during thermal cycling

Shutdown temperature 150 175 200 °C

Reset temperature

R

Thermal reset of STATUS 135 °C

Thermal hysteresis
(T

TSD-TR

)

Status delay in overload
conditions

Turn-off output voltage
clamp

Output voltage drop
limitation

VCC=13V
5V<VCC<36V

=13V

V

CC

TR<Tj<T

T

I

OUT

I

OUT

T

TSD

(see Figure 4)20µs

j>TTSD

=2A; VIN=0; L=6mH

= 0.1A;

= -40°C...+150°C

j

(see Figure 6)

12 18 24

24

7A

TRS + 1 TRS + 5

7°C

VCC-41 VCC-46 VCC-52

25 mV

A
A

°C

V

Table 10. Openload detection

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

OL

t

DOL(on)

Openload on-state
detection threshold

Openload on-state
detection delay

= 5V,8V<VCC<18V 10

V

IN

I

= 0A, VCC=13V

OUT

(see Figure 4)

See

Figure 19

70 mA

200 µs

Delay between INPUT

t

POL

falling edge and STATUS
rising edge in Openload

= 0A (see Figure 4) 200 500 1000 µs

I

OUT

condition

Openload off-state

V

voltage detection

OL

V

= 0V, 8V<VCC<16V 2

IN

threshold

See

Figure 20

4V

Output short circuit to

t

DSTKON

V

detection delay at

CC

(see Figure 4)180t

POL

µs

turn-off

Table 11. Logic input

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

Input low level 0.9 V

IL

Low level input current VIN =0.9 V 1 µA

IL

10/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Electrical specifications

Table 11. Logic input (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

V

I(hyst)

V

ICL

V

SDL

I

SDL

V

SDH

I

SDH

V

SD(hyst)

V

SDCL

Input high level 2.1 V

IH

High level input current VIN = 2.1 V 10 µA

IH

Input hysteresis voltage 0.25 V

Input clamp voltage

STAT_DIS low level
voltage

Low level STAT_DIS
current

STAT_DIS high level
voltage

High level STAT_DIS
current

STAT_DIS hysteresis
voltage

STAT_DIS clamp voltage

Figure 4. Status timings

I

= 1mA

IN

= -1mA

I

IN

V

= 0.9 V 1 µA

SD

5.5

-0.7

2.1 V

= 2.1 V 10 µA

V

SD

0.25 V

ISD= 1mA

= -1mA

I

SD

5.5

-0.7

7V

V

0.9 V

7V

V

OPEN LOAD STATUS TIMING (without external pull-up)

I

< I

OUT

I

OUT

> I

OL

OL

V

t

CC

V

t

DSTKON

OUT

POL

OUT

< V

> V

OL

OL

V

IN

V

STAT

t

DOL(on)

OUTPUT STUCK TO V

V

IN

V

STAT

t

DOL(on)

OPEN LOAD STATUS TIMING (with external pull-up)

I

< I

OUT

V

V

IN

STAT

t

DOL(on)

OL

V

OUT

> V

OL

OVER TEMP STATUS TIMING

Tj > T

V

V

IN

STAT

t

SDL

TSD

t

SDL

Doc ID 12266 Rev 6 11/37

Electrical specifications VND5050J-E / VND5050K-E

Table 12. Truth table

Conditions Input Output Sense (V

Normal operation

L
H

L
H

CSD

H
H

=0V)

(1)

Current limitation

Over temperature

Undervoltage

Output voltage > V

Output current < I

1. If the V
and external circuit.

is high, the SENSE output is at a high impedance, its potential depends on leakage currents

CSD

OL

OL

L
H

L
H

L
H

L
H

L
H

L
X

L
L

L
L

H
H

L
H

2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.

3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.

Figure 5. Switching characteristics

V

OUT

90%

t

f

dV

OUT

dV

OUT

/dt

(on)

80%

t

r

10%

/dt

(off)

H

H
H

H
L

X
X

(2)

L

H

(3)

L

t

INPUT

t

d(on)

12/37 Doc ID 12266 Rev 6

t

d(off)

t

VND5050J-E / VND5050K-E Electrical specifications

Figure 6. Output voltage drop limitation

Vcc-V

out

Tj=150oC

V

on

Von/R

on(T)

Table 13. Electrical transient requirements (part 1/3)

ISO 7637-2:

2004(E)

test pulse

Test levels

III IV

(1)

Number of

pulses or

test times

T

=25oC

j

T

=-40oC

j

I

out

Burst cycle/pulse

repetition time

1 -75V -100V 5000 pulses 0.5 s 5 s 2 ms, 10 Ω

2a +37V +50V 5000 pulses 0.2 s 5 s 50 μs, 2 Ω

3a -100V -150V 1h 90 ms 100 ms 0.1 μs, 50 Ω

3b +75V +100V 1h 90 ms 100 ms 0.1 μs, 50 Ω

4-6V-7V1 pulse

5b

(2)

+65V +87V 1 pulse 400 ms, 2 Ω

Delays and
Impedance

100 ms, 0.01

Ω

Table 14. Electrical transient requirements (part 2/3)

ISO 7637-2:

Test level results

2004(E)

test pulse

III IV

1C C

2a C C

3a C C

3b C C

4C C

(2)

5b

1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

CC

Doc ID 12266 Rev 6 13/37

(1)

Electrical specifications VND5050J-E / VND5050K-E

Table 15. Electrical transient requirements (part 3/3)

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

E

One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.

14/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Electrical specifications

Figure 7. Waveforms

NORMAL OPERATION

INPUT

STAT_DIS

LOAD CURRENT

STATUS

UNDERVOLTAGE

V

V

CC

INPUT
STAT_DIS

LOAD CURRENT

STATUS

INPUT

STAT_DIS

LOAD VOLTAGE

STATUS

V

USD

OPEN LOAD with external pull-up

V

OL

USDhyst

undefined

V

OUT>VOL

OPEN LOAD without external pull-up

INPUT

STAT_DIS

LOAD VOLTAGE

I

LOAD CURRENT

STATUS

OUT<IOL

t

POL

RESISTIVE SHORT TO Vcc, NORMAL LOAD

INPUT

STAT_DIS

LOAD VOLTAGE

I

OUT>IOL

V

OUT>VOL

V

OL

STATUS

t

DSTKON

OVERLOAD OPERATION

T

TSD

T

j

T

R

T

RS

INPUT

STAT_DIS

LOAD CURRENT

I
I

LIMH
LIML

STATUS

current

limitation

power
limitation

SHORTED LOAD NORMAL LOAD

thermal cycling

Doc ID 12266 Rev 6 15/37

Electrical specifications VND5050J-E / VND5050K-E

2.4 Electrical characteristics curves

Figure 8. Off-state output current Figure 9. High level input current

Iloff1 (uA)

1

0.875

0.75

0.625

0.5

0.375

0.25

0.125

0

-50 - 25 0 25 50 75 100 125 150 175

Off state

Vcc=13V

Vin=Vout=0V

Tc ( °C )

Figure 10. Input clamp voltage Figure 11. Input high level

Vicl (V)

8

7.75

7.5

7.25

7

lin=1mA

lih (uA)

5

4.5

4

3.5

3

2.5

2

1.5

0.5

0

Vin=2.1V

1

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Vih (V)

4

3.5

3

2.5

2

6.75

6.5

6.25

6

-50 -25 0 25 5 0 75 100 125 150 175

Tc (°C )

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Figure 12. Input low level Figure 13. Input hysteresis voltage

Vil (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Vihyst (V)

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

16/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Electrical specifications

Figure 14. Status low output voltage Figure 15. On-state resistance vs T

Vstat (V)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Istat=1.6mA

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Ron (mOhm)

100

90

80

70

60

50

40

30

20

10

0

-50 -25 0 25 50 75 100 125 150 175

Iout=2A

Vcc=13V

Tc ( °C )

Figure 16. Status leakage current Figure 17. On-state resistance vs V

Ilstat (uA)

0.055

0.05

Vstat=5V

0.045

0.04

0.035

0.03

0.025

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Ron (mOhm)

100

90

80

70

60

50

40

30

20

10

0

0 5 10 15 20 25 30 35 40

Tc= 150°C

Tc= 125°C

Tc= 25°C

Tc= -40°C

Vcc (V)

case

CC

Figure 18. Status clamp voltage Figure 19. Openload on-state detection

threshold

Vscl (V)

9

8.5

7.5

6.5

5.5

4.5

Istat=1mA

8

7

6

5

4

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Doc ID 12266 Rev 6 17/37

Iol (mA)

100

90

80

70

60

50

40

30

20

10

0

Vin=5V

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Electrical specifications VND5050J-E / VND5050K-E

Figure 20. Openload off-state voltage

Figure 21. I

LIM

vs T

case

detection threshold

Vol (V)

5

4.5

4

3.5

3

2.5

2

1.5

1

Vin=0V

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Ilimh (A)

25

22.5

20

17.5

15

12.5

10

7.5

5

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Figure 22. Turn-on voltage slope Figure 23. Undervoltage shutdown

dVout/dt(on) (V/ms)

1000

900

800

700

600

500

400

300

200

100

Vcc=13V

RI=6.5Ohm

0

-50 - 25 0 25 50 75 100 125 150 175

Tc ( °C )

Vusd (V)

14

12

10

8

6

4

2

0

-50 -25 0 25 50 7 5 100 125 150 175

Tc ( °C )

Figure 24. Turn-off voltage slope Figure 25. STAT_DIS clamp voltage

dVout/dt(off) (V/ms)

1000

900

800

700

600

500

400

300

200

100

Vcc=13V

RI=6.5Ohm

0

-50 - 25 0 25 50 75 100 125 150 175

Tc ( °C )

18/37 Doc ID 12266 Rev 6

Vsdcl(V)

14

12

Isd=1mA

10

8

6

4

2

0

-50 -25 0 25 50 7 5 100 125 150 175

Tc ( °C )

VND5050J-E / VND5050K-E Electrical specifications

Figure 26. High level STAT_DIS voltage Figure 27. Low level STAT_DIS voltage

Vsdh(V)

8

Vsdl(V)

8

7

6

5

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C)

7

6

5

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C)

Doc ID 12266 Rev 6 19/37

Application information VND5050J-E / VND5050K-E

3 Application information

Figure 28. Application schematic

+5V

μ

R

R

C

R

prot

prot

prot

+5V

STAT_DIS

INPUT

STATUS

V

CC

OUTPUT

GND

R

GND

GND

D

GND

V

Note: Channel 2 has the same internal circuit as channel 1.

3.1 GND protection network against reverse battery

D

ld

3.1.1 Solution 1: resistor in the ground line (R

This can be used with any type of load.

The following is an indication on how to dimension the R

1. R

2. R

where -I
maximum rating section of the device datasheet.

Power Dissipation in R

P

= (-VCC)2/R

D

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the
R

GND

values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R

20/37 Doc ID 12266 Rev 6

≤ 600mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

S(on)max

GND

GND

).

)

(when VCC<0: during reverse battery situations) is:

GND

will produce a shift (I

S(on)max

* R

GND

GND

only)

GND

resistor.

GND

S(on)max

becomes the sum of the

) in the input thresholds and the status output

.

VND5050J-E / VND5050K-E Application information

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).

3.1.2 Solution 2: a diode (D

A resistor (R

=1kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V

max DC rating. The same applies if the device is subject to transients on the VCC line

CC

that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 Microcontroller I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of μC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of μC
I/Os.

if the device drives an

GND

prot

) in line to

-V

CCpeak/Ilatchup

≤ R

prot

≤ (V

OHμC-VIH-VGND

Calculation example:

For V

5kΩ ≤ R

Recommended values: R

CCpeak

prot

≤ 180kΩ

= - 100V and I

latchup

prot

≥ 20mA; V

=10kΩ.

3.4 Open-load detection in off-state

Off-state open load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (V
microprocessor.

The external resistor has to be selected according to the following requirements:

1. no false open load indication when load is connected: in this case we have to avoid

V

to be higher than V

OUT

V

=(VPU/(RL+RPU))RL<V

OUT

2. no misdetection when load is disconnected: in this case the V

V

; this results in the following condition RPU<(VPU–V

OLmax

; this results in the following condition

Olmin

Olmin

Doc ID 12266 Rev 6 21/37

) / I

IHmax

≥ 4.5V

OHμC

) like the +5V line used to supply the

PU

.

has to be higher than

OUT

OLmax

)/I

L(off2)

.

Application information VND5050J-E / VND5050K-E

Because I
up resistor R

may significantly increase if V

s(OFF)

should be connected to a supply that is switched OFF when the module is in

PU

standby.

The values of V

OLmin

, V

OLmax

and I

are available in the Electrical Characteristics

L(off2)

section.

Figure 29. Open-load detection in off-state

V

CC

INPUT

STATUS

DRIVER

+

LOGIC

+

-

VOL

GROUND

is pulled high (up to several mA), the pull-

out

V batt. VPU

R

PU

I

L(off2)

OUT

R

R

L

22/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Application information

3.5 Maximum demagnetization energy (VCC = 13.5V)

Figure 30. Maximum turn-off current versus inductance (for each channel)

100

A

B

10

I (A)

1

0,1 1 10 100

C

L (mH)

A: T

B: T

C: T

VIN, I

L

Note: Values are generated with R

= 150°C single pulse

jstart

= 100°C repetitive pulse

jstart

= 125°C repetitive pulse

jstart

demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.

Demagnetization Demagnetization Demagnetization

=0 Ω.In case of repetitive pulses, T

L

(at beginning of each

jstart

t

Doc ID 12266 Rev 6 23/37

Package and PCB thermal data VND5050J-E / VND5050K-E

4 Package and PCB thermal data

4.1 PowerSSO-12™ thermal data

Figure 31. PowerSSO-12™ PC board

Note: Layout condition of R

area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70μm (front and back side),
Copper areas: from minimum pad lay-out to 8cm

Figure 32. R

thj-amb

on)

RTHj_amb(°C/ W)

70

65

60

55

50

45

40

35

30

0246810

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

vs PCB copper area in open box free air condition (one channel

PCB Cu heatsink area (cm^ 2)

24/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Package and PCB thermal data

Figure 33. PowerSSO-12™ thermal impedance junction ambient single pulse (one

channel on)

ZTH (°C/ W)

100

Footprint

2 cm

8 cm

2

2

10

1

0,1

0,0001 0,001 0,01 0,1 1 10 100 1000

Time ( s)

Equation 1: pulse calculation formula

Z

THδ

where δ = t

Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-12™

R

TH

/T

P

δ Z

THtp

1 δ–()+⋅=

(a)

a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Doc ID 12266 Rev 6 25/37

Package and PCB thermal data VND5050J-E / VND5050K-E

Table 16. PowerSSO-12™ thermal parameters

Area/island (cm2)Footprint28

R1= R7 (°C/W) 0.7

R2= R8 (°C/W) 2.8

R3 (°C/W) 4

R4 (°C/W) 8 8 7

R5 (°C/W) 22 15 10

R6 (°C/W) 26 20 15

C1= C7 (W.s/°C) 0.001

C2= C8 (W.s/°C) 0.0025

C3 (W.s/°C) 0.05

C4 (W.s/°C) 0.2 0.1 0.1

C5 (W.s/°C) 0.27 0.8 1

C6 (W.s/°C) 3 6 9

26/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Package and PCB thermal data

4.2 PowerSSO-24™ thermal data

Figure 35. PowerSSO-24™ PC board

Note: Layout condition of R

area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm

Figure 36. R

thj-amb

on)

RTHj_amb(°C/W)

55

50

45

40

35

30

0246810

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

vs PCB copper area in open box free air condition (one channel

PCB Cu heatsink area (cm^2)

Doc ID 12266 Rev 6 27/37

Package and PCB thermal data VND5050J-E / VND5050K-E

Figure 37. PowerSSO-24™ thermal impedance junction ambient single pulse (one

channel on)

Equation 2: pulse calculation formula

Z

THδ

where δ = t

Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-24™

b. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded

R

TH

/T

P

δ Z

THtp

1 δ–()+⋅=

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

(b)

28/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Package and PCB thermal data

Table 17. PowerSSO-24™ thermal parameters

Area/island (cm2)Footprint28

R1=R7 (°C/W) 0.4

R2=R8 (°C/W) 2

R3 (°C/W) 6

R4 (°C/W) 7.7

R5 (°C/W) 9 9 8

R6 (°C/W) 28 17 10

C1=C7 (W.s/°C) 0.001

C2=C8 (W.s/°C) 0.0022

C3 (W.s/°C) 0.025

C4 (W.s/°C) 0.75

C5 (W.s/°C) 1 4 9

C6 (W.s/°C) 2.2 5 17

Doc ID 12266 Rev 6 29/37

Package and packing information VND5050J-E / VND5050K-E

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com

ECOPACK

®

is an ST trademark.

5.2 PowerSSO-12™ package information

Figure 39. PowerSSO-12™ package dimensions

.

30/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Package and packing information

Table 18. PowerSSO-12™ mechanical data

Symbol

Min. Typ. Max.

A 1.25 1.62

A1 0 0.1

A2 1.10 1.65

B 0.23 0.41

C 0.19 0.25

D4.8 5.0

E3.8 4.0

e0.8

H5.8 6.2

h 0.25 0.5

L 0.4 1.27

Millimeters

k0° 8°

X1.9 2.5

Y3.6 4.2

ddd 0.1

Doc ID 12266 Rev 6 31/37

Package and packing information VND5050J-E / VND5050K-E

5.3 PowerSSO-24™ package information

Figure 40. PowerSSO-24™ package dimensions

Table 19. PowerSSO-24™ mechanical data

Millimeters

Symbol

Min. Typ. Max.

A 2.45

A2 2.15 2.35

a1 0 0.1

b 0.33 0.51

c 0.23 0.32

D 10.10 10.50

E7.4 7.6

e0.8

e3 8.8

F2.3

G 0.1

H 10.1 10.5

32/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Package and packing information

Table 19. PowerSSO-24™ mechanical data (continued)

Symbol

Min. Typ. Max.

h 0.4

k 0deg 8deg

L 0.55 0.85

O1.2

Q0.8

S2.9

T3.65

U1.0

N 10deg

X4.1 4.7

Y6.5 7.1

Millimeters

Doc ID 12266 Rev 6 33/37

Package and packing information VND5050J-E / VND5050K-E

5.4 PowerSSO-12™ packing information

Figure 41. PowerSSO-12™ tube shipment (no suffix)

B

C

Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532

A

A1.85
B6.75
C (± 0.1) 0.6

All dimensions are in mm.

Figure 42. PowerSSO-12™ tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

End

Start

Top

cover

tape

500mm min

Empty components pockets
saled with cover tape.

User direction of feed

No componentsNo components Components

500mm min

34/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E Package and packing information

5.5 PowerSSO-24™ packing information

Figure 43. PowerSS0-24™ tube shipment (no suffix)

Base Qty 49

C

B

A

Figure 44. PowerSSO-24™

tape and reel shipment (suffix “TR”)

Bulk Qty 1225
Tube length (±0.5) 532
A 3.5
B 13.8
C (±0.1) 0.6

All dimensions are in mm.

REEL DIMENSIONS

Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (± 0.1) 2

End

All dimensions are in mm.

Start

Top

cover

tape

500mm min

Empty components pockets
sealed with cover tape.

User direction of feed

No componentsNo components Components

500mm min

Doc ID 12266 Rev 6 35/37

Revision history VND5050J-E / VND5050K-E

6 Revision history

Table 20. Document revision history

Date Revision Changes

30-Mar-2006 1 Initial release.

11-Jan-2007 2

31-May-2007 3

03-Dec-2007 4

17-Jun-2009 5

22-Jul-2009 6

Minor formatting changes.
New disclaimer attached.

Reformatted and restructured.
Contents and lists of tables and figures added.

Section 3.5: Maximum demagnetization energy (VCC = 13.5V)

added.

Table 4: Absolute maximum ratings: E

MAX entries updated.

Table 13: Electrical transient requirements (part 1/3):Test level

values III and IV for test pulse 5b and notes updated

Figure 34: Thermal fitting model of a double channel HSD in
PowerSSO-12™, Figure 38: Thermal fitting model of a double
channel HSD in PowerSSO-24™: added notes.

Features table updated: I

changed from 19 to 18A.

LIMH

Updated Section 4.1: PowerSSO-12™ thermal data:
– Changed Figure 32: Rthj-amb vs PCB copper area in open

box free air condition (one channel on).

– Changed Figure 33: PowerSSO-12™ thermal impedance

junction ambient single pulse (one channel on).

– Updated Table 16: PowerSSO-12™ thermal parameters:

R3 value changed from 7 to 4 °C/W.
R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W.

Table 19: PowerSSO-24™ mechanical data:

– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F and k rows

Updated Figure 40: PowerSSO-24™ package dimensions.
Updated Table 19: PowerSSO-24™ mechanical data:
– Deleted G1 row
– Added O, Q, S, T and U rows.

36/37 Doc ID 12266 Rev 6

VND5050J-E / VND5050K-E

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Doc ID 12266 Rev 6 37/37