Datasheet VND5012AK-E Datasheet (ST)

Features

VND5012AK-E

Double channel high side driver with analog current sense

for automotive applications

Max supply voltage V

Operating voltage range V

Max on-state resistance (per ch.)

Current limitation (typ) I

Off-state supply current (typ.) I

1. Typical value with all loads connected.

■ General features

– Inrush current active management by

power limitation
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC

european directive

■ Diagnostic functions

– Proportional load current sense
– High current sense precision for wide range

currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage

■ Protections

– Undervoltage shutdown
– Overvoltage clamp
– Output stuck to Vcc detection
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss

of V

CC

– Thermal shutdown

Table 1. Device summary

Package

PowerSSO-24 VND5012AK-E VND5012AKTR-E

CC

CC

R

ON

LIMH

S

41 V

4.5 to 36 V

12 mΩ

60 A

(1)

2µA

PowerSSO-24

– Reverse battery protection (see Application

schematic)

– Electrostatic discharge protection

Application

■ All types of resistive, inductive and capacitive

loads

Description

The VND5012AK-E a monolithic device made
using STMicroelectronics VIPower M0-5
technology. It is intended for driving resistive or
inductive loads with one side connected to
ground. Active V
device against low energy spikes (see ISO7637
transient compatibility table). This device
integrates an analog current sense which delivers
a current proportional to the load current
(according to a known ratio) when CS_DIS is
driven low or left open. When CS_DIS is driven
high, the CURRENT SENSE pin is in a high
impedance condition. Output current limitation
protects the device in overload condition. In case
of long overload duration, the device limits the
dissipated power to safe level up to thermal
shutdown intervention. Thermal shutdown with
automatic restart allows the device to recover
normal operation as soon as fault condition
disappears.

Order codes

Tub e Tap e a nd reel

pin voltage clamp protects the

CC

December 2009 Doc ID 12285 Rev 7 1/31

www.st.com

1

Contents VND5012AK-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1 GND Protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21

3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21

3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2 PowerSSO-24 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3 PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31 Doc ID 12285 Rev 7

VND5012AK-E List of tables

List of tables

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7. Switching (VCC=13V; Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 8. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10. Current sense (8V<V

Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 13. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 14. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 15. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CC

Doc ID 12285 Rev 7 3/31

List of figures VND5012AK-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Delay response time between rising edge of output current and rising edge of current

sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. I

OUT/ISENSE

Figure 7. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 17. On-state resistance vs T
Figure 18. On-state resistance vs V

Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 20. I

LIMH

vs T

Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 27. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23

Figure 28. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 24

Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 25

Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . . 25

Figure 32. PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 33. PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 34. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

vs I

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

OUT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4/31 Doc ID 12285 Rev 7

VND5012AK-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

CC

Pwr

LIM

UNDERVOLTAGE

DRIVER 1

Pwr

1

LIM

OVERTEMP. 1

I

OUT1

2

PwCLAMP 1

K 1

I

V

DSLIM

LIM

1

1

DRIVER 2

I

OUT2

PwCLAMP 2

OVERTEMP. 2

K 2

V

CC

CLAMP

GND

INPUT1

INPUT2

CS_DIS

Table 2. Pin function

LOGIC

Name Function

V

CC

OUTPUT

GND

INPUT

CURRENT

SENSE

Battery connection.

Power output.

1,2

Ground connection. Must be reverse battery protected by an external diode/resistor
network.

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output

1,2

switch state.

Analog current sense pin, delivers a current proportional to the load current.

1,2

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

V

I

LIM

DSLIM

OUTPUT1

CURRENT
SENSE1

OUTPUT2

2

2

CURRENT
SENSE2

Doc ID 12285 Rev 7 5/31

Block diagram and pin description VND5012AK-E

Figure 2. Configuration diagram (top view)

V

CC

GND

N.C.

INPUT2

N.C.

INPUT1

N.C.

CURRENT SENSE1

N.C.

CURRENT SENSE2

CS_DIS

V

CC

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1

TAB = V

Table 3. Suggested connections for unused and not connected pins

Connection / pin Current Sense N.C. Output Input CS_DIS

Floating Not allowed X X X X

To ground

Through 1 KΩ

resistor

X Not allowed

Through 10 KΩ

CC

resistor

Through 10 KΩ

resistor

6/31 Doc ID 12285 Rev 7

VND5012AK-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I

S

V

CC

I

I

CSD

V

CSD

I

IN1

V

IN1

I

IN2

V

IN2

CS_DIS

INPUT1

INPUT2

GND

OUTPUT1

CURRENT
SENSE1

OUTPUT2

CURRENT
SENSE2

I

GND

OUT1

I

SENSE1

I

OUT2

I

SENSE2

V

SENSE2

V

OUT2

V

SENSE1

VF (*)

V

OUT1

V

CC

Note: V

Fn

= V

- VCC during reverse battery condition.

OUTn

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

DC supply voltage 41 V

CC

Reverse DC supply voltage 0.3 V

CC

DC reverse ground pin current 200 mA

GND

DC output current Internally limited A

Reverse DC output current -30 A

OUT

DC Input current -1 to 10 mA

I

IN

-V

-I

I

-I

V

OUT

I

CSD

-I

CSENSE

V

CSENSE

DC current sense disable input current -1 to 10 mA

DC reverse CS pin current 200 mA

V

Current sense maximum voltage

CC

+V

-41

CC

V
V

Doc ID 12285 Rev 7 7/31

Electrical specifications VND5012AK-E

Table 4. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Maximum switching energy

E

V

V

MAX

(L=1.25 mH; R

= I

I

OUT

limL

(Typ.))

=0 Ω; V

L

=13.5 V; T

bat

jstart

=150 °C;

Electrostatic discharge
(Human body model: R= 1.5 KΩ; C= 100 pF)
– INPUT
– CURRENT SENSE

ESD

–CS_DIS
–OUTPUT
–V

CC

Charge device model (CDM-AEC-Q100-011) 750 V

ESD

Junction operating temperature -40 to 150 °C

T

j

508 mJ

4000
2000
4000
5000
5000

V
V
V
V
V

T

stg

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter Max value Unit

R

thj-case

R

thj-amb

Storage temperature -55 to 150 °C

Thermal resistance junction-case (max) (With one
channel on)

0.4 °C/W

Thermal resistance junction-ambient (max) See Figure 29 °C/W

8/31 Doc ID 12285 Rev 7

VND5012AK-E Electrical specifications

2.3 Electrical characteristics

8V<VCC<36V; -40°C<Tj<150°C, unless otherwise specified.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

USD

V

USDhyst

R

V

clamp

I

L(off)

V

Operating supply voltage 4.5 13 36 V

CC

Undervoltage shutdown 3.5 4.5 V

Undervoltage shutdown
hysteresis

On-state resistance

ON

Clamp voltage IS=20mA 41 46 52 V

I

Supply current

S

Off-state output

(2)

current

Output VCC diode
voltage

(2)

F

1. PowerMOS leakage included.

2. For each channel.

I

=5A; Tj=25°C

OUT

(2)

=5A; Tj=150°C

I

OUT

I

=5A; VCC=5V; Tj=25°C

OUT

Off-state; V
V

IN=VOUT=VSENSE=VCSD

CC

On-state; VCC=13V; VIN=5V;

=0A

I

OUT

VIN=V
V

IN=VOUT

=0V; VCC=13V; Tj=25°C

OUT

=0V; VCC=13V;

Tj=125°C

-I

= 8A; Tj=150°C 0.7 V

OUT

=13V; Tj=25°C;

=0V

0.5 V

(1)

2

5

3

000.01 3

12

mΩ

24

mΩ

16

mΩ

(1)

6µAmA

5µA

Table 7. Switching (VCC=13V; Tj=25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

d(on)

t

d(off)

dV

OUT

dV

OUT

W

W

OFF

Turn-on delay time RL= 2.6 Ω (see Figure 8)20µs

Turn-off delay time RL= 2.6 Ω (see Figure 8)35µs

/dt

Turn-on voltage slope RL= 2.6 Ω See Figure 21 V/µs

(on)

/dt

Turn-off voltage slope RL= 2.6 Ω See Figure 22 V/µs

(off)

Switching energy losses

ON

during t

won

Switching energy losses
during t

woff

RL= 2.6 Ω (see Figure 8)1.1mJ

RL= 2.6 Ω (see Figure 8)0.7mJ

Doc ID 12285 Rev 7 9/31

Electrical specifications VND5012AK-E

Table 8. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

V

I

V

I(hyst)

V

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

V

CSCL

Table 9. Protections and diagnostics

Input low level voltage 0.9 V

IL

Low level input current VIN=0.9 V 1 µA

IL

Input high level voltage 2.1 V

IH

High level input current VIN=2.1 V 10 µA

IH

Input hysteresis voltage 0.25 V

Input clamp voltage

ICL

I

=1 mA

IN

=-1 mA

I

IN

5.5

-0.7

CS_DIS low level voltage 0.9 V

Low level CS_DIS current V

=0.9 V 1 µA

CSD

CS_DIS high level voltage 2.1 V

High level CS_DIS current V

CS_DIS hysteresis
voltage

CS_DIS clamp voltage

=2.1 V 10 µA

CSD

0.25 V

I

CSD

I

CSD

=1 mA
=-1 mA

(1)

5.5

-0.7

7V

7V

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

=13 V

I

limH

I

limL

T

TSD

T

T

RS

T

HYST

V

DEMAG

V

ON

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

DC short circuit current

Short circuit current
during thermal cycling

Shutdown temperature 150 175 200 °C

Reset temperature

R

Thermal reset of
STATUS

Thermal hysteresis

TSD -TR

)

(T

Turn-off output voltage
clamp

Output voltage drop
limitation

CC

5V<V

V

CC

I

OUT

<36 V

CC

=13 V TR<Tj<T

=2 A; VIN=0;

L=6 mH

I

= 0.4 A;

OUT

= -40 °C...+150 °C

T

j

(see Figure 26)

TSD

42 60 84

84

24 A

TRS + 1 TRS + 5

135 °C

7°C

VCC-41 VCC-46 VCC-52

25 mV

A
A

°C

V

10/31 Doc ID 12285 Rev 7

VND5012AK-E Electrical specifications

Table 10. Current sense (8V<VCC<16V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

K

K

dK1/K

K

I

0

OUT/ISENSE

I

1

OUT/ISENSE

Current sense ratio

(1)

1

drift

I

2

OUT/ISENSE

= 0.25 A; V

OUT

V

=0 V;

CSD

= -40°C...150°C

T

j

I

= 5 A; V

OUT

= -40°C...150°C

T

j

I

=5 A; V

OUT

= 25 °C...150 °C

T

j

= 5 A; V

I

OUT

= -40°C to 150°C

T

J

I

= 10 A; V

OUT

= -40°C...150°C

T

j

= 10 A; V

I

OUT

SENSE

SENSE

SENSE

SENSE

SENSE

Tj= 25 °C...150 °C

SENSE

=0.5 V; V

=0.5 V; V

= 0.5 V; V

=4 V; V

=4 V; V

=0.5 V;

CSD

CSD

CSD

CSD

CSD

=0 V;

=0 V;

=0 V;

=0 V;

=0 V;

2780 5580 8390

3590

5100

6630

4110

5100

6090

-8 +8 %

4400

5090

5930

4600

5090

5590

dK2/K

K

dK3/K

I

SENSE0

Current sense ratio

(1)

2

drift

I

3

OUT/ISENSE

Current sense ratio

(1)

3

drift

Analog sense
leakage current

= 10 A; V

I

OUT

= -40°C to 150°C

T

J

I

= 25 A; V

OUT

= -40°C...150°C

T

j

I

= 25 A; V

OUT

= 25 °C...150 °C

T

j

= 25 A; V

I

OUT

= -40°C to 150°C

T

J

I

=0 A; V

OUT

V
V
I

OUT

V

CSD

CSD

CSD

SENSE

=5 V; VIN=0 V; Tj=-40 °C...150 °C
=0 V; VIN=5 V; Tj=-40 °C...150 °C

=2 A; V

SENSE

=5 V; VIN=5 V; Tj=-40 °C...150 °C

SENSE

SENSE

SENSE

SENSE

= 4 V; V

=4 V; V

=4 V; V

= 4 V; V

=0 V;

=0 V;

CSD

CSD

CSD

CSD

=0 V;

=0 V;

=0 V;

=0 V;

-5 +5 %

4820

5060

5420

4860

5060

5250

-4 +4 %

0
0

0

1
2

1

µA
µA

µA

Open-load on-state
current detection

I

OL

V

= 5 V, I

IN

= 5 µA 10 45 mA

SENSE

threshold

V

SENSE

Max analog sense
output voltage

I

OUT

=15 A; V

=0 V 5 V

CSD

Analog sense

V

SENSEH

output voltage in
over temperature

V

CC

= 13 V; R

= 3.9 KΩ 9V

SENSE

condition

Analog sense

I

SENSEH

output current in
over temperature

V

CC

= 13 V; V

= 5 V 8 mA

SENSE

condition

t

DSENSE1H

Delay response
time from falling
edge of CS_DIS pin

V
I

<4 V, 1.5 A<Iout<25 A

SENSE

= 90 % of I

SENSE

(see Figure 4)

SENSE max

50 100 µs

Doc ID 12285 Rev 7 11/31

Electrical specifications VND5012AK-E

Table 10. Current sense (8V<VCC<16V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

DSENSE1L

t

DSENSE2H

Δ

t

DSENSE2H

t

DSENSE2L

Delay response
time from rising
edge of CS_DIS pin

Delay response
time from rising
edge of INPUT pin

Delay response
time between rising
edge of output
current and rising
edge of current
sense

Delay response
time from falling
edge of INPUT pin

V
I
(see Figure 4)

V
I
(see Figure 4)

V
I
I
I

V
I
(see Figure 4)

<4V, 1.5A<Iout<25A

SENSE

= 10% of I

SENSE

<4 V, 1.5 A<Iout<25 A

SENSE

= 90 % of I

SENSE

<4 V,

SENSE

=90% of I

SENSE

=90% of I

OUT

OUTMAX

= 5 A (see Figure 5)

<4 V, 1.5 A<Iout<25 A

SENSE

=10 % of I

SENSE

OUTMAX

SENSE max

SENSE max

SENSEMAX,

SENSE max

1. Parameter guaranteed by design, it is not tested.

Figure 4. Current sense delay characteristics

INPUT

CS_DIS

520µs

270 400 µs

300 µs

100 250 µs

LOAD CURRENT

SENSE CURRENT

t

DSENSE2H

t

DSENSE1L

t

DSENSE1H

t

DSENSE2L

12/31 Doc ID 12285 Rev 7

VND5012AK-E Electrical specifications

Figure 5. Delay response time between rising edge of output current and rising

edge of current sense (CS enabled)

V

IN

Δt

DSENSE2H

t

I

OUT

I

SENSE

90% I

OUTMAX

I

OUTMAX

I

SENSEMAX

t

90% I

SENSEMAX

t

Doc ID 12285 Rev 7 13/31

Electrical specifications VND5012AK-E

Figure 6. I

OUT/ISENSE

7000

6500

6000

5500

5000

4500

4000

3500

3000

510152025

vs I

OUT

max Tj = -40°C to 150°C

max Tj= 25°C to 150°C

min Tj= 25°C to 150°C

min Tj= -40°C to 150°C

typical value

Figure 7. Maximum current sense ratio drift vs load current

dk/k(%)

15

10

5

0

-5

-10

-15

5 10152025

Note: Parameter guaranteed by design; it is not tested.

I

OUT

(A)

14/31 Doc ID 12285 Rev 7

VND5012AK-E Electrical specifications

Table 11. Truth table

Conditions Input Output Sense (V

Normal operation

L
H

L

H

CSD

0

Nominal

=0V)

(1)

Over temperature

Undervoltage

Short circuit to GND
(R

≤ 10 mΩ)

sc

Short circuit to V

CC

Negative output voltage
clamp

1. If the V
and external circuit.

is high, the SENSE output is at a high impedance, its potential depends on leakage currents

CSD

L
H

L
H

L
H
H

L
H

LL 0

Figure 8. Switching characteristics

V

OUT

dV

OUT

t

Won

80%

/dt

(on)

t

r

10%

t

Woff

90%

L
L

L
L

L
L
L

V

SENSEH

H
H

dV

/dt

OUT

(off)

t

f

0

V

SENSEH

0
0

0

0 if T

< T

j

if Tj > T

0

< Nominal

t

TSD

TSD

INPUT

t

d(on)

t

d(off)

t

Doc ID 12285 Rev 7 15/31

Electrical specifications VND5012AK-E

Figure 9. Output voltage drop limitation

Vcc-V

out

Tj=150oC

V

on

Von/R

on(T)

Table 12. Electrical transient requirements (part 1/3)

=25oC

T

j

=-40oC

T

j

I

out

ISO 7637-2:

Test levels

2004(E)

test pulse

III IV Min. Max.

1 -75V -100V

2a +37V +50V

(1)

Number of

pulses or

test times

5000

pulses

5000

pulses

Burst cycle/pulse

repetition time

Delays and
impedance

0.5 s 5 s 2 ms, 10 Ω

0.2 s 5 s 50 µs, 2 Ω

3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω

3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω

4-6V-7V1 pulse

5b

(2)

+65V +87V 1 pulse 400 ms, 2 Ω

100 ms, 0.01

Table 13. Electrical transient requirements (part 2/3)

ISO 7637-2:

Test level results

2004(E)

test pulse

III IV

1C C

2C C

(1)

Ω

3a C C

3b C C

4C C

(2)

5

1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5 b.

2. Valid in case of external load dump clamp: 40 V maximum referred to ground.

CC

16/31 Doc ID 12285 Rev 7

VND5012AK-E Electrical specifications

Table 14. Electrical transient requirements (part 3/3)

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

E

One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.

Figure 10. Waveforms

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

V

CC

INPUT
CS_DIS

LOAD CURRENT

SENSE CURRENT

INPUT
CS_DIS

LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT

V

USD

NORMAL OPERATION

UNDERVOLTAGE

SHORT TO V

<Nominal

V

USDhyst

CC

<Nominal

OVERLOAD OPERATION

T

TSD

T

j

T

R

T

RS

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

current

limitation

power
limitation

SHORTED LOAD NORMAL LOAD

thermal cycling

I

LIMH

I

LIML

V

SENSEH

Doc ID 12285 Rev 7 17/31

Electrical specifications VND5012AK-E

2.4 Electrical characteristics curves

Figure 11. Off-state output current Figure 12. High level input current

Figure 13. Input clamp voltage Figure 14. Input high level

Figure 15. Input low level Figure 16. Input hysteresis voltage

18/31 Doc ID 12285 Rev 7

VND5012AK-E Electrical specifications

Figure 17. On-state resistance vs T

case

Figure 18. On-state resistance vs V

Figure 19. Undervoltage shutdown Figure 20. I

LIMH

vs T

CC

case

Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope

Doc ID 12285 Rev 7 19/31

Electrical specifications VND5012AK-E

Figure 23. CS_DIS high level voltage Figure 24. CS_DIS clamp voltage

Figure 25. CS_DIS low level voltage

20/31 Doc ID 12285 Rev 7

VND5012AK-E Application information

3 Application information

Figure 26. Application schematic

+5V

V

CC

R

prot

μ

C

R

prot

R

prot

R

SENSE

C

ext

CS_DIS

INPUT

CURRENT SENSE

D

ld

OUTPUT

GND

R

GND

GND

D

GND

V

Note: Channel 2 has the same internal circuit as channel 1.

3.1 GND Protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (R

This can be used with any type of load.

The following is an indication on how to dimension the R

1. R

2. R

where -I
maximum rating section of the device datasheet.

Power Dissipation in R

P

= (-VCC)2/R

D

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the
R

GND

values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R

≤ 600 mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

S(on)max

GND

GND

).

)

(when VCC<0: during reverse battery situations) is:

GND

will produce a shift (I

S(on)max

* R

GND

GND

) in the input thresholds and the status output

.

GND

only)

GND

S(on)max

resistor.

becomes the sum of the

Doc ID 12285 Rev 7 21/31

Application information VND5012AK-E

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).

3.1.2 Solution 2: diode (D

A resistor (R

=1 kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V

max DC rating. The same applies if the device is subject to transients on the VCC line

CC

that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (input levels compatibility) with the latch-up limit of µC
I/Os.

if the device drives an

GND

prot

) in line to

-V

CCpeak/Ilatchup

≤ R

prot

≤ (V

OHµC-VIH-VGND

Calculation example:

For V

5kΩ ≤ R

Recommended values: R

22/31 Doc ID 12285 Rev 7

CCpeak

prot

= - 100 V and I

≤ 180 kΩ.

latchup

=10 kΩ, C

prot

≥ 20 mA; V

EXT

) / I

IHmax

OHµC

=10 nF.

≥ 4.5 V

VND5012AK-E Application information

3.4 Maximum demagnetization energy (VCC = 13.5V)

Figure 27. Maximum turn-off current versus inductance (for each channel)

100

A

B

C

10

I (A)

1

0,1110100L (mH)

A: T

jstart

B: T

jstart

C: T

jstart

V

, I

IN

L

Note: Values are generated with R

demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.

= 150°C single pulse

= 100°C repetitive pulse

= 125°C repetitive pulse

Demagnetization Demagnetization Demagnetization

=0 Ω.In case of repetitive pulses, T

L

(at beginning of each

jstart

t

Doc ID 12285 Rev 7 23/31

Package and PCB thermal data VND5012AK-E

4 Package and PCB thermal data

4.1 PowerSSO-24 thermal data

Figure 28. PowerSSO-24 PC board

Note: Layout condition of R

area= 77 mm x 86 mm,PCB thickness=1.6 mm, Cu thickness=70 µm (front and back side),
Copper areas: from minimum pad layout to 8 cm

Figure 29. R

thj-amb

on)

RTHj_amb(°C/W)

55

50

45

40

35

30

0246810

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

vs PCB copper area in open box free air condition (one channel

PCB Cu heatsink area (cm^2)

24/31 Doc ID 12285 Rev 7

VND5012AK-E Package and PCB thermal data

Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse (one

channel on)

ZTH (° C/ W)

100

foot pr int

2

2 cm

2

8 cm

10

1

0,1

0,0001 0,001 0,01 0,1 1 10 100 1000

Time ( s)

Equation 1: pulse calculation formula

Z

THδ

where δ = t

Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-24

R

TH

P

δ Z

/T

THtp

1 δ–()+⋅=

(a)

a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Doc ID 12285 Rev 7 25/31

Package and PCB thermal data VND5012AK-E

Table 15. Thermal parameter

Area/island (cm2)Footprint28

R1 (°C/W) 0.1

R2 (°C/W) 0.3

R3 (°C/W) 6

R4 (°C/W) 7.7

R5 (°C/W) 9 9 8

R6 (°C/W) 28 17 10

R7 (°C/W) 0.1

R8 (°C/W) 0.3

C1 (W.s/°C) 0.0025

C2 (W.s/°C) 0.0024

C3 (W.s/°C) 0.025

C4 (W.s/°C) 0.75

C5 (W.s/°C) 1 4 9

C6 (W.s/°C) 2.2 5 17

C7 (W.s/°C) 0.0025

C8 (W.s/°C) 0.0024

26/31 Doc ID 12285 Rev 7

VND5012AK-E Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com

ECOPACK® is an ST trademark.

5.2 PowerSSO-24 package mechanical data

Figure 32. PowerSSO-24 package dimensions

.

Table 16. PowerSSO-24 mechanical data

Millimeters

Symbol

Min. Typ. Max.

A 2.15 2.47

A2 2.15 2.40

a1 0 0.1

b 0.33 0.51

Doc ID 12285 Rev 7 27/31

Package and packing information VND5012AK-E

Table 16. PowerSSO-24 mechanical data (continued)

Symbol

Min. Typ. Max.

c 0.23 0.32

D 10.10 10.50

E7.4 7.6

e0.8

e3 8.8

G 0.1

G1 0.06

H 10.1 10.5

h 0.4

L 0.55 0.85

N 10deg

Millimeters

X4.1 4.7

Y6.5 7.1

5.3 PowerSSO-24 packing information

Figure 33. PowerSSO-24 tube shipment (no suffix)

Base Q.ty 49
Bulk Q.ty 1225

C

B

A

Tube length (± 0.5) 532
A 3.5
B 13.8
C (± 0.1) 0.6

All dimensions are in mm.

28/31 Doc ID 12285 Rev 7

VND5012AK-E Package and packing information

Figure 34. PowerSSO-24 tape and reel shipment (suffix “TR”)

Reel dimensions

Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 24.4
N (min) 100

Tape dimensions

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

End

Start

Top

cover

tape

500mm min

Empty components pockets
saled with cover tape.

User direction of feed

No componentsNo components Components

500mm min

Doc ID 12285 Rev 7 29/31

Revision history VND5012AK-E

6 Revision history

Table 17. Document revision history

Date Revision Changes

10-Apr-2006 1 Initial release.

Document reformatted and restructured.
Added lists of tables and figures.
Added ECOPACK

Table 4: Absolute maximum ratings: updated EMAX entries.
Table 10: Current sense (8V<V

tDSENSE2H.

02-Jul-2007 2

Added Figure 5: Delay response time between rising edge of output

current and rising edge of current sense (CS enabled).

Updated Figure 6: I
Added Figure 7: Maximum current sense ratio drift vs load current.

Table 12: Electrical transient requirements (part 1/3): updated Test

level values III and IV for test pulse 5b and notes.
Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V).

Updated Table 10: Current sense (8V<V

– changed dk3/k3 values from ± 3 to ± 4%

12-Feb-2008 3

– changed tDSENSE2H max value from 250 µs to 300 µs
– added IOL parameter

Updated Figure 7: Maximum current sense ratio drift vs load current
with new dk3/k3 value.

18-Jul-2008 4

01-Aug-2008 5

Updated Table 4: Absolute maximum ratings: corrected typing error in

parameter.

V

ESD

Updated Table 16: PowerSSO-24 mechanical data: changed a1 max.
value from 0.075 mm to 0.1 mm.

Updated Section 5.1: ECOPACK

26-May-2009 6

Updated Figure 13, Figure 15, Figure 16, Figure 17, Figure 18,

Figure 20, Figure 21, Figure 22 and Figure 23.

02-Dec-2009 7 Added Table 8: Logic inputs.

®

packages information.

<16V): added dk1/k1, dk2/k2, dk3/k3,

CC

OUT/ISENSE

vs I

OUT

®

packages.

.

CC

<16V):

30/31 Doc ID 12285 Rev 7

VND5012AK-E

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Doc ID 12285 Rev 7 31/31