Page 1
Single channel high-side solid state relay
Features
Typ e R
VN920B5-E 16 mΩ 30 A 36 V
DS(on)
I
OUT
VN920B5-E
V
CC
■ ECOPACK
■ Automotive Grade: compliance with AEC
®
: lead free and RoHS compliant
Guidelines
■ Very low standby current
■ CMOS compatible input
■ Proportional load current sense
■ Current sense disable
■ Thermal shutdown protection and diagnosis
■ Undervoltage shutdown
■ Overvoltage clamp
■ Load current limitation
P2PAK
Description
The VN920B5-E is a monolithic device designed
in STMicroelectronics™ VIPower™ M0-3
technology. The VN920B5-E is intended for
driving any type of load with one side connected
to ground.
The active V
pin voltage clamp protects the
CC
device against low energy spikes (see ISO7637
transient compatibility table).
Active current limitation combined with thermal
shutdown and automatic restart protect the device
against overload.
The device integrates an analog current sense
output which delivers a current proportional to the
load current. The device automatically turns off in
the case where the ground pin becomes
disconnected.
Table 1. Device summary
Order codes
Package
Tube Tape and reel
2
PAK VN920B5-E VN920B5TR-E
P
July 2010 Doc ID 17608 Rev 1 1/26
www.st.com
1
Page 2
Contents VN920B5-E
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 16
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 17
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 P
2
PAK maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . 18
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 P2PAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
5.2 P
5.3 P
PAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26 Doc ID 17608 Rev 1
Page 3
VN920B5-E List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Switching (V
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Current sense (9 V ≤ V
Table 9. V
output diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
Table 10. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 13. P
Table 14. P
2
PAK thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
PAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
= 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
≤ 16 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
Doc ID 17608 Rev 1 3/26
Page 4
List of figures VN920B5-E
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. I
OUT/ISENSE
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. I
LIM
vs T
Figure 14. On-state resistance vs V
Figure 15. Input high-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17. On-state resistance vs T
Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20. P
Figure 21. P
Figure 22. P
Figure 23. P
Figure 24. Thermal fitting model of a single channel HSD in P
Figure 25. P
Figure 26. P
Figure 27. P
2
PAK maximum turn-off current versus inductance
2
PAK PC board
2
PAK Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . 19
2
PAK thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 20
2
PAK package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
PAK tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
PAK tape and reel (suffix “TR”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
versus I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
case
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
case
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2
PAK. . . . . . . . . . . . . . . . . . . . . . . . . . 20
4/26 Doc ID 17608 Rev 1
Page 5
VN920B5-E Block diagram and pin description
1 Block diagram and pin description
Figure 1. Block diagram
V
CC
V
CC
CLAMP
GND
INPUT
LOGIC
OVERTEMPERATURE
DETECTION
OVERVOLTAGE
DETECTION
UNDERVOLTAGE
Figure 2. Configuration diagram (top view)
5
4
3
2
1
DETECTION
DRIVER
OUTPUT
C.SENSE
V
CC
INPUT
GND
Power CLAMP
OUTPUT
CURRENT LIMITER
VDS LIMITER
I
OUT CURRENT
K
SENSE
P2PAK
Table 2. Suggested connections for unused and not connected pins
Connection / pin Current Sense N.C. Output Input
Floating X X X
To ground
Through 1KΩ
resistor
X
Through 10KΩ
Doc ID 17608 Rev 1 5/26
resistor
Page 6
Electrical specifications VN920B5-E
2 Electrical specifications
Figure 3. Current and voltage conventions
I
S
V
I
IN
V
IN
INPUT
CURRENT SENSE
2.1 Absolute maximum ratings
GND
CC
OUTPUT
I
GND
I
OUT
I
SENSE
V
SENSE
V
F
V
OUT
V
CC
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics sure
program and other relevant quality document.
Table 3. Absolute maximum ratings
Symbol Parameter
V
- V
- I
I
OUT
- I
OUT
I
V
CSENSE
CC
CC
gnd
IN
DC supply voltage 41 V
Reverse DC supply voltage - 0.3 V
DC reverse ground pin current - 200 mA
DC output current Internally limited A
Reverse DC output current - 21 A
DC input current +/- 10 mA
Current sense maximum voltage
Electrostatic discharge (human body model:
R=1.5KΩ; C = 100 pF)
V
ESD
– INPUT
– CURRENT SENSE
–OUTPUT
–V
CC
E
MAX
Maximum switching energy (L = 0.25 mH;
R
L
=0Ω; V
=13.5V; T
bat
jstart
= 150 °C; IL=45A)
Val ue
- 3
+ 15
4000
2000
5000
5000
364 mJ
Unit
V
V
V
V
V
V
6/26 Doc ID 17608 Rev 1
Page 7
VN920B5-E Electrical specifications
Table 3. Absolute maximum ratings (continued)
Symbol Parameter
Val ue
Unit
P
tot
T
j
T
c
T
stg
Power dissipation TC ≤ 25 °C 96.1 W
Junction operating temperature Internally limited °C
Case operating temperature - 40 to 150 °C
Storage temperature - 55 to 150 °C
2.2 Thermal data
Table 4. Thermal data
Symbol Parameter Max. value Unit
R
thj-case
R
thj-lead
R
thj-amb
1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35μm thick).
2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35μm thick).
Thermal resistance junction-case 1.3 °C/W
Thermal resistance junction-lead °C/W
Thermal resistance junction-ambient
51.3
37
(2)
(1)
°C/W
°C/W
Doc ID 17608 Rev 1 7/26
Page 8
Electrical specifications VN920B5-E
2.3 Electrical characteristics
Values specified in this section are for 8 V < V
< 36 V; -40 °C < Tj < 150 °C, unless
CC
otherwise stated.
Table 5. Power
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
R
V
CLAMP
I
L(off1)
I
L(off2)
I
L(off3)
I
L(off4)
Operating supply voltage 5.5 13 36 V
CC
Undervoltage shutdown 3 4 5.5 V
USD
Overvoltage shutdown 36 V
OV
I
= 10 A; Tj = 25 °C 16 mΩ
OUT
On-state resistance
ON
Clamp voltage I
Supply current
I
S
Off-state output current V
Off-state output current V
Off-state output current
Off-state output current
= 10 A 32 mΩ
I
OUT
= 3 A; V
I
OUT
= 20 mA 41 48 55 V
CC
Off-state; V
= V
V
IN
OUT
Off-state; V
= V
V
IN
OUT
On-state; V
= 0 A; R
I
OUT
= V
IN
OUT
= 0 V; V
IN
V
= V
IN
OUT
= 125 °C
T
j
V
= V
IN
OUT
= 25 °C
T
j
= 6 V 55 mΩ
CC
= 13 V;
CC
= 0 V
= 13 V;
CC
= 0 V; Tj = 25 °C
= 13 V; V
CC
SENSE
= 5 V;
IN
= 3.9 kΩ
= 0 V 0 50 µA
= 3.5 V -75 0 µA
OUT
= 0V; V
= 0 V; V
CC
CC
= 13 V;
= 13 V;
10 25 µA
10 20 µA
5mA
5µA
3µA
Note: V
Table 6. Switching (VCC=13V)
and VOV are correlated. Typical difference is 5V.
CLAMP
Symbol Parameter Test conditions Min. Typ. Max. Unit
Turn-on delay time RL = 1.3 Ω (see Figure 4)50µs
Turn-off delay time RL = 1.3 Ω (see Figure 4)50µs
/dt
Turn-on voltage slope RL = 1.3 Ω (see Figure 4) See Figure 10 V/µs
(on)
/dt
Turn-off voltage slope RL = 1.3 Ω (see Figure 4) See Figure 12 V/µs
(off)
dV
dV
t
d(on)
t
d(off)
OUT
OUT
8/26 Doc ID 17608 Rev 1
Page 9
VN920B5-E Electrical specifications
Table 7. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
I(hyst)
V
V
Input low level voltage 1.25 V
IL
Low level input current V
I
IL
Input high-level voltage 3.25 V
IH
I
High-level input current V
IH
= 1.25 V 1 µA
IN
= 3.25 V 10 µA
IN
Input hysteresis voltage 0.5 V
I
= 1 mA 6 6.8 8 V
Input clamp voltage
ICL
IN
I
= - 1 mA -0.7 V
IN
Table 8. Current sense (9 V ≤ VCC ≤ 16 V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
dK
dK
K
1
1/K1
K
2
2/K2
I
OUT/ISENSE
Current sense ratio drift
I
OUT/ISENSE
Current sense ratio drift
= 1 A; V
OUT
= -40 °C...150 °C
T
j
I
= 1 A; V
OUT
= - 40 °C...150 °C
T
j
I
= 10 A; V
OUT
= - 40 °C
T
j
Tj= 25 °C...150 °C
I
= 10 A; V
OUT
Tj = -40 °C...150 °C
SENSE
SENSE
SENSE
SENSE
= 0.5 V;
= 0.5 V;
= 4 V;
= 4 V;
3300 4400 6000
-10 +10 %
4200
4900
6000
4400
4900
5750
-8 +8 %
I
= 30 A; V
OUT
K
dK
3/K3
I
SENSE0
V
SENSE
V
SENSEH
R
VSENSEH
t
DSENSE
1. Current sense signal delay after positive input slope.
I
3
OUT/ISENSE
Current sense ratio drift
Analog sense current
Max analog sense output
voltage
Sense voltage in
overtemperature condition
Analog sense output
impedance in
overtemperature condition
Current sense delay
response
Tj = -40 °C
= 25 °C...150 °C
T
j
I
= 30 A; V
OUT
= -40 °C...150 °C
T
j
V
= 6...16 V; I
CC
V
SENSE
= -40 °C...150 °C
T
j
V
= 5.5 V; I
CC
R
SENSE
V
> 8 V, I
CC
R
SENSE
V
= 13 V; R
CC
V
= 13 V; Tj > T
CC
output open
To 9 0 % I
= 0 V;
OUT
= 10 kΩ
OUT
= 10 kΩ
SENSE
= 4 V;
SENSE
4200
4900
4400
4900
= 4 V;
SENSE
OUT
= 0 A;
-6 +6 %
010µA
= 5 A;
= 10 A;
= 3.9 kΩ 5.5 V
SENSE
;
TSD
(1)
2V
4V
400 Ω
5500
5250
500 µs
Doc ID 17608 Rev 1 9/26
Page 10
Electrical specifications VN920B5-E
Table 9. VCC output diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
F
Table 10. Protections
Forward on voltage -I
(1)
= 5 A; Tj = 150 °C — — 0.6 V
OUT
Symbol Parameter Test conditions Min. Typ. Max. Unit
T
TSD
T
T
hyst
I
lim
V
demag
V
1. To ensure long term reliability under heavy over-load or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device operates under
abnormal conditions this software must limit the duration and number of activation cycles.
Table 11. Truth table
Shutdown temperature 150 175 200 °C
Reset temperature 135 °C
R
Thermal hysteresis 7 15 °C
V
= 13 V 30 45 75 A
Current limitation
Turn-off output clamp
voltage
Output voltage drop
ON
limitation
CC
5V < V
I
OUT
< 36 V 75 A
CC
= 2 A; V
IN
= 0 V;
L = 6 mH
= 1 A;
I
OUT
Tj = -40 °C...150 °C
V
CC
- 41 V
- 48 V
CC
50 mV
- 55 V
CC
Conditions Input Output Sense
Normal operation
Overtemperature
Undervoltage
Overvoltage
Short circuit to GND
Short circuit to V
CC
L
H
L
H
L
H
L
H
L
H
H
L
H
L
H
Nominal
L
L
V
L
L
L
L
L
L
L
(T
j>TTSD
(T
H
H
< Nominal
Negative output voltage clamp L L 0
0
0
SENSEH
0
0
0
0
0
j<TTSD
) V
0
) 0
SENSEH
10/26 Doc ID 17608 Rev 1
Page 11
VN920B5-E Electrical specifications
Table 12. Electrical transient requirements
ISO T/R
Test level
7637/1
Test pulse
1- 25V
2 + 25V
3a - 25V
3b + 25V
4- 4V
5+ 26.5V
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
proper operation without replacing the device.
I II III IV Delays and impedance
(1)
(1)
(1)
(1)
(1)
(1)
- 50V
+ 50V
- 50V
+ 50V
- 5V
+ 46.5V
(1)
(1)
(1)
(1)
(1)
(2)
- 75V
+ 75V
- 100V
+ 75V
(1)
- 6V
+ 66.5V
(1)
(1)
(1)
(1)
(2)
- 100V
+ 100V
- 150V
+ 100V
- 7V
+ 86.5V
(1)
(1)
(1)
(1)
(1)
(2)
2ms, 10Ω
0.2ms, 10Ω
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
400ms, 2Ω
Figure 4. Switching characteristics
V
OUT
90%
t
f
dV
OUT
/dt
(off)
t
dV
I
SENSE
OUT
80%
/dt
(on)
t
90%
r
10%
t
t
d(on)
DSENSE
t
d(off)
INPUT
t
t
Doc ID 17608 Rev 1 11/26
Page 12
Electrical specifications VN920B5-E
Figure 5. I
I
OUT/ISENSE
6500
6500
6000
6000
5500
5500
5000
5000
4500
4500
4000
4000
3500
3500
3000
3000
0 2 4 6 8 101214 161820222426283032
OUT/ISENSE
versus I
OUT
max.Tj=25...150°C
min.Tj=25...150°C
I
OUT
max.Tj=-40°C
typical value
min.Tj=-40°C
(A)
12/26 Doc ID 17608 Rev 1
Page 13
VN920B5-E Electrical specifications
Figure 6. Waveforms
NORMAL OPERATION
INPUT
LOAD CURRENT
SENSE
UNDERVOLTAGE
V
CC
INPUT
LOAD CURRENT
SENSE
V
CC
INPUT
LOAD CURRENT
SENSE
V
USD
V
VCC > V
OV
USD
V
USDhyst
OVERVOLTAGE
V
OVhyst
INPUT
LOAD CURRENT
LOAD VOLTAGE
SENSE
INPUT
LOAD VOLTAGE
LOAD CURRENT
SENSE
T
j
INPUT
LOAD CURRENT
SENSE
SHORT TO GROUND
SHORT TO V
<Nominal
T
TSD
T
R
OVERTEMPERATURE
CC
<Nominal
I
SENSE
=
V
SENSEH
R
SENSE
Doc ID 17608 Rev 1 13/26
Page 14
Electrical specifications VN920B5-E
2.4 Electrical characteristics curves
Figure 7. Off-state output current Figure 8. High-level input current
Figure 9. Input clamp voltage Figure 10. Turn-on voltage slope
Figure 11. Overvoltage shutdown Figure 12. Turn-off voltage slope
IL(off1) (uA)
9
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Vicl (V)
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
Iin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Vov (V)
50
48
46
44
42
40
38
36
34
32
30
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Iih (uA)
5
4.5
3.5
2.5
1.5
0.5
Vin=3.25V
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
dVout/dt(on) (V/ms)
700
650
600
550
500
450
400
350
300
250
-50 -25 0 25 50 75 100 125 150 175
Vcc=13V
Rl=1.3Ohm
Tc (ºC)
dVout/dt(off) (V/ms)
550
500
450
400
350
300
250
200
150
100
50
0
Vcc=13V
Rl=1.3Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
14/26 Doc ID 17608 Rev 1
Page 15
VN920B5-E Electrical specifications
Figure 13. I
Ilim (A)
100
90
80
70
60
50
40
30
20
10
0
-50 -25 0 25 50 75 100 125 150 175
Figure 15. Input high-level Figure 16. Input hysteresis voltage
Vih (V)
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
-50 -25 0 25 50 75 100 125 150 175
vs T
LIM
Vcc=13V
case
Tc (°C)
Tc (°C)
Figure 14. On-state resistance vs V
Ron (mOhm)
50
45
40
35
30
25
20
15
10
5
0
5 10152025303540
Tc= 150ºC
Tc= 25ºC
Tc= - 40ºC
Vcc (V)
Vhyst (V)
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
CC
Figure 17. On-state resistance vs T
Ron (mOhm)
50
45
40
35
30
25
20
15
10
5
0
-50 -25 0 25 50 75 100 125 150 175
Iout=10A
Vcc=8V; 36V
Tc (ºC)
case
Figure 18. Input low level
Vil (V)
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Doc ID 17608 Rev 1 15/26
Page 16
Application information VN920B5-E
3 Application information
Figure 19. Application schematic
+5V
GND
V
CC
OUTPUT
D
GND
R
prot
INPUT
R
μ
C
prot
R
SENSE
CURRENT SENSE
V
GND
R
GND
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (R
This can be used with any type of load.
GND
only)
D
ld
The following is an indication on how to dimension the R
1. R
2. R
where -I
≤ 600 mV / (I
GND
≥ (-VCC) / (-I
GND
is the DC reverse ground pin current and can be found in the absolute
GND
S(on)max
GND
)
)
maximum rating section of the device datasheet.
Power Dissipation in R
P
= (-VCC)2/ R
D
GND
GND
(when V
< 0: during reverse battery situations) is:
CC
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
produces a shift (I
GND
S(on)max
* R
) in the input thresholds and the status output
GND
values. This shift varies depending on how many devices are ON in the case of several highside drivers sharing the same R
GND
.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
16/26 Doc ID 17608 Rev 1
resistor.
GND
S(on)max
becomes the sum of the
Page 17
VN920B5-E Application information
3.1.2 Solution 2: diode (D
A resistor (R
= 1 kΩ) should be inserted in parallel to D
GND
) in the ground line
GND
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift not varies if more than one HSD shares the same diode/resistor network.
Series resistor in INPUT and STATUS lines are also required to prevent that, during battery
voltage transient, the current exceeds the absolute maximum rating.
Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V
max DC rating. The same applies if the device is subject to transients on the VCC line
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (R
the microcontroller I/Os pins to latch-up.
if the device drives an
GND
) in line to prevent
prot
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-V
CCpeak/Ilatchup
≤ R
prot
≤ (V
OHµC-VIH-VGND
) / I
IHmax
Calculation example:
For V
5kΩ ≤ R
Recommended values: R
CCpeak
prot
= -100 V and I
≤ 65 kΩ.
latchup
=10 kΩ.
prot
≥ 20 mA; V
OHµC
≥ 4.5 V
Doc ID 17608 Rev 1 17/26
Page 18
Application information VN920B5-E
3.4
P2PAK
Figure 20.
LMAX (A)
I
maximum demagnetization energy (VCC = 13.5V)
P2PAK
maximum turn-off current versus inductance
100
A
B
C
10
1
0.01 0.1 1 10 100
L(mH)
(1)
A: T
B: T
C: T
VIN, I
1. Values are generated with R
In case of repetitive pulses, T
the temperature specified above for curves A and B.
= 150 °C single pulse
jstart
= 100 °C repetitive pulse
jstart
= 125 °C repetitive pulse
jstart
L
Demagnetization Demagnetization Demagnetization
=0 Ω.
L
(at beginning of each demagnetization) of every pulse must not exceed
jstart
t
18/26 Doc ID 17608 Rev 1
Page 19
VN920B5-E Package and PCB thermal data
4 Package and PCB thermal data
4.1 P2PAK thermal data
Figure 21. P2PAK PC board
1. Layout condition of R
Cu thickness = 35 μm , Copper areas: 0.97 cm2, 8 cm2).
Figure 22. P2PAK R
and Zth measurements (PCB FR4 area = 60 mm x 60 mm, PCB thickness = 2 mm,
th
thj-amb
(1)
vs PCB copper area in open box free air condition
RTHj_amb (°C/W)
55
50
Tj-Tamb=50°C
45
40
35
30
0246810
PCB Cu heatsink area (cm^2)
Doc ID 17608 Rev 1 19/26
Page 20
Package and PCB thermal data VN920B5-E
Figure 23. P2PAK thermal impedance junction ambient single pulse
ZT H (°C/W)
1000
100
10
1
0.1
0.01
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
Equation 1: pulse calculation formula
Z
THδ
R
TH
δ Z
THtp
1 δ–()+⋅=
where δ = tP/T
0.97 cm
6 cm
2
2
Figure 24. Thermal fitting model of a single channel HSD in P
20/26 Doc ID 17608 Rev 1
2
PAK
Page 21
VN920B5-E Package and PCB thermal data
Table 13 . P2PAK thermal parameter
Area/island (cm2)0.976
R1 (°C/W) 0.02
R2 (°C/W) 0.1
R3 (°C/W) 0.22
R4 (°C/W) 4
R5 (°C/W) 9
R6 (°C/W) 37 22
C1 (W·s/°C) 0.0015
C2 (W·s/°C) 0.007
C3 (W·s/°C) 0.015
C4 (W·s/°C) 0.4
C5 (W·s/°C) 2
C6 (W·s/°C) 3 5
Doc ID 17608 Rev 1 21/26
Page 22
Package and packing information VN920B5-E
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
5.2 P2PAK mechanical data
Figure 25. P2PAK package dimensions
22/26 Doc ID 17608 Rev 1
P010R
Page 23
VN920B5-E Package and packing information
Table 14 . P2PAK mechanical data
mm
Dim.
Min. Typ. Max.
A 4.30 4.80
A1 2.40 2.80
A2 0.03 0.23
b 0.80 1.05
c 0.45 0.60
c2 1.17 1.37
D 8.95 9.35
D2 8.00
E 10.00 10.40
E1 8.50
e 3.20 3.60
e1 6.60 7.00
L 13.70 14.50
L2 1.25 1.40
L3 0.90 1.70
L5 1.55 2.40
R0.40
V2 0º 8º
Package weight 1.40 Gr (typ)
Doc ID 17608 Rev 1 23/26
Page 24
Package and packing information VN920B5-E
5.3 P2PAK packing information
Figure 26. P2PAK tube shipment (no suffix)
Base Q.ty 50
Bulk Q.ty 1000
Tube length (± 0.5) 532
A 18
B 33.1
C (± 0.1) 1
All dimensions are in mm.
REEL DIMENSIONS
All dimensions are in mm.
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 24.4
N (min) 60
T (max) 30.4
Figure 27. P
B
C
A
2
PAK tape and reel (suffix “TR”)
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 11.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2
All dimensions are in mm.
Top
cover
tape
End
24/26 Doc ID 17608 Rev 1
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Start
No componentsNo components Components
500mm min
Page 25
VN920B5-E Revision history
6 Revision history
Table 15. Document revision history
Date Revision Changes
19-Jul-2010 1 Initial release.
Doc ID 17608 Rev 1 25/26
Page 26
VN920B5-E
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