Datasheet VN5050AJ-E Datasheet (ST)

Features

Max supply voltage V

Operating voltage range V

Max On-State resistance R

Current limitation (typ) I

Off state supply current I

VN5050AJ-E

Single channel high side driver with analog

current sense for automotive applications

CC

CC

ON

LIMH

S

41 V

4.5 to 36V

50 mΩ

16.5 A

2 µA

PowerSSO-12

– Reverse battery protection ( see

Application schematic )

– Electrostatic discharge protection

■ General features

– Inrush current active management by

power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC

European directive

■ Diagnostic functions

– Proportional load current sense
– High current sense precision for wide range

currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage

■ Protection

– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss

of V

CC

– Thermal shut down

Table 1. Device summary

Package

PowerSSO-12 VN5050AJ-E VN5050AJTR-E

Application

■ All types of resistive, inductive and capacitive

loads

■ Suitable as LED driver

Description

The VN5050AJ-E is a monolithic device made
using STMicroelectronics VIPower technology. It
is intended for driving resistive or inductive loads
with one side connected to ground. Active V
voltage clamp protects the device against low
energy spikes (see ISO7637 transient
compatibility table).
This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open.
When CS_DIS is driven high, the CURRENT
SENSE pin is in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.

Order codes

Tube Tape and Reel

CC

pin

February 2008 Rev 6 1/31

www.st.com

31

Contents VN5050AJ-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21

3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21

3.1.2 Solution 2: diode (D

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

) in the ground line . . . . . . . . . . . . . . . . . . . . . . 22

GND

3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31

VN5050AJ-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7. Switching (V

Table 8. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9. Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10. Current sense (8V<V

Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 13. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CC

3/31

List of figures VN5050AJ-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Delay response time between rising edge of ouput current and rising edge of current sense

(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. I

Figure 9. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 17. On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 18. On state resistance vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 20. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 21. ILIMH Vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 22. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 27. Maximum turn Off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 28. PowerSSO-12™ PC Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 24

Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 25

Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25

Figure 32. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 33. PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

OUT/ISENSE

Vs. I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

OUT

4/31

VN5050AJ-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

CC

V

CC

CLAMP

UNDERVOLTAGE

DRIVER

GND

LOGIC

INPUT

CS_DIS

Table 2. Pin function

Name Function

V

CC

Battery connection.

OUTPUT Power output.

GND

INPUT

Ground connection. Must be reverse battery protected by an external
diode/resistor network.

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.

Pwr

LIM

OVERTEMP.

I

OUT

PwCLAMP

I

LIM

V

DSLIM

K

OUTPUT

CURRENT
SENSE

CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current.

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

5/31

Block diagram and pin description VN5050AJ-E

Figure 2. Configuration diagram (top view)

TA B = V

N.C.

GND

INPUT

CURRENT SENSE

CS_DIS

N.C.

Note: The above pin configuration reflects the changes notified with PCN-APG-BOD/07/2886. The

new pinout is backaward compatible with existing PCB layouts where pins #1 and #6 are
connected to Vcc and/or pins #7 and 12 are connected to OUTPUT. For new PCB designs,
these pins should be left unconnected.

Table 3. Suggested connections for unused and N.C. pins

Connection / Pin Current Sense N.C. Output Input CS_DIS

1
2
3
4
5

6

12
11
10

9
8
7

cc

N.C.
OUTPUT

OUTPUT
OUTPUT
OUTPUT

N.C.

Floating N.R. X X X X

Through 10kΩ

To ground Through 1kΩ resistor X N.R.

1. Not recommended.

(1)

resistor

Through

10kΩ resistor

6/31

VN5050AJ-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I

S

V

CC

V

F

I

I

CSD

I

IN

V

CSD

V

IN

CS_DIS

INPUT

CURRENT SENSE

GND

OUTPUT

I

GND

OUT

I

SENSE

V

SENSE

V

CC

V

OUT

Note: V

= V

F

- VCC during reverse battery condition.

OUT

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

V

-V

- I

I

OUT

- I

I

CSD

-I

CSENSE

V

CSENSE

E

DC supply voltage 41 V

CC

Reverse DC supply voltage 0.3 V

CC

DC reverse ground pin current 200 mA

GND

DC output current

Reverse DC output current 30 A

OUT

DC input current -1 to 10 mA

I

IN

DC current sense disable input current -1 to 10 mA

DC reverse CS pin current 200 mA

Current sense maximum voltage

Maximum switching energy (single pulse)

MAX

(L= 3mH; R

=0Ω; V

L

=13.5V; T

bat

jstart

=150ºC; I

OUT

= I

limL

(Typ.) )

Internally

limited

V

-41

CC

+V

CC

104 mJ

A

V
V

7/31

Electrical specifications VN5050AJ-E

Table 4. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Electrostatic discharge (Human Body Model: R=1.5kΩ; C=100pF)

- INPUT

V

- CURRENT SENSE

ESD

- CS_DIS

- OUTPUT

- V

CC

V

T

Charge device model (CDM-AEC-Q100-011) 750 V

ESD

Junction operating temperature -40 to 150 °C

T

j

Storage temperature -55 to 150 °C

stg

4000
2000
4000
5000
5000

V
V
V
V
V

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter Max value Unit

R

R

thj-case

thj-amb

Thermal resistance junction-case (MAX) 2.7 °C/W

Thermal resistance junction-ambient (MAX) See Figure 29. °C/W

8/31

VN5050AJ-E Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8V < VCC < 36V; -40°C < Tj < 150°C, unless
otherwise specified.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

USDhyst

R

V

clamp

Operating supply

CC

voltage

Undervoltage

USD

shutdown

Undervoltage
shutdown hysteresis

I

= 2A; Tj=25°C

OUT

On state resistance

ON

I

= 2A; Tj=150°C

OUT

= 2A; VCC=5V; Tj=25°C

I

OUT

Clamp voltage IS= 20mA 41 46 52 V

Off State; V

I

S

Supply current

VIN=V

OUT=VSENSE=VCSD

On State; V

I

L(off)

1. PowerMOS leakage included.

Table 7. Switching (VCC=13V, Tj=25°C)

Off state output current

Output - VCC diode

V

F

voltage

VIN=V
VIN=V

-I

OUT

=0V; VCC=13V; Tj=25°C

OUT

=0V; VCC=13V; Tj=125°C

OUT

= 2A; Tj= 150°C 0.7 V

=13V; Tj=25°C;

CC

=13V; VIN=5V; I

CC

=0V

OUT

4.5 13 36 V

3.5 4.5 V

0.5 V

(1)

2

=0A

1.5

000.01 3

50

100

65

(1)

5

3µAmA

5

mΩ
mΩ
mΩ

µA

Symbol Parameter Test conditions Min. Typ. Max. Unit

(dV

(dV

t

d(on)

t

d(off)

OUT

OUT

W

W

ON

OFF

Turn-on delay time RL= 6.5Ω (see Figure 7.)20µs

Turn-off delay time RL= 6.5Ω (see Figure 7.)40µs

/dt)onTurn-on voltage slope RL= 6.5Ω

/dt)

Turn-off voltage slope RL= 6.5Ω

off

Switching energy losses
during

tw

on

Switching energy losses
during tw

off

RL= 6.5Ω (see Figure 7.)0.20mJ

RL= 6.5Ω (see Figure 7.)0.3mJ

See

Figure 20

See

Figure 22

9/31

V/ µs

V/ µs

Electrical specifications VN5050AJ-E

Table 8. Logic input

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

V

I

V

I(hyst)

V

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

V

CSCL

Table 9. Protection and diagnostics

Input low level voltage 0.9 V

IL

Low level input current VIN= 0.9V 1 µA

IL

Input high level voltage 2.1 V

IH

High level input current VIN= 2.1V 10 µA

IH

Input hysteresis voltage 0.25 V

Input clamp voltage

ICL

I

= 1mA

IN

= -1mA

I

IN

5.5

-0.7

CS_DIS low level voltage 0.9 V

Low level CS_DIS current V

= 0.9V 1 µA

CSD

CS_DIS high level voltage 2.1 V

High level CS_DIS current V

= 2.1V 10 µA

CSD

CS_DIS hysteresis voltage 0.25 V

CS_DIS clamp voltage

I

CSD

I

CSD

= 1mA
= -1mA

(1)

5.5

-0.7

7V

7V

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

limH

I

limL

DC Short circuit
current

Short circuit current
during thermal cycling

= 13V

V

CC

5V<V

CC

V

=13V TR<Tj<T

CC

<36V

TSD

12 16.5 23

23

7A

V

V

A
A

T

T

T

HYST

V

DEMAG

V

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device operates under
abnormal conditions this software must limit the duration and number of activation cycles.

Shutdown

TSD

temperature

Reset temperature TRS + 1 TRS + 5 °C

T

R

Thermal reset of

RS

STATUS

Thermal hysteresis

TSD-TR

)

I

= 2A; VIN= 0; L= 6mH VCC-41 VCC-46 VCC-52 V

OUT

I

= 0.1A;

OUT

Tj= -40°C...+150°C
(see Figure 5.)

(T

Turn-off output voltage
clamp

Output voltage drop

ON

limitation

10/31

150 175 200 °C

135 °C

7°C

25 mV

VN5050AJ-E Electrical specifications

Table 10. Current sense (8V<VCC<16V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

K

K

dK

1/K1

K

dK

2/K2

K

dK

3/K3

I

SENSE0

I

OL

I

0

OUT/ISENSE

I

1

OUT/ISENSE

Current sense ratio

(1)

drift

I

2

OUT/ISENSE

Current sense ratio

(1)

drift

I

3

OUT/ISENSE

Current sense ratio

(1)

drift

Analog sense
leakage current

Openload ON state
current detection
threshold

= 0.05A; V

OUT

Tj= -40°C...150°C

I

=1A; V

OUT

SENSE

Tj= -40°C...150°C

= 1A; V

I

OUT

= 25°C...150°C

T

j

I

OUT

V

CSD

=1A; V

=0V;

SENSE

SENSE

TJ=-40 °C to 150 °C

I

= 2A; V

OUT

SENSE

Tj= -40°C...150°C

= 2A; V

I

OUT

= 25°C...150°C

T

j

I

OUT

V

CSD

= -40 °C to 150 °C

T

J

I

OUT

= -40°C...150°C

T

j

I

OUT

= 25°C...150°C

T

j

I

OUT

V

CSD

=-40 °C to 150 °C

T

J

I

OUT

V

CSD

V

CSD

I

OUT

V

CSD

V

= 5V, I

IN

SENSE

= 2 A; V

SENSE

= 0V;

= 4A; V

SENSE

= 4A; V

SENSE

= 4 A; V

SENSE

=0V;

= 0A; V

SENSE

= 5V; VIN=0V; Tj= -40°C...150°C
= 0V; VIN=5V; Tj= -40°C...150°C

= 2A; V

SENSE

= 5V; VIN=5V; Tj= -40°C...150°C

SENSE

SENSE

=0.5V; V

= 0.5V; V

=0.5V; V

CSD

CSD

CSD

=0V;

= 0V;

=0V;

1100 2440 3480

1600

2030

2580

1630

2030

2430

= 0.5V;

-10 +10 %

= 4V; V

= 4V; V

CSD

CSD

= 0V;

= 0V;

1770

1800

2000

2000

2310

2200

= 4 V;

-6 +6 %

= 4V; V

= 4V; V

CSD

CSD

= 0V;

= 0V;

1860

1870

1970

1970

2140

2120

= 4 V;

-3 +3 %

=0V;

0
0

1
2

= 0V;

0

1

= 5 µA 4 20 mA

µA
µA

µA

V

SENSE

V

SENSEH

I

SENSEH

Max analog sense
output voltage

Analog sense
output voltage in
overtemperature
condition

Analog sense
output current in
overtemperature
condition

I

OUT

V

V

CC

CC

=2A; V

=13V; R

=13V, V

=0V 5 V

CSD

=10KΩ 9V

SENSE

=5V 8 mA

SENSE

11/31

Electrical specifications VN5050AJ-E

Table 10. Current sense (8V<VCC<16V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

<4V, 0.5A<Iout<4A

Delay response

t

DSENSE1H

time from falling
edge of CS_DIS pin

Delay response

t

DSENSE1L

time from rising
edge of CS_DIS pin

Delay response

t

DSENSE2H

time from rising
edge of INPUT pin

Delay response
time between rising

∆

t

DSENSE2H

edge of output
current and rising
edge of current
sense

Delay response

t

DSENSE2L

time from falling
edge of INPUT pin

1. Parameter guaranteed by design; it is not tested.

V

SENSE

=90% of I

I

SENSE

(see Figure 4.)

<4V, 0.5A<Iout<4A

V

SENSE

I

=10% of I

SENSE

(see Figure 4.)

<4V, 0.5A<Iout<4A

V

SENSE

=90% of I

I

SENSE

(see Figure 4.)

V
I

SENSE

I

OUT

I

OUTMAX

V
I

SENSE

<4V,

SENSE

= 90% of I

= 90% of I

=2A (see Figure 6)

<4V, 0.5A<Iout<4A

SENSE

=10% of I

(see Figure 4.)

SENSEmax

SENSEmax

SENSE max

SENSEMAX,

OUTMAX

SENSE max

50 100 µs

520µs

80 250 µs

65 µs

100 250 µs

Figure 4. Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

t

DSENSE2H

t

DSENSE1L

Figure 5. Output voltage drop limitation

Vcc-V

out

Tj=150oC

V

on

T

=25oC

j

t

DSENSE1H

=-40oC

T

j

t

DSENSE2L

V

on/Ron(T)

12/31

I

out

VN5050AJ-E Electrical specifications

Figure 6. Delay response time between rising edge of ouput current and rising

edge of current sense (CS enabled)

V

IN

∆

t

DSENSE2H

t

I

OUT

90% I

OUTMAX

I

OUTMAX

t

I

SENSE

Figure 7. Switching characteristics

V

OUT

dV

OUT

INPUT

/dt

(on)

t

d(on)

t

Won

80%

t

r

90% I

10%

I

SENSEMAX

SENSEMAX

t

d(off)

t

Woff

90%

t

t

dV

/dt

OUT

(off)

f

t

t

13/31

Electrical specifications VN5050AJ-E

Figure 8. I

I

/ I

out

sense

2800

2600

2400

2200

2000

18 0 0

16 0 0

14 0 0

12 0 0

1 1,5 2 2,5 3 3,5 4 4,5 5

OUT/ISENSE

max Tj = -40 °C to 150 °C

max Tj = 25 °C to 150 °C

min Tj = 25 °C to 150 °C

min Tj = -40 °C to 150 °C

Vs. I

(see Table 10. for details)

OUT

I

(A)

OUT

typical value

Figure 9. Maximum current sense ratio drift vs load current

dk/k(%)

15

10

5

0

-5

-10

-15
1234

I

(A)

OUT

Note: Parameter guaranteed by design; it is not tested.

14/31

VN5050AJ-E Electrical specifications

Table 11. Truth table

Conditions Input Output Sense (V

Normal operation

L

H

L
H

CSD

0

Nominal

=0V)

(1)

Overtemperature

Undervoltage

Short circuit to GND
(Rsc ≤ 10 mΩ)

Short circuit to V

CC

Negative output voltage
clamp

1. If the V
and external circuit.

is high, the SENSE output is at a high impedance, its potential depends on leakage currents

CSD

L

H

L

H

L
H
H

L
H

L
L

L
L

L
L
L

V

SENSEH

H
H

0

V

SENSEH

0
0

0

0 if T

< T

j

if Tj > T

0

< Nominal

TSD

TSD

LL 0

15/31

Electrical specifications VN5050AJ-E

Table 12. Electrical transient requirements

ISO 7637-2:

Test levels

2004(E)

Tes t puls e

III IV

1 -75V -100V 5000 pulses 0.5 s 5 s 2 ms, 10 Ω

2a +37V +50V 5000 pulses 0.2 s 5 s 50 µs, 2 Ω

3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω

3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω

4-6V-7V1 pulse

5b

(2)

+65V +87V 1 pulse 400 ms, 2 Ω

Number of

pulses or

test times

Burst cycle/pulse

repetition time

Delays and
Impedance

100 ms, 0.01

Ω

ISO 7637-2:

Test level results

(1)

2004(E)

Tes t puls e

III IV

1C C

2a C C

3a C C

3b C C

4C C

(2)

5b

1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

CC

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

E

One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.

16/31

VN5050AJ-E Electrical specifications

Figure 10. Waveforms

NORMAL OPERATION

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

UNDERVOLTAGE

V

V

CC

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

V

USD

USDhyst

INPUT

CS_DIS

LOAD VOLTAGE

LOAD CURRENT

SENSE CURRENT

T

j

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

T

R

T

T

TSD

RS

current

limitation

<Nominal

power
limitation

SHORT TO V

CC

<Nominal

OVERLOAD OPERATION

thermal cycling

SHORTED LOAD NORMAL LOAD

I

LIMH

I

LIML

V

SENSEH

17/31

Electrical specifications VN5050AJ-E

2.4 Electrical characteristics curves

Figure 11. Off state output current Figure 12. High level input current

TBD

Figure 13. Input clamp voltage Figure 14. Input low level

Figure 15. Input high level Figure 16. Input hysteresis voltage

18/31

VN5050AJ-E Electrical specifications

Figure 17. On state resistance vs. T

case

Figure 18. On state resistance vs. V

Figure 19. Undervoltage shutdown Figure 20. Turn-On voltage slope

CC

Figure 21. I

LIMH

Vs. T

case

TBD

Figure 22. Turn-Off voltage slope

19/31

Electrical specifications VN5050AJ-E

Figure 23. CS_DIS high level voltage Figure 24. CS_DIS clamp voltage

Figure 25. CS_DIS low level voltage

20/31

VN5050AJ-E Application information

3 Application information

Figure 26. Application schematic

+5V

V

CC

R

prot

µ

C

.

R

prot

R

prot

R

SENSE

C

ext

CS_DIS

INPUT

CURRENT SENSE

V

GND

GND

R

GND

D

GND

OUTPUT

D

ld

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against
reverse battery.

3.1.1 Solution 1: resistor in the ground line (R

This can be used with any type of load.

The following show how to dimension the R

1. R

2. R

where -I

≤ 600mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

S(on)max

GND

)

)

maximum rating section of the device datasheet.

Power dissipation in R

P

= (-VCC)2/ R

D

(when VCC<0 during reverse battery situations) is:

GND

GND

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.

Please note that, if the microprocessor ground is not shared by the device ground, then the
R

will produce a shift (I

GND

S(on)max

* R

GND

values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R

GND

.

resistor:

GND

) in the input thresholds and the status output

GND

only)

S(on)max

becomes the sum of the

21/31

Application information VN5050AJ-E

If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.

3.1.2 Solution 2: diode (D

Note that a resistor (R

GND

) in the ground line

GND

=1kΩ) should be inserted in parallel to D

an inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (j600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V

maximum DC rating. The same applies if the device is subject to transients on the VCC

CC

line that are greater than those shown in the ISO T/R 7637/1 table.

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the

The value of these resistors is a compromise between the leakage current of
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
I/Os:

-V

µC I/O pins from latching up.

≤ R

CCpeak/Ilatchup

prot

≤ (V

OHµC-VIH-VGND

) / I

IHmax

if the device drives

GND

) in line to

prot

µC and the

µC

Equation 1:

For the following conditions:

V

I

latchup

V

5kΩ ≤ R

CCpeak

OHµC

= - 100V

≥ 20mA

≥ 4.5V

≤ 180kΩ.

prot

Recommended values are:

R

=10kΩ, C

prot

22/31

EXT

=10nF

VN5050AJ-E Application information

3.4 Maximum demagnetization energy (VCC = 13.5V)

Figure 27. Maximum turn Off current versus inductance

100

A

A

B

B

C

10

I (A)

1

0,1110100L (mH)

C

VIN, I

A: T

B: T

C: T

L

= 150°C single pulse

jstart

= 100°C repetitive pulse

jstart

= 125°C repetitive pulse

jstart

Demagnetization Demagnetization Demagnetization

Note: Values are generated with R

demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.

=0 Ω. In case of repetitive pulses, T

L

(at beginning of each

jstart

t

23/31

Package and PCB thermal data VN5050AJ-E

4 Package and PCB thermal data

4.1 PowerSSO-12™ thermal data

Figure 28. PowerSSO-12™ PC Board

Note: Layout condition of R

area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70 µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm

Figure 29. R

RTHj_amb(°C/W)

thj-amb

65

60

55

50

45

40

35

0246810

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

Vs. PCB copper area in open box free air condition

PCB Cu heatsink area (cm^2)

24/31

VN5050AJ-E Package and PCB thermal data

Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse

ZTH (°C/W)

100

10

1

0,1

0,001 0,01 0,1 1 10 100 1000

Time (s)

Equation 2: pulse calculation formula

Z

THδ

where δ = t

R

TH

P

/T

δ Z

THtp

1 δ–()+⋅=

Footprint

2 cm

8 cm

2

2

Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™

a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

(a)

25/31

Package and PCB thermal data VN5050AJ-E

Table 13. Thermal parameter

Area/island (cm2)Footprint28

R1 (°C/W) 0.7

R2 (°C/W) 2.8

R3 (°C/W) 3

R4 (°C/W) 8 8 7

R5 (°C/W) 22 15 10

R6 (°C/W) 26 20 15

C1 (W.s/°C) 0.001

C2 (W.s/°C) 0.0025

C3 (W.s/°C) 0.0166

C4 (W.s/°C) 0.2 0.1 0.1

C5 (W.s/°C) 0.27 0.8 1

C6 (W.s/°C) 3 6 9

26/31

VN5050AJ-E Package information

5 Package information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.2 Package mechanical data

Figure 32. PowerSSO-12™ package dimensions

27/31

Package information VN5050AJ-E

Table 14. PowerSSO-12™ mechanical data

Symbol

Min. Typ. Max.

A 1.250 1.620

A1 0.000 0.100

A2 1.100 1.650

B 0.230 0.410

C 0.190 0.250

D 4.800 5.000

E 3.800 4.000

e0.800

H 5.800 6.200

h 0.250 0.500

L 0.400 1.270

Millimeters

k0° 8°

X 2.200 2.800

Y 2.900 3.500

ddd 0.100

28/31

VN5050AJ-E Package information

5.3 Packing information

Figure 33. PowerSSO-12™ tube shipment (no suffix)

B

C

Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532

A

A1.85
B6.75
C (± 0.1) 0.6

All dimensions are in mm.

Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm min

Empty components pockets
saled with cover tape.

User direction of f eed

Start

No componentsNo components Components

500mm min

29/31

Revision history VN5050AJ-E

6 Revision history

Table 15. Document revision history

Date Revision Changes

24-Jan-2006 1 Initial release.

Jul-2006 2 Minor updates.

Document reformatted.

Table 14: PowerSSO-12™ mechanical data, X and Y values (slug

06-Feb-2007 3

13-Sep-2007 4

7-Dec-2007 5

12-Feb-2008 6

dimensions) updated.

Table 10: Current sense (8V<VCC<16V) t

DSENSE2H

entry updated.

Figure 27: Maximum turn Off current versus inductance and
Table 13: Thermal parameter updated.

Document reformatted and restructured.
Contents and lists of tables and figures added.

Figure 2: Configuration diagram (top view) updated: pins 1-6-7-12

left unconnected (N.C).

Table 4: Absolute maximum ratings: updated E
Ta bl e 1 0 : added dk1/k1, dk2/k2, dk3/k3, ∆t

MAX entries.

DSENSE2H

.

Added Figure 6: Delay response time between rising edge of ouput

current and rising edge of current sense (CS enabled).

Updated Figure 8: I

OUT/ISENSE

Vs. I

(see Table 10. for details).

OUT

Added Figure 9: Maximum current sense ratio drift vs load current.

Table 12: Electrical transient requirements : updated test level values

III and IV for test pulse 5b and notes.
Corrected Figure 30: PowerSSO-12™ thermal impedance junction

ambient single pulse.

Figure 2: Configuration diagram (top view): added note.

Updated Table 10: Current sense (8V<V
– changed t
– added I

OL

DSENSE2H

parameter.

max value from 300 µs to 250µs.

<16V) :

CC

Updated Section 4.1: PowerSSO-12™ thermal data:
– changed Figure 29: Rthj-amb Vs. PCB copper area in open box

free air condition.

– changed Figure 30: PowerSSO-12™ thermal impedance junction

ambient single pulse.

– updated Table 13: Thermal parameter:

R1 value changed from 0.6 to 0.7 °C/W.
R3 value changed from 6.5 to 3 °C/W
R4 values changed from 10 /10 /9 to 8 /8 /7 °C/W.
C3 value changed from 0.022 to 0.0166 W.s/°C

Corrected typing error in Table 10: Current sense (8V<V
changed I

test condition from VIN = 0V to VIN = 5V.

OL

<16V) :

CC

30/31

VN5050AJ-E

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31/31