Datasheet VN5016AJ-E Datasheet (ST)

Features

VN5016AJ-E

Single channel high side driver with analog

current sense for automotive applications

Max supply voltage V

Operating voltage range V

Max On-State resistance (per ch.)

Current limitation (typ) I

Off state supply current I

■ Main features

CC

CC

R

ON

LIMH

S

4.5 to 36V

16 mΩ

– Inrush current active management by

power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC

european directive

■ Diagnostic functions

– Proportional load current sense
– High current sense precision for wide range

currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage

■ Protection

– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss

of V

CC

– Thermal shut down
– Reverse battery protection
– Electrostatic discharge protection

Table 1. Device summary

41V

65A

2 µA

PowerSSO-12

Application

■ All types of resistive, inductive and capacitive

loads

Description

The VN5016AJ-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology. It is intended for driving resistive or
inductive loads with one side connected to
ground. Active V
device against low energy spikes (see ISO7637
transient compatibility table). This device
integrates an analog current sense which delivers
a current proportional to the load current
(according to a known ratio) when CS_DIS is
driven low or left open.

When CS_DIS is driven high, the CURRENT
SENSE pin is in a high impedance condition.

Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.

pin voltage clamp protects the

CC

Package

Tube Tape & Reel

PowerSSO-12 VN5016AJ-E VN5016AJTR-E

February 2008 Rev 7 1/32

Order codes

www.st.com

32

Contents VN5016AJ-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22

3.1.1 Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 22

3.1.2 Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 23

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.4 Maximum demagnetization energy (V

= 13.5V) . . . . . . . . . . . . . . . . . . 24

CC

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.2 PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3 PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32

VN5016AJ-E List of tables

List of tables

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7. Switching (V

Table 9. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 8. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10. Current sense (8V<V

Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 13. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 14. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CC

3/32

List of figures VN5016AJ-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5. Delay response time between rising edge of ouput current and rising edge of current sense

(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 6. IOUT/ISENSE Vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 17. On state resistance vs. T
Figure 18. On state resistance vs. V

Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 20. Turn - On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 21. I

LIMH

vs. T

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 22. Turn - Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 27. Maximum turn Off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 28. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 29. Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 25

Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 26

Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 26

Figure 32. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 33. PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4/32

VN5016AJ-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

CC

V

CC

CLAMP

UNDERVOLTAGE

LIM

PwCLAMP

I

OUT

I

V

DSLIM

LIM

K

GND

INPUT

CS_DIS

DRIVER

LOGIC

Pwr

OVERTEMP.

Table 2. Pin function

Name Function

V

CC

OUTPUT Power output.

GND

INPUT

CURRENT

SENSE

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

Battery connection.

Ground connection. Must be reverse battery protected by an external
diode/resistor network.

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.

Analog current sense pin, delivers a current proportional to the load current.

OUTPUT

CURRENT
SENSE

5/32

Block diagram and pin description VN5016AJ-E

Figure 2. Configuration diagram (top view)

TAB = V

V

CC

GND

INPUT

CURRENT SENSE

CS_DIS

V

CC

Table 3. Suggested connections for unused and N.C. pins

Connection / Pin Current Sense N.C. Output Input CS_DIS

Floating N.R.

To ground

(1) Not recommended.

Through 1KΩ

(1)

resistor

1
2
3
4
5

6

XX X X

XN.R.

(1)

12
11
10

9
8
7

Through 10KΩ

cc

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

OUTPUT

resistor

Through 10KΩ

resistor

6/32

VN5016AJ-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I

S

V

CC

V

F

V

CC

I

Note: V

Fn

V

= V

CSD

CSD

- VCC during reverse battery condition.

OUTn

I

IN

V

IN

CS_DIS

INPUT

CURRENT SENSE

2.1 Absolute maximum ratings

Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to the conditions in this section for extended

periods may affect device reliability. Refer also to the STMicroelectronics SURE Program

and other relevant quality documents.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

GND

OUTPUT

I

GND

I

OUT

I

SENSE

V

SENSE

V

OUT

V

CC

-V

-I

GND

I

OUT

-I

OUT

I

IN

I

CSD

-I

CSENSE

V

CSENSE

E

MAX

DC supply voltage 41 V

Reverse DC supply voltage 0.3 V

CC

DC reverse ground pin current 200 mA

DC output current Internally limited A

Reverse DC output current 30 A

DC input current -1 to 10 mA

DC current sense disable input current -1 to 10 mA

DC reverse CS pin current 200 mA

Current sense maximum voltage

VCC-41

+V

CC

Maximum switching energy
(L=0.75mH; R

= I

I

OUT

limL

(Typ.) )

=0Ω; V

L

=13.5V; T

bat

jstart

=150ºC;

304 mJ

7/32

V
V

Electrical specifications VN5016AJ-E

Table 4. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Electrostatic discharge (Human Body Model: R=1.5KΩ;

V

V

ESD

ESD

T

C=100pF)

- INPUT

- CURRENT SENSE

- CS_DIS

- OUTPUT

- V

CC

4000
2000
4000
5000
5000

Charge device model (CDM-AEC-Q100-011) 750 V

Junction operating temperature -40 to 150 °C

T

j

Storage temperature -55 to 150 °C

stg

V
V
V
V
V

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter Max value Unit

R

thj-case

R

thj-amb

Thermal resistance junction-case 0.5 °C/W

Thermal resistance junction-ambient See Figure 29 °C/W

8/32

VN5016AJ-E Electrical specifications

2.3 Electrical characteristics

8V<VCC<36V; -40°C<Tj<150°C, unless otherwise specified.

.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

CC

V

USD

V

USDhyst

R

ON

V

clamp

I

I

L(off)

V

(1) PowerMOS leakage included.

Operating supply voltage 4.5 13 36 V

Undervoltage shutdown 3.5 4.5 V

Undervoltage Shut-down
hysteresis

On state resistance

Clamp voltage IS= 20mA 41 46 52 V

Supply current

S

Off state output current

Output - VCC diode
voltage

F

I

OUT

I

OUT

I

OUT

Off State; V
VIN=V

On State; V
I

OUT

VIN=V

=25°C

T

j

VIN=V

=125°C

T

j

I

OUT

0.5 V

16
32
20

(1)

5

3µAmA

mΩ
mΩ
mΩ

= 5A; Tj= 25°C
= 5A; Tj= 150°C
= 5A; VCC= 5V; Tj= 25°C

=13V; Tj=25°C;

CC

OUT=VSENSE=VCSD

=13V; VIN=5V;

CC

=0V

2

1.5

(1)

=0A

=0V; VCC=13V;

OUT

=0V; VCC=13V;

OUT

000.01 3
µA

5

= 6A; Tj= 150°C 0.7 V

Table 7. Switching (VCC=13V, Tj=25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

(dV

(dV

t

d(on)

t

d(off)

OUT

OUT

W

W

OFF

Turn-On delay time RL= 2.6Ω (see Figure 8)35µs

Turn-Off delay time RL= 2.6Ω (see Figure 8)50µs

/dt)onTurn-On voltage slope RL= 2.6Ω (see Figure 8)See Figure 20 V/ µs

/dt)

Turn-Off voltage slope RL= 2.6Ω (see Figure 8)See Figure 22 V/ µs

off

Switching energy losses

ON

during t

won

Switching energy losses
during t

woff

RL= 2.6Ω (see Figure 8)1.1mJ

RL= 2.6Ω (see Figure 8)0.8mJ

9/32

Electrical specifications VN5016AJ-E

Table 8. Logic input

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

I

IL

V

I

IH

V

I(hyst)

V

ICL

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

V

CSCL

Table 9. Protections and diagnostics

Input low level voltage 0.9 V

IL

Low level input current VIN=0.9V 1 µA

Input high level voltage 2.1 V

IH

High level input current VIN=2.1V 10 µA

Input hysteresis voltage 0.25 V

Input clamp voltage

CS_DIS low level voltage 0.9 V

Low level CS_DIS
current

CS_DIS high level
voltage

High level CS_DIS
current

CS_DIS hysteresis
voltage

CS_DIS clamp voltage

(1)

IIN=1mA

=-1mA

I

IN

=0.9V 1 µA

V

CSD

5.5

-0.7

2.1 V

V

=2.1V 10 µA

CSD

0.25 V

I

CSD

I

CSD

=1mA

=-1mA

5.5

-0.7

7V

V

7V

V

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

=13V

I

limH

I

limL

T

TSD

T

T

RS

T

HYST

V

DEMAG

V

ON

(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related

diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

DC short circuit current

Short circuit current
during thermal cycling

Shutdown temperature 150 175 200 °C

Reset temperature

R

Thermal reset of
STATUS

Thermal hysteresis

TSD -TR

)

(T

Turn-Off output voltage
clamp

Output voltage drop
limitation

CC

5V<V

V

I

OUT

I

OUT

T

<36V

CC

=13V TR<Tj<T

CC

=2A; VIN=0; L=6mH

=0.3A;

= -40°C...+150°C

j

(see Figure 9)

TSD

46 65 91

91

24 A

T

+1 TRS +5 °C

R

S

135 °C

7°C

VCC-41

VCC-46

VCC-52

25 mV

A
A

V

10/32

VN5016AJ-E Electrical specifications

Table 10. Current sense (8V<VCC<16V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

=0.25A;

OUT

K

K

dK

1/K1

K

dK

2/K2

K

dK

3/K3

I

SENSE0

I

0

OUT/ISENSE

I

1

OUT/ISENSE

(1)

Current sense ratio drift

I

2

OUT/ISENSE

(1)

Current sense ratio drift

I

3

OUT/ISENSE

(1)

Current sense ratio drift

Analog sense leakage
current

V
T

I
V

Tj= -40°C...150°C
I

V
T

I
V
T

I
V

T
I

V
T

I
V
T

I
V

Tj= -40°C...150°C
I

V
T

I
V
T

I
V
T
V
T

=0.5V;V

SENSE

= -40°C...150°C

j

=4A; V

OUT

CSD

OUT

CSD

= 25°C...150°C

j

OUT

CSD

=-40 °C to 150 °C

J

OUT

CSD

=-40°C...150°C

j

OUT

CSD

=25°C...150°C

j

OUT

CSD

=-40 °C to 150 °C

J

OUT

CSD

OUT

CSD

= 25°C...150°C

j

OUT

CSD

=-40 °C to 150 °C

J

OUT

CSD

=-40°C...150°C

j

CSD

=-40°C...150°C

j

SENSE

=0V;

=4A; V

SENSE

=0V;

=4A; V

SENSE

=0V;

=10A; V

SENSE

=0V;

=10A; V

SENSE

=0V;

=10A; V

SENSE

=0V;

=25A; V

SENSE

=0V;

=25A; V

SENSE

=0V;

=25A; V

SENSE

=0V;

=0A; V

SENSE

=5V; VIN=0V;

=0V; VIN=5V;

CSD

=0.5V;

=0.5V;

= 0.5V;

=4V;

=4V;

= 4V;

=4V;

=4V;

= 4V;

=0V;

=0V;

2760 5010 7240

3510

4560

5690

3770

4560

5350

-8 +8 %

4180

4570

5060

4250

4570

4890

-4 +4 %

4360

4500

4700

4380

4500

4620

-3 +3 %

0

0

1

2

µA

µA

I

OL

Openload ON state
current detection
threshold

=2A; V

I

OUT

=5V; VIN=5V;

V

CSD

=-40°C...150°C

T

j

VIN = 5V, I

=0V;

SENSE

0

= 5 µA 10 45 mA

SENSE

1

11/32

µA

Electrical specifications VN5016AJ-E

Table 10. Current sense (8V<VCC<16V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

SENSE

Max analog sense
output voltage

I

OUT

=15A; V

Analog sense output

V

SENSEH

voltage in
overtemperature

V

CC

=13V; R

condition

Analog sense output

I

SENSEH

current in
overtemperature

V

CC

=13V; V

condition

Delay response time

t

DSENSE1H

from falling edge of
CS_DIS pin

Delay response time

t

DSENSE1L

from rising edge of
CS_DIS pin

Delay response time

t

DSENSE2H

from rising edge of
INPUT pin

Delay response time

∆

t

DSENSE2H

between rising edge of
output current and rising
edge of current sense

Delay response time

t

DSENSE2L

from falling edge of
INPUT pin

(1) Parameter guaranteed by design; it is not tested.

V

SENSE

I

SENSE

(see Figure 4)

V

SENSE

I

SENSE

(see Figure 4)

V

SENSE

I

SENSE

(see Figure 4)

V

SENSE

I

SENSE

I

OUT

I

OUTMAX

V

SENSE

I

SENSE

(see Figure 4)

=0V; 5 V

CSD

=3.9KΩ 9V

SENSE

=5V 8 mA

SENSE

<4V, 1.5A<Iout<25A

= 90% of I

SENSE max

<4V, 1.5A<Iout<25A

= 10% of I

SENSE max

<4V, 1.5A<Iout<25A

= 90% of I

SENSE max

<4V,

= 90% of I

= 90% of I

SENSEMAX,

OUTMAX

=15A (see Figure 5)

<4V, 1.5A<Iout<25A

=10% of I

SENSE max

50 100 µs

520µs

270 400 µs

280 µs

100 250 µs

12/32

VN5016AJ-E Electrical specifications

Figure 4. Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

t

DSENSE2H

t

DSENSE1L

t

DSENSE1H

t

DSENSE2L

Figure 5. Delay response time between rising edge of ouput current and rising

edge of current sense (CS enabled)

V

IN

∆

t

DSENSE2H

I

OUT

I

SENSE

90% I

OUTMAX

90% I

I

OUTMAX

I

SENSEMAX

SENSEMAX

t

t

t

13/32

Electrical specifications VN5016AJ-E

Figure 6. I

I

out

OUT/ISENSE

/ I

sense

6000

5500

5000

max Tj = 25 °C to 150 °C

4500

min Tj = 25 °C to 150 °C

4000

min Tj = -40 °C to 150 °C

3500

3000

4 8 12 16 20 24

Vs. I

max Tj = -40 °C to 150 °C

(see Ta bl e 1 0 for details)

OUT

I

OUT

typical value

(A)

Figure 7. Maximum current sense ratio drift vs load current

dk/k(%)

15

10

5

0

-5

-10

-15
4 7 10 13 16 19 22 25

I

(A)

OUT

Note: Parameter guaranteed by design; it is not tested.

14/32

VN5016AJ-E Electrical specifications

Figure 8. Switching characteristics

V

OUT

t

Won

t

Woff

80%

dV

/dt

OUT

INPUT

(on)

t

d(on)

t

r

10%

Figure 9. Output voltage drop limitation

Vcc-V

out

Tj=150oC

t

d(off)

90%

t

f

T

j

=25oC

=-40oC

T

j

dV

OUT

/dt

(off)

t

t

V

on

I

Von/R

on(T)

out

15/32

Electrical specifications VN5016AJ-E

Table 11. Truth table

Conditions Input Output Sense (V

Normal operation

CSD

L

H

L

H

0

Nominal

=0V)

(1)

Overtemperature

Undervoltage

Short circuit to GND
(Rsc ≤ 10 mΩ)

Short circuit to V

CC

L

H

L

H

L
H
H

L
H

L
L

V

SENSEH

L
L

L
L
L

0 if T

V

SENSEH

H
H

< Nominal

Negative output voltage clamp L L 0

(1) If the V

and external circuit.

is high, the SENSE output is at a high impedance, its potential depends on leakage currents

CSD

0

0
0

0

< T

j

TSD

if Tj > T

0

TSD

16/32

VN5016AJ-E Electrical specifications

Table 12. Electrical transient requirements

ISO 7637-2:

Test levels

2004(E)

Test pulse

III IV

1 -75V -100V 5000 pulses 0.5 s 5 s 2 ms, 10 Ω

2a +37V +50V 5000 pulses 0.2 s 5 s 50 µs, 2 Ω

3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω

3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω

4 -6V -7V 1 pulse 100 ms, 0.01Ω

5b

(2)

+65V +87V 1 pulse 400 ms, 2 Ω

(1)

Number of

pulses or

test times

Burst cycle/pulse

repetition time

Delays and
Impedance

ISO 7637-2:

Test level results

(1)

2004(E)

Tes t puls e

III IV

1C C

2a C C

3a C C

3b C C

4C C

(2)

5b

(1) The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.

(2) Valid in case of external load dump clamp: 40V maximum referred to ground.

CC

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

E

One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.

17/32

Electrical specifications VN5016AJ-E

Figure 10. Waveforms

NORMAL OPERATION

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

UNDERVOLTAGE

V

V

CC

INPUT
CS_DIS

LOAD CURRENT

SENSE CURRENT

V

USD

USDhyst

INPUT

CS_DIS

LOAD VOLTAGE

LOAD CURRENT

SENSE CURRENT

T

j

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

T

R

T

T

TSD

RS

current

limitation

<Nominal

OVERLOAD OPERATION

power
limitation

SHORT TO V

CC

<Nominal

thermal cycling

SHORTED LOAD NORMAL LOAD

I

LIMH

I

LIML

V

SENSEH

18/32

VN5016AJ-E Electrical specifications

C)

2.4 Electrical characteristics curves

Figure 11. Off state output current Figure 12. High level input current

Ilo ff (u A)

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

-50 -25 0 25 50 75 100 125 150 175

Off S tate
Vcc=13V

Vin=Vout=0V

Tc (°C )

Iih (uA )

5

4.5

3.5

2.5

1.5

0.5

Vin=2.1V

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°

Figure 13. Input clamp voltage Figure 14. Input low level

Vicl (V)

7

6.75

6.5

6.25

6

5.75

Ii n =1m A

Vil (V)

4

3.5

3

2.5

2

1.5

5.5

5.25

5

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

Figure 15. Input high level Figure 16. Input hysteresis voltage

Vih (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

Vhyst (V)

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

19/32

Electrical specifications VN5016AJ-E

Figure 17. On state resistance vs. T

Ron (mOhm)

50

45

40

35

30

25

20

15

10

5

0

Io u t=5 A

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

case

Figure 18. On state resistance vs. V

Ron (mOhm)

40

35

30

25

20

15

10

5

0

0 5 10 15 20 25 30 35 40

Vcc (V)

Tc= 150°C

Tc= 125°C

Tc= 25°C

Tc= -40°Cv

Figure 19. Undervoltage shutdown Figure 20. Turn - On voltage slope

Vusd (V)

16

14

12

10

8

6

4

2

0

-50 -25 0 25 50 75 100 125 150 175

Figure 21. I

LIMH

vs. T

Tc (°C )

case

dV out/dt(on ) (V /ms )

1000

900

800

700

600

500

400

300

200

100

Vcc=13V

RI=2.6Ohm

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

Figure 22. Turn - Off voltage slope

CC

Ili mh (A )

80

75

Vcc=13V

70

65

60

55

50

45

40

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

20/32

(dVout/dt)off (V/ms)

1000

900

800

700

600

500

400

300

200

100

Vc c=13V

Rl=2.6Ohm

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

VN5016AJ-E Electrical specifications

Figure 23. CS_DIS high level voltage Figure 24. CS_DIS clamp voltage

Vcsdh (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

Figure 25. CS_DIS low level voltage

Vcsdl (V)

4

3.5

3

2.5

2

1.5

Vcsdcl (V)

8

7.5

6.5

5.5

4.5

Ic s d =1m A

7

6

5

4

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C )

21/32

Application Information VN5016AJ-E

3 Application Information

Figure 26. Application schematic

+5V

V

CC

R

prot

CS_DIS

D

ld

µC

R

prot

R

prot

R

SENSE

C

ext

INPUT

CURRENT SENSE

OUTPUT

GND

R

V

GND

GND

D

GND

3.1 GND protection network against reverse battery

3.1.1 Solution 1 : resistor in the ground line (R

This can be used with any type of load.

The following is an indication on how to dimension the R

1. R

2. R

where -I
maximum rating section of the device datasheet.

≤ 600mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

S(on)max

GND

).

)

GND

only)

GND

resistor.

Power Dissipation in R

P

= (-VCC)2/R

D

GND

(when VCC<0: during reverse battery situations) is:

GND

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the
R

will produce a shift (I

GND

S(on)max

* R

GND

values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R

22/32

GND

S(on)max

becomes the sum of the

) in the input thresholds and the status output

.

VN5016AJ-E Application Information

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).

3.1.2 Solution 2 : diode (D

A resistor (R

=1kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V

max DC rating. The same applies if the device is subject to transients on the VCC line

CC

that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the

The value of these resistors is a compromise between the leakage current of
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
I/Os.

µC I/Os pins to latch-up.

if the device drives an

GND

prot

) in line to

µC and the

µC

-V

CCpeak/Ilatchup

≤ R

prot

≤ (V

Calculation example:

For V

5kΩ ≤ R

CCpeak

prot

≤ 180kΩ.

= - 100V and I

Recommended values: R

OHµC-VIH-VGND

≥ 20mA; V

latchup

=10kΩ, C

prot

) / I

IHmax

≥ 4.5V

OHµC

=10nF.

EXT

23/32

Application Information VN5016AJ-E

3.4 Maximum demagnetization energy (V

Figure 27. Maximum turn Off current versus load inductance

100

A

B

C

10

I (A)

1

0,1 1 10 100L (mH)

= 13.5V)

CC

A: T

B: T

C: T

VIN, I

= 150°C single pulse

jstart

= 100°C repetitive pulse

jstart

= 125°C repetitive pulse

jstart

L

Demagnetization

Note: Values are generated with R

In case of repetitive pulses, T
must not exceed the temperature specified above for curves B and C.

Demagnetization

=0 Ω.

L

(at beginning of each demagnetization) of every pulse

jstart

Demagnetization

t

24/32

VN5016AJ-E Package and PCB thermal data

4 Package and PCB thermal data

4.1 PowerSSO-12™ thermal data

Figure 28. PowerSSO-12™ PC board

Note: Layout condition of R

area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm

Figure 29. R

RTHj_amb(°C/W)

thj-amb

65

60

55

50

45

40

35

30

0246810

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

vs. PCB copper area in open box free air condition

PCB Cu heatsink area (cm^2)

25/32

Package and PCB thermal data VN5016AJ-E

Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse

100

ZTH (°C/W)

10

1

0,1

0,0001 0,001 0,01 0,1 1 10 100 1000

Time (s)

Equation 1: pulse calculation formula

Z

THδ

where δ = t

R

TH

/T

P

δ Z

THtp

1 δ–()+⋅=

2 cm

Footprint

8 cm

2

2

Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™

(a )The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

(a)

26/32

VN5016AJ-E Package and PCB thermal data

Table 13. Thermal parameter

Area/island (cm2)Footprint28

R1 (°C/W) 0.1

R2 (°C/W) 0.2

R3 (°C/W) 4

R4 (°C/W) 8 8 7

R5 (°C/W) 22 15 10

R6 (°C/W) 26 20 15

C1 (W.s/°C) 0.0001

C2 (W.s/°C) 0.002

C3 (W.s/°C) 0.05

C4 (W.s/°C) 0.2 0.1 0.1

C5 (W.s/°C) 0.27 0.8 1

C6 (W.s/°C) 3 6 9

27/32

Package information VN5016AJ-E

5 Package information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.2 PowerSSO-12™ package information

Figure 32. PowerSSO-12™ package dimensions

28/32

VN5016AJ-E Package information

Table 14. PowerSSO-12™ mechanical data

Symbol

Min. Typ. Max.

A 1.250 1.620

A1 0.000 0.100

A2 1.100 1.650

B 0.230 0.410

C 0.190 0.250

D 4.800 5.000

E 3.800 4.000

e0.800

H 5.800 6.200

h 0.250 0.500

L 0.400 1.270

Millimeters

k0° 8°

X 1.900 2.500

Y 3.600 4.200

ddd 0.100

29/32

Package information VN5016AJ-E

5.3 PowerSSO-12™ packing information

Figure 33. PowerSSO-12™ tube shipment (no suffix)

B

C

Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532

A

A1.85
B6.75
C (± 0.1) 0.6

All dimensions are in mm.

Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

30/32

Top

cover

tape

End

500mm min

Empty components pockets
saled with cover tape.

User direction of feed

Start

No componentsNo components Components

500mm min

VN5016AJ-E Revision history

6 Revision history

Table 15. Document revision history

Date Revision Changes

30-Oct-2004 1 Initial release.

15-Jan-2005 2 Minor text changes.

11-May-2006 3 Document changed from Advance Data to maturity.

Changes minor formatting.

02-Feb-2007 4

02-Jul-2007 5

Added Figure 27: Maximum turn Off current versus load

inductance.

Added new disclaimer.

Ta bl e 4 : updated E
Ta bl e 1 0 : added dk1/k1, dk2/k2, dk3/k3, ∆t

MAX

entries.

DSENSE2H

.
Added Figure 5.
Updated Figure 6.
Added Figure 7.

Ta bl e 1 2 : updated test level values III and IV for test pulse 5b and

notes.
Added Section 3.4: Maximum demagnetization energy (V

CC

=

13.5V).
Figure 31: Thermal fitting model of a single channel HSD in

PowerSSO-12™: added notes.

09-Jan-2007 6

12-Feb-2008 7

Updated Table 10: Current sense (8V<VCC<16V) :
– Changed dK3/K3 values from ± 2 to ± 3 %.
– Added I
– Changed ∆t

parameter.

OL

DSENSE2H

max value from 120 to 280 µs.

Updated Figure 7: Maximum current sense ratio drift vs load

current with new dK/K values.

Updated Section 4.1: PowerSSO-12™ thermal data:
– Changed Figure 29: Rthj-amb vs. PCB copper area in open box

free air condition.

– Changed Figure 30: PowerSSO-12™ thermal impedance

junction ambient single pulse.

– Updated Table 13: Thermal parameter:

R3 value changed from 7 to 4 °C/W.
R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W.

Corrected typing error in Table 10: Current sense (8V<V
changed I

test condition from VIN = 0V to VIN = 5V.

OL

<16V) :

CC

31/32

VN5016AJ-E

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32/32