Datasheet VN5010AK-E Datasheet (ST)

Features

Max supply voltage V

Operating voltage range V

Max on-state resistance R

Current limitation (typ) I

Off-state supply current (typ) I

CC

CC

ON

LIMH

S

VN5010AK-E

High side driver with analog current sense

for automotive applications

41 V

4.5 to 36 V

10 mΩ

65 A

2µA

PowerSSO-24

– Reverse battery protection (see Figure 26)
– Electrostatic discharge protection

TM

■ Main features

– Inrush current active management by

power limitation
– Very low standby current
– 3.0v CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC

European directive

■ Diagnostic functions

– Proportional load current sense
– High current sense precision for wide range

currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage

■ Protections

– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss

of V

CC

– Thermal shutdown

Table 1. Device summary

Package

PowerSSO-24

TM

Application

■ All types of resistive, inductive and capacitive

loads

Description

The VN5010AK-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology. It is intended for driving resistive or
inductive loads with one side connected to
ground. Active V
device against low energy spikes (see ISO7637
transient compatibility table). This device
integrates an analog current sense which delivers
a current proportional to the load current
(according to a known ratio) when CS_DIS is
driven low or left open. When CS_DIS is driven
high, the CURRENT SENSE pin is in a high
impedance condition. Output current limitation
protects the device in overload condition. In case
of long overload duration, the device limits the
dissipated power to safe level up to thermal
shutdown intervention. Thermal shutdown with
automatic restart allows the device to recover
normal operation as soon as fault condition
disappears.

Order codes

Tub e Tap e a n d r eel

VN5010AK-E VN5010AKTR-E

pin voltage clamp protects the

CC

July 2009 Doc ID 13218 Rev 6 1/31

www.st.com

1

Contents VN5010AK-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21

3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21

3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4 Maximum demagnetization energy (V

=13.5V) . . . . . . . . . . . . . . . . . . . 23

CC

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 PowerSSO-24TM thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31 Doc ID 13218 Rev 6

VN5010AK-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7. Switching (VCC=13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 8. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 9. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10. Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 12. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 13. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 14. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Doc ID 13218 Rev 6 3/31

List of figures VN5010AK-E

List of figures

Figure 1. Connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4. Delay response time between rising edge of output current and rising edge of Current Sense

(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. IOUT/ISENSE vs IOUT (see Table 10 for details) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 10. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16. On-state resistance vs T
Figure 17. On-state resistance vs V

Figure 18. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 19. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 20. I

LIMH

vs T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

case

Figure 21. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 22. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 23. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 25. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 26. Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 27. PowerSSO-24

Figure 28. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 29. PowerSSO-24

TM

PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TM

thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 25

Figure 30. Thermal fitting model of a double channel HSD in PowerSSO-24

Figure 31. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 32. PowerSSO-24
Figure 33. PowerSSO-24

TM

tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

TM

tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CC

TM

. . . . . . . . . . . . . . . . . 25

4/31 Doc ID 13218 Rev 6

VN5010AK-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

CC

V

CC

CLAMP

UNDERVOLTAGE

DRIVER

GND

LOGIC

INPUT

CS_DIS

Table 2. Pin function

Name Function

V

CC

Battery connection.

OUTPUT Power output.

GND

INPUT

Ground connection. Must be reverse battery protected by an external

diode/resistor network.

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output

switch state.

Pwr

LIM

OVERTEMP.

I

OUT

PwCLAMP

I

LIM

V

DSLIM

K

OUTPUT

CURRENT
SENSE

CURRENT

SENSE

Analog current sense pin, delivers a current proportional to the load current.

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

Doc ID 13218 Rev 6 5/31

Block diagram and pin description VN5010AK-E

Figure 2. Connection diagram (top view)

V

CC

GND

NC
NC

INPUT

NC

CURRENT SENSE

NC

CS_DIS

NC
NC

V

CC

1
2
3
4
5
6

7
8
9
10
11
12

24
23
22
21
20
19

18
17
16
15
14
13

NC
NC
NC
OUTPUT
OUTPUT
OUTPUT

OUTPUT
OUTPUT
OUTPUT
NC
NC
NC

TAB = Vc c

Table 3. Suggested connections for unused and not connected pins

Connection/pin Current sense N.C. Output Input CS_DIS

Floating N.R.

To ground

1. Not recommended.

(1)

Through 1 kΩ

resistor

XX X X

XN.R.

Through 10 kΩ

resistor

Through 10 kΩ

resistor

6/31 Doc ID 13218 Rev 6

VN5010AK-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I

S

V

CC

V

CC

I

V

CSD

CSD

I

IN

CS_DIS

INPUT

CURRENT SENSE

V

IN

Note: V

Fn

= V

- VCC during reverse battery condition.

OUT

2.1 Absolute maximum ratings

Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in this section for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality documents.

Table 4. Absolute maximum ratings

GND

OUTPUT

I

GND

I

OUT

I

SENSE

V

SENSE

V

OUT

Symbol Parameter Value Unit

V

-V

- I

I

OUT

- I

I

CSD

-I

CSENSE

DC supply voltage 41 V

CC

Reverse DC supply voltage 0.3 V

CC

DC reverse ground pin current 200 mA

GND

DC output current

Reverse DC output current 30 A

OUT

DC input current -1 to 10 mA

I

IN

Internally

limited

DC current sense disable input current -1 to 10 mA

DC reverse CS pin current 200 mA

A

Doc ID 13218 Rev 6 7/31

Electrical specifications VN5010AK-E

Table 4. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

V

V

CSENSE

E

MAX

V

ESD

V

ESD

T

Current sense maximum voltage

Maximum switching energy (single pulse)
(L=1.25mH; R

=0Ω; V

L

=13.5V; T

bat

jstart

=150ºC; I

OUT

= I

limL

(typ.))

Electrostatic discharge (Human Body Model: R=1.5KΩ; C=100pF)
– Input
– Current Sense
–CS_DIS
– Output
–V

CC

CC

+V

609 mJ

4000
2000
4000
5000
5000

Charge device model (CDM-AEC-Q100-011) 750 V

Junction operating temperature -40 to 150 °C

j

-41

CC

V
V

V

T

Storage temperature -55 to 150 °C

stg

Table 5. Thermal data

Symbol Parameter Max value Unit

R

thj-case

R

thj-amb

Thermal resistance junction case (max) 0.3 °C/W

Thermal resistance junction ambient (max) See Figure 29 °C/W

2.2 Electrical characteristics

Values specified in this section are for 8 V< VCC< 36 V; -40 °C< Tj< 150 °C, unless
otherwise stated (for each channel).

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

USDhyst

R

V

clamp

Operating supply

CC

voltage

Undervoltage

USD

shutdown

Undervoltage
shutdown hysteresis

On-state resistance

ON

Clamp voltage ICC= 20 mA 41 46 52 V

Supply current

I

S

I

= 6A; Tj= 25°C

OUT

= 6A; Tj= 150°C

I

OUT

=6A; VCC=5V;Tj=25°C

I

OUT

Off-state; V
V

IN=VOUT=VSENSE=VCSD

On-state; V

= 13V; Tj= 25°C;

CC

=13V; VIN=5V; I

CC

=0V

OUT

=0A

4.5 13 36 V

3.5 4.5 V

0.5 V

10

mΩ

20

mΩ

13

mΩ

(1)

(1)

5

3µAmA

2

1.5

8/31 Doc ID 13218 Rev 6

VN5010AK-E Electrical specifications

Table 6. Power section (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

L(off)

V

1. PowerMOS leakage included.

Table 7. Switching (VCC=13V)

Off-state output
current

Output - VCC diode

F

voltage

V

IN=VOUT

V

IN=VOUT

-I

OUT

=0V; VCC= 13V; Tj= 25°C
=0V; VCC= 13V; Tj= 125°C

= 10A; Tj= 150°C 0.7 V

000.01 3
5

Symbol Parameter Test conditions Min. Typ. Max. Unit

t

d(on)

t

d(off)

(dV

OUT

(dV

OUT

W

ON

W

OFF

Table 8. Logic input

Turn-on delay time RL= 2.6Ω (see Figure 8)- 35 -µs

Turn-off delay time RL= 2.6Ω (see Figure 8)- 65 -µs

Turn-on voltage

/dt)

on

slope

Turn-off voltage

/dt)

off

slope

Switching energy
losses during t

Switching energy
losses during t

won

woff

= 2.6Ω -

R

L

R

= 2.6Ω -

L

RL= 2.6Ω (see Figure 8)- 1.5 -mJ

RL= 2.6Ω (see Figure 8)- 0.8 -mJ

See

Figure 20

See

Figure 22

-V/µs

-V/µs

µA

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

I

V

I(hyst)

V

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

V

CSCL

I

Input low level voltage 0.9 V

IL

Low level input current VIN= 0.9V 1 µA

IL

Input high level voltage 2.1 V

IH

High level input current VIN= 2.1V 10 µA

IH

Input hysteresis voltage 0.25 V

Input clamp voltage

ICL

= 1mA

IN

IIN= -1mA

5.5

-0.7

I

CS_DIS low level voltage 0.9 V

Low level CS_DIS current V

= 0.9V 1 µA

CSD

CS_DIS high level voltage 2.1 V

High level CS_DIS current V

= 2.1V 10 µA

CSD

CS_DIS hysteresis voltage 0.25 V

CS_DIS clamp voltage

I

CSD

I

CSD

= 1mA

= -1mA

5.5

-0.7

7V

V

7V

V

Doc ID 13218 Rev 6 9/31

Electrical specifications VN5010AK-E

Table 9. Protections and diagnostics

(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

I

T

T

T

HYST

V

DEMAG

V

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related

Table 10. Current sense (8V<VCC<16V)

Short circuit current

limH

Short circuit current during

limL

thermal cycling

Shutdown temperature 150 175 200 °C

TSD

Reset temperature TRS+1 TRS+5 °C

T

R

Thermal reset of STATUS 135 °C

RS

Thermal hysteresis (T

TSD-TR

Turn-off output voltage clamp I

Output voltage drop

ON

limitation

diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

VCC= 13V
5V<VCC<36V

= 13V;

V

CC

TR<Tj<T

TSD

)7°C

=2A; VIN=0; L=6mH

OUT

I

=0.5A (see Figure 9);

OUT

Tj= -40°C...+150°C

46 65 91

24 A

CC

V

-46

CC

V

-41

25 mV

V

-52

91

CC

A
A

V

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

= 0.25A;

OUT

K

I

0

OUT/ISENSE

V
T

I

K

I

1

OUT/ISENSE

T
I
Tj= 25°C...150°C

I
V
T

dK

1/K1

Current sense ratio

(1)

drift

I

K

I

2

OUT/ISENSE

T
I
T

I
V
TJ= -40 °C to 150 °C

dK

2/K2

Current sense ratio

(1)

drift

I

K

I

3

OUT/ISENSE

Tj= -40°C...150°C
I
T

=0.5V;V

SENSE

= -40°C...150°C

j

= 6A; V

OUT

= -40°C...150°C

j

OUT

OUT

CSD

= -40 °C to 150 °C

J

OUT

=-40°C...150°C

j

OUT

=25°C...150°C

j

OUT

CSD

OUT

OUT

= 25°C...150°C

j

= 6A; V

= 6A; V

= 0V;

= 10A; V

= 10A; V

= 10A; V

=0V;

= 25A; V

= 25A; V

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

=0V;

CSD

=0.5V; V

=0.5V; V

= 0.5V;

=4V; V

=4V; V

= 4V;

=4V; V

=4V; V

CSD

CSD

CSD

CSD

CSD

CSD

=0V;

=0V;

=0V;

=0V;

=0V;

=0V;

2770 5490 8220

3610

4580

5630

3930

4580

5230

-8 +8 %

4000

4570

5220

4180

4570

4960

-5 +5 %

4480

4660

4980

4500

4660

4820

10/31 Doc ID 13218 Rev 6

VN5010AK-E Electrical specifications

Table 10. Current sense (8V<VCC<16V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

dK3/K

3

I

SENSE0

I

OL

V

SENSE

V

SENSEH

I

SENSEH

t

DSENSE1H

t

DSENSE1L

t

DSENSE2H

Current sense ratio

(1)

drift

Analog sense
leakage current

Openload on-state
current detection
threshold

Max analog sense
output voltage

Analog sense output
voltage in over
temperature condition

Analog sense output
current in over
temperature condition

Delay response time
from falling edge of
CS_DIS pin

Delay response time
from rising edge of
CS_DIS pin

Delay response time
from rising edge of
INPUT pin

= 25A; V

I

OUT

=0V;

V

CSD

= -40 °C to 150 °C

T

J

I

= 0A; V

OUT

= 5V; VIN=0V; Tj= -40°C...150°C

V

CSD

V

= 0V; VIN=5V; Tj= -40°C...150°C

CSD

I

= 2A; V

OUT

V

=5V; VIN=5V; Tj= -40°C...150°C

CSD

VIN = 5V, I

I

OUT

V

CC

SENSE

=15A; V

= 13V; R

VCC= 13V; V

V
I

<4V, 1.5A<Iout<25A

SENSE

= 90% of I

SENSE

= 4V;

SENSE

=0V;

SENSE

=0V;

SENSE

= 5 µA 10 45 mA

=0V; 5 V

CSD

= 3.9KΩ 9V

SENSE

= 5V 8 mA

SENSE

SENSE max

(see Figure 4)

V
I

<4V, 1.5A<Iout<25A

SENSE

= 10% of I

SENSE

SENSE max

(see Figure 4)

V
I

<4V, 1.5A<Iout<25A

SENSE

= 90% of I

SENSE

SENSE max

(see Figure 4)

-3 +3 %

0
0

0

1

µA

2

µA

1

µA

50 100 µs

520µs

270 500 µs

Delay response time
between rising edge

Δ

t

DSENSE2H

of output current and
rising edge of current
sense

Delay response time

t

DSENSE2L

from falling edge of
INPUT pin

1. Parameter guaranteed by design; it is not tested.

V
I

SENSE

I

OUT

I

OUTMAX

V
I

SENSE

(see Figure 4)

<4V,

SENSE

= 90% of I

=90% of I

OUTMAX

=15A (see Figure 5)

<4V, 1.5A<Iout<25A

SENSE

=10% of I

SENSEMAX,

SENSE max

µ

310

100 250 µs

s

Doc ID 13218 Rev 6 11/31

Electrical specifications VN5010AK-E

Figure 4. Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

t

DSENSE2H

t

DSENSE1L

t

DSENSE1H

t

DSENSE2L

Figure 5. Delay response time between rising edge of output current and rising

edge of Current Sense (CS enabled)

V

IN

Δ

t

DSENSE2H

t

I

OUT

90% I

OUTMAX

I

OUTMAX

t

I

SENSE

12/31 Doc ID 13218 Rev 6

90% I

I

SENSEMAX

SENSEMAX

t

VN5010AK-E Electrical specifications

Figure 6. I

I

OUT/ISENSE

6000

5500

5000

max Tj= 25°C to 150°C

4500

min Tj= 25°C to 150°C

4000

3500

3000

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

OUT/ISENSE

max Tj = -40°C to 150°C

min Tj= -40°C to 150°C

vs I

(see Table 1 0 for details)

OUT

typical value

I

(A)

OUT

Figure 7. Maximum current sense ratio drift vs load current

dk/k(%)

15

10

5

0

-5

-10

-15

510152025

Note: Parameter guaranteed by design; it is not tested.

I

OUT

(A)

Doc ID 13218 Rev 6 13/31

Electrical specifications VN5010AK-E

Table 11. Truth table

Conditions Input Output Sense (V

Normal operation

CSD

L
H

L

H

0

Nominal

=0V)

(1)

Overtemperature

Undervoltage

Short circuit to GND
(Rsc ≤ 10 mΩ)

Short circuit to V

CC

L
H

L
H

L
H
H

L
H

L
L

V

SENSEH

L
L

L
L
L

0 if T

V

SENSEH

H
H

< Nominal

Negative output voltage clamp L L 0

1. If the V
and external circuit.

is high, the SENSE output is at a high impedance, its potential depends on leakage currents

CSD

Figure 8. Switching characteristics

V

OUT

dV

OUT

/dt

(on)

t

Won

80%

t

r

10%

t

Woff

90%

t

f

dV

OUT

/dt

(off)

t

0

0
0

0

< T

j

TSD

if Tj > T

0

TSD

INPUT

t

d(on)

14/31 Doc ID 13218 Rev 6

t

d(off)

t

VN5010AK-E Electrical specifications

Figure 9. Output voltage drop limitation

Vcc-Vout

Tj=150oC

Von

Von/Ron(T)

Table 12. Electrical transient requirements (part 1/3)

ISO 7637-2:

Test levels

2004(E)

Test pulse

III IV

1 -75V -100V

2a +37V +50V

(1)

Number of

pulses or

test times

5000

pulses

5000

pulses

Tj=25oC

Tj=-40oC

Iout

Burst cycle/pulse

repetition time

0.5 s 5 s 2 ms, 10 Ω

0.2 s 5 s 50 µs, 2 Ω

3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω

3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω

Delays and
impedance

4-6V-7V1 pulse

5b

(2)

+65V +87V 1 pulse 400 ms, 2 Ω

100 ms,

0.01Ω

Table 13. Electrical transient requirements (part 2/3)

ISO 7637-2:

Test level results

2004(E)

Test pulse

III IV

1C C

2a C C

3a C C

3b C C

4C C

(2)

5b

1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

CC

(1)

Doc ID 13218 Rev 6 15/31

Electrical specifications VN5010AK-E

Table 14. Electrical transient requirements (part 3/3)

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

E

One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.

16/31 Doc ID 13218 Rev 6

VN5010AK-E Electrical specifications

Figure 10. Waveforms

NORMAL OPERATION

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

UNDERVOLTAGE

V

V

CC

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

V

USD

USDhyst

INPUT

CS_DIS

LOAD VOLTAGE

LOAD CURRENT

SENSE CURRENT

T

j

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

T

R

T

TSD

T

RS

current

limitation

<Nominal

power
limitation

SHORT TO V

CC

<Nominal

OVERLOAD OPERATION

thermal cycling

SHORTED LOAD NORMAL LOAD

I

LIMH

I

LIML

V

SENSEH

Doc ID 13218 Rev 6 17/31

Electrical specifications VN5010AK-E

2.3 Electrical characteristics curves

Figure 11. Off-state output current Figure 12. High level input current

Iloff (uA)

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Off state

Vcc=13V

Vin=Vout=0V

Tc ( °C )

Figure 13. Input clamp voltage Figure 14. Input low level

Vicl (V)

7

6.8

6.6

6.4

6.2

5.8

5.6

5.4

5.2

Iin=1mA

6

5

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Iih (uA)

5

4.5

4

3.5

3

2.5

2

1.5

0.5

0

Vin=2.1V

1

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Vil (V)

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Figure 15. Input high level Figure 16. Input hysteresis voltage

Vih (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

18/31 Doc ID 13218 Rev 6

Vihyst (V)

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

VN5010AK-E Electrical specifications

Figure 17. On-state resistance vs T

case

Ron (mOhm)

50

45

40

35

30

25

20

15

10

5

0

Iout=6A

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Figure 18. On-state resistance vs V

Ron (mOhm)

20

18

16

14

12

10

8

6

4

2

0

0 5 10 15 20 25 30 35 40

Vcc (V)

Tc=150°C

Tc=125°C

Figure 19. Undervoltage shutdown Figure 20. Turn-on voltage slope

Vusd (V)

16

14

12

10

8

6

4

2

0

-50 -25 0 25 50 75 100 125 1 50 175

Tc ( °C )

dVout/dt(on) (V/ms)

1000

900

800

700

600

500

400

300

200

100

0

Vcc=13V

RI=2.6Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

CC

Tc=25°C

Tc= -40 °C

Figure 21. I

LIMH

vs T

case

Ilimh (A)

80

75

70

65

60

55

50

45

40

Vcc=13V

-50 -25 0 25 50 75 100 125 1 50 175

Tc ( °C )

Figure 22. Turn-off voltage slope

dVout/dt(off) (V/ms)

1000

900

800

700

600

500

400

300

200

100

0

Doc ID 13218 Rev 6 19/31

Vcc=13V

RI=2.6Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Electrical specifications VN5010AK-E

Figure 23. CS_DIS high level voltage Figure 24. CS_DIS clamp voltage

Vcsdh (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Vcsdcl (V)

8

7.5

Icsd=1mA

7

6.5

6

5.5

5

4.5

4

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

Figure 25. CS_DIS low level voltage

Vcsdl (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75 100 125 150 175

Tc ( °C )

20/31 Doc ID 13218 Rev 6

VN5010AK-E Application information

3 Application information

Figure 26. Application schematic

+5V

V

CC

R

mC

prot

R

prot

CS_DIS

IINPUT

OUTPUT

D

ld

R

prot

C

ext

CURRENT SENSE

R

SENSE

V

GND

GND

R

GND

D

GND

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (R

This can be used with any type of load.

The following is an indication on how to dimension the R

1. R

2. R

where -I
maximum rating section of the device datasheet.

Power Dissipation in R

P

= (-VCC)2/ R

D

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.

≤ 600 mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

S(on)max

GND

GND

).

)

(when VCC<0: during reverse battery situations) is:

GND

GND

only)

resistor.

GND

S(on)max

becomes the sum of the

Please note that if the microprocessor ground is not shared by the device ground then the
R

will produce a shift (I

GND

S(on)max

* R

) in the input thresholds and the status output

GND

values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R

GND

.

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).

Doc ID 13218 Rev 6 21/31

Application information VN5010AK-E

3.1.2 Solution 2: diode (D

A resistor (R

=1 kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600 mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V

max DC rating. The same applies if the device is subject to transients on the VCC line

CC

that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 Microcontroller I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the microcontroller I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.

if the device drives an

GND

prot

) in line to

-V

CCpeak/Ilatchup

≤ R

prot

≤ (V

OHµC-VIH-VGND

) / I

IHmax

Calculation example:

For V

5kΩ ≤ R

Recommended values: R

= - 100 V and I

CCpeak

≤ 180 kΩ

prot

latchup

=10 kΩ, C

prot

≥ 20 mA; V

=10 nF.

EXT

OHµC

≥ 4.5 V

22/31 Doc ID 13218 Rev 6

VN5010AK-E Application information

3.4 Maximum demagnetization energy (VCC=13.5V)

Figure 27. Maximum turn-off current versus load inductance

100

A

B

C

10

I (A)

1

0,1 1 10 100L (mH)

A: T

B: T

C: T

VIN, I

= 150°C single pulse

jstart

= 100°C repetitive pulse

jstart

= 125°C repetitive pulse

jstart

L

Note: Values are generated with R

In case of repetitive pulses, T
must not exceed the temperature specified above for curves B and C.

Demagnetization

=0 Ω.

L

(at beginning of each demagnetization) of every pulse

jstart

Demagnetization

Demagnetization

t

Doc ID 13218 Rev 6 23/31

Package and PCB thermal data VN5010AK-E

4 Package and PCB thermal data

4.1 PowerSSO-24TM thermal data

Figure 28. PowerSSO-24TM PC board

Note: Layout condition of R

area= 77 mm x 86 mm, PCB thickness=1.6mm, Cu thickness=70 µm (front and back side),
Copper areas: from minimum pad lay-out to 8 cm

Figure 29. R

RTHj_amb(°C/W)

thj-amb

55

50

45

40

35

30

0246810

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

vs PCB copper area in open box free air condition

PCB Cu heatsink area (cm^2)

24/31 Doc ID 13218 Rev 6

VN5010AK-E Package and PCB thermal data

Figure 30. PowerSSO-24TM thermal impedance junction ambient single pulse

ZTH (° C/ W)

1000

100

10

1

0,1

0,01

1E-04 0,001 0,01 0,1 1 10 100 1000

Time (s)

Equation 1: pulse calculation formula

Z

THδ

where δ = t

Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24

R

TH

P

δ Z

/T

THtp

1 δ–()+⋅=

TM

Footprint

2 cm

8 cm

(a)

2

2

a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Doc ID 13218 Rev 6 25/31

Package and PCB thermal data VN5010AK-E

Table 15. Thermal parameters

Area/island (cm2)Footprint28

R1 (°C/W) 0.08

R2 (°C/W) 0.16

R3 (°C/W) 6

R4 (°C/W) 7.7

R5 (°C/W) 9 9 8

R6 (°C/W) 28 17 10

C1 (W.s/°C) 0.002

C2 (W.s/°C) 0.002

C3 (W.s/°C) 0.025

C4 (W.s/°C) 0.75

C5 (W.s/°C) 1 4 9

C6 (W.s/°C) 2.2 5 17

26/31 Doc ID 13218 Rev 6

VN5010AK-E Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

.

®

is an ST trademark.

Figure 32. PowerSSO-24™ package dimensions

Doc ID 13218 Rev 6 27/31

Package and packing information VN5010AK-E

Table 16. PowerSSO-24™ mechanical data

Millimeters

Symbol

Min. Typ. Max.

A 2.45

A2 2.15 2.35

a1 0 0.1

b 0.33 0.51

c 0.23 0.32

D 10.10 10.50

E7.4 7.6

e0.8

e3 8.8

F2.3

G 0.1

H 10.1 10.5

h 0.4

k0° 8°

L 0.55 0.85

O1.2

Q0.8

S2.9

T3.65

U1.0

N 10deg

X4.1 4.7

Y6.5 7.1

28/31 Doc ID 13218 Rev 6

VN5010AK-E Package and packing information

5.2 Packing information

Figure 33. PowerSSO-24TM tube shipment (no suffix)

Base Q.ty 49
Bulk Q.ty 1225

C

B

A

Figure 34. PowerSSO-24

TM

tape and reel shipment (suffix “TR”)

Tube length (± 0.5) 532
A 3.5
B 13.8
C (± 0.1) 0.6

All dimensions are in mm.

REEL DIMENSIONS

Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 24.4
N (min) 100
T (max) 30.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986

Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (± 0.1) 2

Top

cover

tape

End

500mm min

Empty components pockets
saled with cover tape.

User direction of feed

Start

No componentsNo components Components

500mm min

All dimensions are in mm.

Doc ID 13218 Rev 6 29/31

Revision history VN5010AK-E

6 Revision history

Table 17. Document revision history

Date Revision Changes

24-Jan-2006 1 Initial release.

Reformatted and restructured.

09-Feb-2007 2

13-Dec-2007 3

12-Feb-2008 4

16-Jun-2009 5

16-Jul-2009 6

Added Contents, List of tables and List of figures.
Added Section 3.4: Maximum demagnetization energy (V

=13.5V).

CC

Document reformatted and restructured.

Table 4: Absolute maximum ratings: corrected E

value from 506

MAX

to 609 mJ.
Updated Table 10: Current sense (8V<VCC<16V):
– Changed t

DSENSE2H

– Added dk1/k1, dk2/k2, dk3/k3, Δt

max value from 600 to 500 µs.

, I

DSENSE2H

parameters.

OL

Added Figure 5: Delay response time between rising edge of output

current and rising edge of Current Sense (CS enabled).

Updated Figure 6: IOUT/ISENSE vs IOUT (see Table 10 for details).
Added Figure 7: Maximum current sense ratio drift vs load current.

Table 12: Electrical transient requirements (part 1/3): updated test

level values III and IV for test pulse 5b and notes.

Figure 31: Thermal fitting model of a double channel HSD in
PowerSSO-24

TM

: added note.

Corrected typing error in Table 10: Current sense (8V<VCC<16V):
changed I

test condition from VIN = 0V to VIN = 5V.

OL

Table 16: PowerSSO-24™ mechanical data:

– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F and k rows

Updated Figure 32: PowerSSO-24™ package dimensions.

Table 16: PowerSSO-24™ mechanical data:

– Deleted G1 row
– Added O, Q, S, T and U rows

30/31 Doc ID 13218 Rev 6

VN5010AK-E

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Doc ID 13218 Rev 6 31/31