Datasheet VIPER17 Datasheet (ST)

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Features

VIPER17

Off-line high voltage converters

■ 800 V avalanche rugged power section

■ PWM operation with frequency jittering for low

EMI

■ Operating frequency:

– 60 kHz for L type
– 115 kHz for H type

■ Standby power < 50 mW at 265 Vac

■ Limiting current with adjustable set point

■ Adjustable and accurate over voltage

protection

■ On-board soft-start

■ Safe auto-restart after a fault condition

■ Hysteretic thermal shutdown

Application

■ Adapters for PDA, camcorders, shavers,

cellular phones, videogames

■ Auxiliary power supply for LCD/PDP TV,

monitors, Audio systems, computer, industrial

■ SMPS for set-top boxes, DVD players and

recorders, white goods.

DIP-7DIP-7

Description

The device is an off-line converter with an 800 V
rugged power section, a PWM control, two levels
of over current protection, over voltage and
overload protections, hysteretic thermal
protection, soft-start and safe auto-restart after
any fault condition removal. Burst mode operation
and device very low consumption helps to meet
the standby energy saving regulations.

Advance frequency jittering reduces EMI filter
cost. Brown-out function is embedded into the
high voltage start-up.

Figure 1. Typical topology

Table 1. Device summary

Order codes Package Packaging

VIPER17LN

VIPER17HN

February 2008 Rev 2 1/31

DIP-7 Tube

www.st.com

31

Contents VIPER17

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Operation descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.2 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.3 Power-up and soft-start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.4 Power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.5 Auto restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.6 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.7 Current mode conversion with adjustable current limit set point . . . . . . . 19

7.8 Over Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.9 About CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.10 Feed-back and Over Load Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . 21

7.11 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 24

7.12 Brown-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.13 2nd level over current protection and hiccup mode . . . . . . . . . . . . . . . . . 27

2/31

VIPER17 Contents

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/31

Block diagram VIPER17

1 Block diagram

Figure 2. Block diagram

BR

VDD

Vcc

DRAIN

CONT

15uA

OVP

LOGIC

OVP

0.45V

SOFT

START

.

-

+

6uA

OCP

BLOCK

Vin_OK

FB

2 Typical power

Table 2. Typical power

Inte rnal Supply bus

&

Ref erence Voltages

-

OCP

+

PWM

+

-

+

-

Ref

BURST-MODE

LOGIC

2nd OCP

LOGIC

BURST

SUPPLY

& UVLO

UVLO

LEB

BURST

OSCILLATOR

TUR N -ON

LOGIC

OVP

OTPOLP

HV_ON

S

R1

Istart-up

THE RMA L

SHUTDOWN

OTP

Q

R2

Rsense

GND

230 V

Part number

Adapter

(1)

AC

Open frame

(2)

Adapter

VIPER17 9 W 12 W 5 W 7 W

1. Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient.

2. Maximum practical continuous power in an open frame design at 50

°C ambient, with adequate heat sinking.

4/31

85-265 V

(1)

AC

Open frame

(2)

VIPER17 Pin settings

3 Pin settings

3.1 Connection diagram

Figure 3. Connection diagram (top view)

3.2 Pin description

Table 3. Pin description

N. Name Function

1 GND This pin represents the device ground and the source of the power section.

2VDD

3CONT

4FB

Supply voltage of the control section. This pin also provides the charging
current of the external capacitor during start-up time.

Control pin. The following functions can be selected:

1. current limit set point adjustment. The internal set default value of the cycle­by-cycle current limit can be reduced by connecting to ground an external
resistor.

2. output voltage monitoring. A voltage exceeding 3V shuts the IC down
reducing the device consumption. This function is strobed and digitally filtered
for high noise immunity.

Control input for duty cycle control. Internal current generator provides bias
current for loop regulation. A voltage below 0.5 V activates the burst-mode
operation. A level close to 3.3 V means that we are approaching the cycle-by­cycle over-current set point.

GND

VDD

CONT

FB

DRAIN

DRAIN

BR

5BR

7,8 DRAIN

Brownout protection input with hysteresis. A voltage below 0.45 V shuts down
(not latch) the device and lowers the power consumption. Device operation
restarts as the voltage exceeds 0.45 V plus hysteresis voltage. It can be
connected to ground when not used.

High voltage drain pin. The built-in high voltage switched start-up bias current is
drawn from this pin too.

5/31

Electrical data VIPER17

4 Electrical data

4.1 Maximum ratings

Table 4. Absolute maximum ratings

Symbol Pin Parameter Value Unit

V

DRAIN

E

I

AR

I

DRAIN

V

CONT

V

V

V

P

TOT

T

T

STG

AV

FB

BR

DD

J

7, 8 Drain-to-source (ground) voltage 800 V

7, 8 Repetitive avalanche energy (limited by TJ = 150 °C) 2 mJ

7, 8 Repetitive avalanche current (limited by TJ = 150 °C ) 0.6 A

7, 8 Pulse drain current 0.7 A

3 Control input pin voltage (with I

4 Feedback voltage -0.3 to 5.5 V

5 Brown-out input pin voltage 2 V

2 Supply voltage (IDD = 25 mA) Self limited V

4.2 Thermal data

Table 5. Thermal data

Symbol Parameter Max value Unit

R

R

Thermal resistance junction pin 40 °C/W

thJP

Thermal resistance junction ambient

thJA

= 1 mA) Self limited V

CONT

Power dissipation at TA < 50 °C 1 W

Operating junction temperature range -40 to 150 °C

Storage temperature -55 to 150 °C

90 °C/W

(1)

80

°C/W

1. When mounted on a standard single side FR4 board whit 200 mm2 (0.31 sq in) Of Cu (35 m thick)

6/31

VIPER17 Electrical data

4.3 Electrical characteristics

(TJ = -25 to 125 °C, VDD = 14 V; unless otherwise specified)

Table 6. Power section

Symbol Parameter Test condition Min Typ Max Unit

I

= 1 mA, VFB = GND

V

BVDSS

I

OFF

R

DS(on)

C

OSS

Table 7. Supply section

Break-down voltage

OFF state drain current

Drain-source on state
resistance

Effective (energy related)
output capacitance

Symbol Parameter Test condition Min Typ Max Unit

DRAIN

TJ = 25 °C

V

V

I

= max rating,

DRAIN

= GND

FB

= 0.2 A, VFB = 3 V,

DRAIN

VBR = GND, TJ = 25 °C

I

= 0.2 A, VFB = 3 V ,

DRAIN

VBR = GND, TJ = 125 °C

V

= 0 to 640 V 10 pF

DRAIN

800 V

60 µA

20 24 Ω

40 48 Ω

Volt ag e

V

DRAIN

I

DD_CH

V

DD

V

DDclamp

V

DDon

V

DDoff

V

DD(RESTART)

Current

I

DD0

I

DD1

I

DD_FAULT

I

DD_OFF

_START

Drain-source start voltage 60 80 100 V

Start up charging current

V

VBR = GND, VFB = GND,
V

V

V

= 120 V,

DRAIN

= 4 V

DD

= 120 V ,

DRAIN

= GND, VFB = GND,

BR

-2 -3 -4 mA

-0.4 -0.6 -0.8 mA

VDD = 4 V after fault.

Operating voltage range After turn-on 8.5 23.5 V

VDD clamp voltage IDD = 20 mA 23.5 V

VDD start up threshold

VDD under voltage
shutdown threshold

VDD restart voltage
threshold

Operating supply current,
not switching

Operating supply current,
switching

Operating supply current,
with protection tripping

Operating supply current
with VDD < V

DD_OFF

V

V

V

= 120 V,

DRAIN

= GND, VFB = GND

BR

= 120 V,

DRAIN

VBR = GND, VFB = GND

VFB = GND, FSW = 0 k H z ,
VBR = GND, VDD = 10 V

V

DRAIN

= 120 V,

FSW = 60 kHz

V

DRAIN

= 120 V,

FSW = 115 kHz

VDD = 7 V 270 uA

13 14 15 V

7.588.5V

44.55 V

0.9 mA

1.8 mA

2mA

400 uA

7/31

Electrical data VIPER17

Table 8. Controller section

(T

= -25 to 125 °C, V

J

Symbol Parameter Test condition Min Typ Max Unit

Feedback pin

= 14 V; unless otherwise specified)

DD

V

FB_olp

V

FB_lin

V

FB_bm

V

FB_bm_hys

Over load shut down
threshold

Linear dynamics upper limit 3.2 3.3 3.4 V

Burst mode threshold Voltage falling 0.5 V

Burst mode hysteresis Voltage rising 50 mV

4.7 4.8 5.2 V

VFB = 0.3 V -150 -200 -280 uA

I

R

FB(DYN)

H

FB

FB

Feedback sourced current

Dynamic resistance V

∆VFB / ∆I

D

3.3 V < V

FB

< 4.8 V -3 uA

FB

< 3.3 V 14 19 kΩ

49V/A

CONT pin

VCONT_l Low level clamp voltage I

= -100 uA 0.5 V

CONT

Current limitation

VFB = 4 V,

I

Dlim

Max drain current limitation

I

CONT

= -10 µA

0.38 0.4 0.42 A

TJ = 25 °C

t

SS

T

ON_MIN

Soft-start time 8.5 ms

Minimum turn ON time 400 ns

td Propagation delay 150 ns

t

LEB

I

D_BM

Leading edge blanking 300 ns

Peak drain current during
burst mode

Oscillator section

VIPER17L VDD = operating

F

OSC

VIPER17H 103 115 127 kHz

FD Modulation depth

FM Modulation frequency 250 Hz

D

MAX

Maximum duty cycle 70 80 %

8/31

V

= 0.6 V 90 mA

FB

54 60 66 kHz
voltage range,
VFB = 1 V

VIPER17L ±4 kHz

VIPER17H ±8 kHz

VIPER17 Electrical data

Table 8. Controller section (continued)

(T

= -25 to 125 °C, V

J

Symbol Parameter Test condition Min Typ Max Unit

= 14 V; unless otherwise specified)

DD

Over current protection ( 2

I

DMAX

Second over current
threshold

Over voltage protection

V

OVP

T

STROBE

Over voltage protection
threshold

Over voltage protection
strobe time

Brown out protection

V

BRth

V

BR Hyst

I

BR Hyst

V

V

BR

DIS

Brown out threshold

Voltage hysteresis above
V

BRth

Current hysteresis 7 10 uA

Operating range 0.15 2 V

Brown out disable voltage 50 150 mV

Thermal shutdown

T

T

SD

HYST

Thermal shutdown
temperature

Thermal shutdown
hysteresis

nd

OCP )

0.6 A

2.7 3 3.3 V

2.2 us

0.41 0.45 0.49 V

50 mV

Voltage falling

150 170 °C

30 °C

9/31

Electrical data VIPER17

Figure 4. Minimum turn-on time test circuit

Figure 5. Brown out threshold test circuits

Figure 6. OVP threshold test circuits

10/31

(The OVP protection is triggered
after four consecutive oscillator cycles)

VIPER17 Typical electrical characteristics

5 Typical electrical characteristics

Figure 7. Current limit vs TJ Figure 8. Switching frequency vs T

J

Figure 9. Drain start voltage vs T

Figure 11. Brown out threshold vs T

J

J

Figure 10. HFB vs T

J

Figure 12. Brown out hysteresis vs T

J

11/31

Typical electrical characteristics VIPER17

Figure 13. Brown out hysteresis current

vs T

J

Figure 14. Operating supply current

(no switching) vs T

J

Figure 15. Operating supply current

(switching) vs T

J

Figure 17. Power MOSFET on-resistance

vs T

J

Figure 16. current limit vs R

LIM

Figure 18. Power MOSFET break down

voltage vs T

J

12/31

VIPER17 Typical electrical characteristics

Figure 19. Thermal shutdown

T

J

TSD

T

HYST

V

DD RESTART

V

V

DD OFF

DD ON

V

DD

V

DS

t

t

t

13/31

Typical circuit VIPER17

6 Typical circuit

Figure 20. Flyback application (basic)

VoutD3

AC IN

AC IN

BR

Vcc

V

C1

DD

BR

C3

CONT

CONTROL

FB

Figure 21. Flyback application

GND

R1

C5

D1

GND

R3

OPTO

R4

C6

U2

D3

Vout

C2

R2

D2

DRAIN

SOURCE

C4 R6

R5

AC IN

AC IN

BR

C1

Rh

Rl

Rovp

Vcc

V

DD

BR

C3

CONT

Rlim

CONTROL

14/31

FB

R1

C2

D1

Daux

D2

R2

DRAIN

GND

SOURCE

C4

C5

OPTO

GND

R3

R5

C6

R4

U2

R6

VIPER17 Operation descriptions

7 Operation descriptions

VIPER17 is a high-performance low-voltage PWM controller chip with an 800 V, avalanche
rugged Power section.

The controller includes: the oscillator with jittering feature, the start up circuits with soft-start
feature, the PWM logic, the current limit circuit with adjustable set point, the second over
current circuit, the burst mode management, the brown-out circuit, the UVLO circuit, the
auto-restart circuit and the thermal protection circuit.

The current limit set-point is set by the CONT pin. The burst mode operation guaranties high
performance in the stand-by mode and helps in the energy saving norm accomplishment.

All the fault protections are built in Auto Restart Mode with very low repetition rate to prevent
IC's over heating.

7.1 Power section and gate driver

The Power section is implemented with an avalanche ruggedness N-channel MOSFET,
which guarantees safe operation within the specified energy rating as well as high dv/dt
capability. The Power section has a BV
at 25 °C.

of 800 V min. and a typical R

DSS

DS(on)

of 20 Ω

The integrated SenseFET structure allows a virtually loss-less current sensing.

The gate driver is designed to supply a controlled gate current during both turn-on and turn­off in order to minimize common mode EMI. Under UVLO conditions an internal pull-down
circuit holds the gate low in order to ensure that the Power section cannot be turned on
accidentally.

7.2 High voltage startup generator

The HV current generator is supplied through the DRAIN pin and it is enabled only if the
input bulk capacitor voltage is higher than V
the HV current generator is ON, the I
capacitor on the V
is reduced to 0.6 mA, typ. in order to have a slow duty cycle during the restart phase.

pin. In case of Auto Restart mode after a fault event, the I

DD

DD_ch

DRAIN_START

current (3 mA typical value) is delivered to the

Threshold, 80 VDC typically. When

current

DD_ch

15/31

Operation descriptions VIPER17

7.3 Power-up and soft-start up

If the input voltage rises up till the device start level (V
to grow due to the I
voltage start up circuit. If the V

current (see Table6 on page7) coming from the internal high

DD_ch

voltage reaches V

DD

DRAIN_START

threshold (~14 V) the power

DDon

), the VDD voltage begins

MOSFET starts switching and the HV current generator is turned OFF. See Figure 23 on

page 17.

The IC is powered by the energy stored in the capacitor on the VDD Pin, C

, until when

VDD

the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode)
develops a voltage high enough to sustain the operation.

C

capacitor must be sized enough to avoid fast discharge and keep the needed voltage

VDD

value higher than V

threshold. In fact, a too low capacitance value could terminate the

DDoff

switching operation before the controller receives any energy from the auxiliary winding.

The following formula can be used for the V

capacitor calculation:

DD

Equation 1

I

×

DDchtSSaux

VDD

----------------------------------------=

V

–

DDonVDDoff

The t

C

is the time needed for the steady state of the auxiliary voltage. This time is

SSaux

estimated by applicator according to the output stage configurations (transformer, output
capacitances, etc).

During the converter start up time, the drain current limitation is progressively increased to
the maximum value. In this way the stress on the secondary diode is considerably reduced.
It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the
feature is implemented for every attempt of start up converter or after a fault.

Figure 22. Start up I

I

DD

2 mA

1 mA

I

DD_FAULT

I

DD_OFF

I

DS_CH_FAULT

-1 mA

-2 mA

-3 mA

-4 mA

I

I

DS_CH

DD0

V

DD

DDrestart

current

V

DDoff

16/31

V

= 120V

DS

= 0 kHz

F

SW

AFTER FAULT

V

DDon

VDD

VIPER17 Operation descriptions

V

V

V

Figure 23. Timing diagram: normal power-up and power-down sequences

Vin

Vin

Start

Start

V

V

V

DD

V

Vcc

Vcc

V

DD

Vcc

Vcc

V

DD

Vcc

Vcc

DRAIN

I

DD_CH

I

I

charge

charge

3 mA

3 mA

cc

cc

DD

ON

ON

OFF

OFF

restart

restart

Power

Power

Normal

-

-

on

on

Normal

operation

operation

regulation is lost here

regulation is lost here

Power - off

Power - off

t

t

t

t

t

t

t

t

t

t

t

t

Figure 24. Soft-start: timing diagram

I

DRAIN

t

ss

IDLIM

V

FB

V

FB OL P

V

FB_lin

t

t

17/31

Operation descriptions VIPER17

7.4 Power down operation

At converter power down, the system loses regulation as soon as the input voltage is so low
that the peak current limitation is reached. The V
the V
to the IC interrupted and consequently the V
Later, if the V

threshold (8 V typical) the power MOSFET is switched OFF, the energy transfers

DDoff

is lower than V

IN

DRAIN_START

DD

(80 V typical), the start up sequence is inhibited

voltage drops and when it falls below

DD

voltages decreases, Figure 23 on page 17.

and the power down completed. This feature is useful to prevent converter’s restart attempts
and ensures monotonic output voltage decay during the system power down.

7.5 Auto restart operation

If after a converter power down, the VIN is higher than V
is not inhibited and will be activated only when the V

DRAIN_START,

voltage drops down the V

DD

threshold (4.5 V typical). This means that the HV start up current generator restarts the V
capacitor charging only when the V

voltage drops below V

DD

DDrestart

the start up sequence

DDrestart

DD

. The scenario above
described is for instance a power down because of a fault condition. After a fault condition,
the charging current is 0.6 mA (typ.) instead of the 3 mA (typ.) of a normal start up converter
phase. This feature together with the low V

DDrestart

threshold (4.5 V) ensures that, after a
fault, the restart attempts of the IC has a very long repetition rate and the converter works
safely with extremely low power throughput. The Figure 25 shows the IC behavioral after a
short circuit event.

Figure 25. Timing diagram: behavior after short circuit

V

V

DD

DD

V

V

ON

ON

DD

DD

V

OFF

V

OFF

DD

DD

V

V

DDrest

DDrest

VDS

VDS

IDD_CH

IDD_CH

0.6 mA

0.6 mA

Short circuit occurs here

Short circuit occurs here

Trep

Trep

< 0.03Trep

< 0.03Trep

t

t

t

t
t

t

FB Pin

FB Pin

4.8 V

4.8 V

3.3 V

3.3 V

7.6 Oscillator

The switching frequency is internally fixed to 60 kHz or 115 kHz. In both case the switching
frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz
(115 kHz version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action
distributes the energy of each harmonic of the switching frequency over a number of side­band harmonics having the same energy on the whole but smaller amplitudes.

18/31

t

t

t

t

VIPER17 Operation descriptions

7.7 Current mode conversion with adjustable current limit set
point

The device is a current mode converter: the drain current is sensed and converted in voltage
that is applied to the non inverting pin of the PWM comparator. This voltage is compared
with the one on the feedback pin through a voltage divider on cycle by cycle basis.

The VIPER17 has a default current limit value, I
the electrical specification, by the R

resistor connected to the CONT see Figure 8 on

LIM

page 11.

The CONT pin has a minimum current sunk needed to activate the I
R

or with high R

LIM

(i.e. 100 KΩ) the current limit is fixed to the default value (see I

LIM

Table 8 on page 8).

7.8 Over Voltage Protection (OVP)

The device can monitor the converter output voltage. This operation is done by CONT pin
during power MOSFET OFF-time, when the voltage generated by the auxiliary winding
tracks converter's output voltage, through turn ratio See Figure 26.

In order to perform the output voltage monitor, the CONT pin has to be connected to the aux
winding through a resistor divider made up by R
(see Figure 21 and Figure 27). If the voltage applied to the CONT pin exceeds the internal 3
V reference for four consecutive times the controller recognizes an over voltage condition.
This special feature uses an internal counter; that is to reduce sensitivity to noise and
prevent the latch from being erroneously activated. see Figure 26 on page 20. The counter
is reset every time the OVP signal is not triggered in one oscillator cycle.

Referring to the Figure 21, the resistors divider ratio k

, that the designer can adjust according

DLIM

adjustment: without

DLIM

N

AUX

--------------

N

SEC

and R

LIM

OVP

will be given by:

OVP

DLIM

,

Equation 2

Equation 3

k

OVP

V

---------------------------------------------------------------------------------------------------=

N

AUX

--------------

N

V

SEC

k

OVP

19/31

OVP

OUTOVPVDSEC

+()V

R

LIM

----------------------------------=

R

+

LIMROVP

–⋅

DAUX

Operation descriptions VIPER17

U

Where:

● V

● V

● N

● N

● V

● V

● R

Than, fixed R

is the OVP threshold (see Table 8 on page 8)

OVP

OUT OVP

AUX

SEC

DSEC

DAUX

OVP

is the converter output voltage value to activate the OVP set by designer

is the auxiliary winding turns

is the secondary winding turns

is the secondary diode forward voltage

is the Auxiliary diode forward voltage

together R

according to the desired I

LIM,

make the Output Voltage divider

LIM

DLIM

, the R

can be calculating by:

OVP

Equation 4

1k

–

OVP

R

OVP

-----------------------

R

×=

LIM

k

OVP

The resistor values will be such that the current sourced and sunk by the CONT pin be
within the rated capability of the internal clamp.

Figure 26. OVP timing diagram

V

V

DS

DS

VA

X

0

0

CONT
(pin 4)

(pin 4)

3V

3V

0.5 µs

STROBE

STROBE

OVP

OVP

COUNTER

COUNTER

RESET

RESET

COUNTER

COUNTER

STATUS

STATUS

FAULT

FAULT

2 µs

2 µs

0 0 0

0 0 0

NORMAL OPERATION TEMPORARY DISTURBANCE FEEDBACK LOOP FAILURE

NORMAL OPERATION TEMPORARY DISTURBANCE FEEDBACK LOOP FAILURE

0.5 µs

→

→

1

1

0

0

t

t

t

t

t

t

t

t

t

t

→

→

1

1

→

→

2

2

0

0

2

2

→

→

0

0

→

→

1

1

1

1

→

→

2

2

2

2

→

→

3

3

3

3

t

40

40

t

t

t

t

20/31

VIPER17 Operation descriptions

7.9 About CONT pin

Referring to the Figure 27, through the CONT PIN, the below features can be implemented:

1. Current Limit set point

2. Over Voltage Protection on the converter output voltage

The Table9 on page21 referring to the Figure 27, lists the external resistance combinations
needed to activate one or plus of the CONT pin functions.

Figure 27. CONT pin configuration

OCP

Daux

Auxiliary
winding

Rovp

CONT

Rlim

SOFT

START

OVP DETECTION

LOGIC

To OVP Protec tion

Curr. Lim.

BLOCK

From SenseFET

Current Limit C omparator

-

+

To PWM Logic

Table 9. CONT pin configurations

LIM

(1)

1. R

Function / component R

I

reduction See Figure 8 No No

Dlim

OVP ≥ 80 KΩ See Equation 4 Ye s

I

reduction + OVP See Figure 8 See Equation 4 Ye s

Dlim

have to be fixed before RFF and R

LIM

OVP

7.10 Feed-back and Over Load Protection (OLP)

The VIPER17 is a current mode converter: the feedback pin controls the PWM operation,
controls the burst mode and actives the overload protection of the device. Figure 28 on

page 23 and Figure 29 show the internal current mode structure.

With the feedback pin voltage between V
typical values) the drain current is sensed and converted in voltage that is applied to the non
inverting pin of the PWM comparator.

This voltage is compared with the one on the feedback pin through a voltage divider on
cycle by cycle basis. When these two voltages are equal, the PWM logic orders the switch
off of the power MOSFET. The drain current is always limited to I

In case of overload the feedback pin increases in reaction to this event and when it goes
higher than V

the drain current is limited or to the default I

FB_lin

FB_bm

and V

, (respectively 0.5 V and 3.3 V,

FB_lin

DLIM

R

OVP

value.

DLIM

value or the one

D

AUX

21/31

Operation descriptions VIPER17

imposed through a resistor at the CONT pin (using the R

, see Figure 8 on page 11); the

LIM

PWM comparator is disabled.

At the same time an internal current generator starts to charge the feedback capacitor
(C

) and when the feedback voltage reaches the V

FB

off and the start up phase is activated with reduced value of I

threshold, the converter is turned

FB_olp

charge

to 0.6 mA.

During the first start up phase of the converter, after the soft-start up time (typical value is

8.5 ms) the output voltage could force the feedback pin voltage to rise up to the V

FB_olp

threshold that switches off the converter itself.

To avoid this event, the appropriate feedback network has to be selected according to the
output load. More the network feedback fixes the compensation loop stability. The Figure 28

on page 23 and Figure 29 show the two different feedback networks.

The time from the over load detection (VFB = V
V

) can be calculating by CFB value (see Figure 28 on page 23 and Figure 29), using

FB_olp

) to the device shutdown (VFB =

FB_lin

the formula:

Equation 5

V

–

FBolpVFBlin

T

OLP delay–

In the Figure 28, the capacitor connected to FB pin (C

----------------------------------------

C

×=

FB

3µ A

) is used as part of the circuit to

FB

compensate the feedback loop but also as element to delay the OLP shut down owing to the
time needed to charge the capacitor (see equation 5).

After the start up time, 8.5 ms typ value, during which the feedback voltage is fixed at
V

, the output capacitor could not be at its nominal value and the controller interpreter

FB_lin

this situation as an over load condition. In this case, the OLP delay helps to avoid an
incorrect device shut down during the start up.

Owing to the above considerations, the OLP delay time must be long enough to by-pass the
initial output voltage transient and check the over load condition only when the output
voltage is in steady state. The output transient time depends from the value of the output
capacitor and from the load.

When the value of the C

capacitor calculated for the loop stability is too low and cannot

FB

ensure enough OLP delay, an alternative compensation network can be used and it is
showed in Figure 29 on page 24.

Using this alternative compensation network, two poles (f
introduced by the capacitors C

The capacitor C

introduces a pole (f

FB

and C

FB

and the resistor R

FB1

) at higher frequency than fZB and f

PFB

PFB

, f

) and one zero (f

PFB1

.

FB1

. This pole

PFB1

ZFB

) are

is usually used to compensate the high frequency zero due to the ESR (Equivalent Series
Resistor) of the output capacitance of the fly-back converter.

The mathematical expressions of these poles and zero frequency, considering the scheme
in Figure 29 are reported by the equations below:

Equation 6

f

ZFB

=

1

RC2

⋅⋅π⋅

1FB1FB

22/31

VIPER17 Operation descriptions

Equation 7

RR

+

f

PFB

=

()

1FB)DYN(FB

RRC2

⋅⋅⋅π⋅

1FB)DYN(FBFB

Equation 8

1

()

+⋅⋅π⋅

RRC2

)DYN(FB1FB1FB

results much higher than CFB.

FB1

FB1

The R

FB(DYN)

page 10

The C

FB1

The equation

is the dynamic resistance seen by the FB pin and reported on Figure 4 on

.

capacitor fixes the OLP delay and usually C

5 can be still used to calculate the OLP delay time but C

considered instead of C

f

=

1PFB

. Using the alternative compensation network, the designer can

FB

satisfy, in all case, the loop stability and the enough OLP delay time alike.

Figure 28. FB pin configuration

From sense FET

Cfb

PWM

CONTROL

BURST-MODE
REFERENCES

OLP comparator

4.8V

PWM

+

-

BURST-MODE

LOGIC

+

-

To PWM Logic

BURST

To disable logic

has to be

23/31

Operation descriptions VIPER17

Figure 29. FB pin configuration

From sense FET

Rfb1

Cfb1

Cfb

PWM

CONTROL

BURST-MODE

REFERENCES

OLP comparator

4.8V

PWM

+

-

BURST-MODE

LOGIC

+

-

To PWM Logic

BURST

To disable logic

7.11 Burst-mode operation at no load or very light load

When the voltage on feedback pin falls down 50 mV below the burst mode threshold, V

FBbm

power MOSFET is not more allowed to be switched on. It can be switched on again if the
voltage on feedback pin exceeds V

. The voltage on PWM comparator non inverting

FBbm

internal input, connected to feedback pin through a resistive voltage divider, is lower
clamped to a certain value leading to a minimum value, of 90 mA (typ.) for the drain peak
current.

When the load decrease the feedback loop reacts lowering the feedback pin voltage. As the
voltage goes 50mV below V

MOSFET stops switching. After the MOSFET stops, as a

FBbm

result of the feedback reaction to the energy delivery stop, the feedback pin voltage
increases and exceeding V

threshold MOSFET the power device start switching again.

FBbm

Figure 30 shows this behavior called burst mode. Systems alternates period of time where

power MOSFET is switching to period of time where power MOSFET is not switching. The
power delivered to output during switching periods exceeds the load power demands; the
excess of power is balanced from not switching period where no power is processed. The
advantage of burst mode operation is an average switching frequency much lower then the
normal operation working frequency, up to some hundred of hertz, minimizing all frequency
related losses.

,

24/31

VIPER17 Operation descriptions

Figure 30. Burst mode timing diagram, light load management

FB

100

50 mV

50 mV

hyster.

V

I

FBBM

DS

Normal - mode

Normal - mode Normal - mode

Burst-mode

Burst-mode Burst-mode

hyster.

Normal - mode

Normal - mode Normal - mode

t

t

t

t

7.12 Brown-out protection

Brown-out protection is a not-latched shutdown function activated when a condition of mains
under voltage is detected.

The Brown-out comparator is internally referenced to V

,0.45 V typ value, and disables

BRth

the PWM if the voltage applied at the BR pin is below this internal reference. Under this
condition the power MOSFET is turned off. Until the Brown out condition is present, the VDD
voltage continuously oscillates between the V
the timing diagram of

Figure 31 on page 26. A voltage hysteresis is present to improve the

and the UVLO thresholds, as shown in

DDon

noise immunity.

The switching operation is restarted as the voltage on the pin is above the reference plus the
before said voltage hysteresis. See

The Brown-out comparator is provided also with a current hysteresis, I
approach is possible to set the V

Figure 31.

threshold and V

INon

.With this

thresholds separately, by properly

INoff

BRhyst

choosing the resistors of the divider connect to the BR pin.

25/31

Operation descriptions VIPER17

K

K

−

−

Figure 31. Brown-out protection: BR external setting and timing diagram

HV Input bus

HV Input bus

ON

ON

Vin

Vin

OFF

OFF

Vin

Vin

HV Input bus

Rh

Rl

BR

BR

15u

Fixed the V

0.1V

0.45V

and the V

INon

V

Vcc

+

-

-

+

DD

AC_OK D is able

VinOK

levels, with reference to Figure 31, the following relationships

INoff

0.45V

0.45V

VinO

VinO

BR HYS

I

15 µA

15 µA

V

Vcc

Vcc

(pin 3)

(pin 3)

VDS

VDS

Vout

Vout

DD

can be established for the calculation of the resistors R

Equation 9

V

R ×

BRHYST

L

I

BRHYST

+−=

−

−−

VV

VVV

BRHYSTINoffINon

BRINoff

and RL:

H

V

BR

I

BRHYST

t

t

t

t

t

t

t

t

t

t

t

t

t

t

Equation 10

=

R

H

I

BRHYST

For a proper operation of this function, V
minimum mains and V

less than the minimum voltage on the input bulk capacitor at

IN off

minimum mains and maximum load.

The BR pin is a high impedance input connected to high value resistors, thus it is prone to
pick up noise, which might alter the OFF threshold when the converter operates or gives
origin to undesired switch-off of the device during ESD tests.

It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent
any malfunctioning of this kind.

If the Brown-out function is not used the pin has to be connected to GND.

26/31

VVV

BRHYSTINoffINon

IN on

×

must be less than the peak voltage at

R

L

V

R

BRHYST

+

L

I

BRHYST

VIPER17 Operation descriptions

7.13 2nd level over current protection and hiccup mode

The VIPER17 is protected against short circuit of the secondary rectifier, short circuit on the
secondary winding or a hard-saturation of fly-back transformer. Such as anomalous
condition is invoked when the drain current exceed 0.6 A typical.

To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a
“warning state” is entered after the first signal trip. If in the subsequent switching cycle the
signal is not tripped, a temporary disturbance is assumed and the protection logic will be
reset in its idle state; otherwise if the 2
switching cycles a real malfunction is assumed and the power MOSFET is turned OFF.

The shutdown condition is latched as long as the device is supplied. While it is disabled, no
energy is transferred from the auxiliary winding; hence the voltage on the V
decays till the V

under voltage threshold (V

DD

The start up HV current generator is still off, until V
V

. After this condition the VDD capacitor is charged again by 600 mA current, and the

DDrest

converter switching restart if the V
device enters in auto-restart mode. This behavioral, results in a low-frequency intermittent
operation (Hiccup-mode operation), with very low stress on the power circuit. See the timing
diagram of

Figure 32.

Figure 32. Hiccup-mode OCP: timing diagram

nd

OCP threshold is exceeded for two consecutive

), which clears the latch.

DDoff

voltage goes below its restart voltage,

DD

occurs. If the fault condition is not removed the

DDon

DD

capacitor

V

Vcc

V

DD

V

DD

V

DD

Vccrest

Vccrest

IDRAIN

V

DS

DD

OFF

IDm ax

IDm ax

Secondary diode is shorted here

Secondary diode is shorted here

ON

t

t

t

t

t

t

27/31

Package mechanical data VIPER17

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

Table 10. DIP-7 mechanical data

mm

Dim.

Typ Mi n Ma x

A 5,33

A1 0,38

A2 3,30 2,92 4,95

b 0,46 0,36 0,56

b2 1,52 1,14 1,78

c 0,25 0,20 0,36

D 9,27 9,02 10,16

E 7,87 7,62 8,26

E1 6,35 6,10 7,11

e 2,54

eA 7,62

eB 10,92

L 3,30 2,92 3,81

(6)(8)

M

2,508

N 0,50 0,40 0,60

N1 0,60

(7)(8)

O

1- The leads size is comprehensive of the thickness of the leads finishing material.

2- Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side).

3- Package outline exclusive of metal burrs dimensions.

4- Datum plane "H" coincident with the bottom of lead, where lead exits body.

5- Ref. POA MOTHER doc. 0037880

6- Creepage distance >800 V

7- Creepage distance 250 V

8- Creepage distance as shown in the 664-1 CEI / IEC standard.

0,548

28/31

VIPER17 Package mechanical data

Figure 33. Package dimensions

29/31

Revision history VIPER17

9 Revision history

Table 11. Document revision history

Date Revision Changes

14-Feb-2008 1 Initial release

19-Feb-2008 2 Updated: Figure 1 on page 1, Figure 3 on page 5

30/31

VIPER17

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31/31