Page 1
V-Data VDS6632A4A
A
1
234
5
6
7
8
9
8
6
8
5
8
4
8
3
8
2
8
1
8
0
797
8
6
6
6
5
6
4
6
3
6
2
6
1
6
0
5
9
5
8
1
0
1
1
1
2
1
3
141
5
1
6
1
7
1
8
1
9
2
0
7
7
7
6
7
5
7
4
73727
1
7
0
6
9
6
8
6
7
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
414
2
4
3
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
464
5
4
4
Synchronous DRAM 512K x 32 Bit x 4 Banks
General Description
The VDS6632A4A are four-bank Synchronous
DRAMs organized as 524,288 words x 32 bits x 4
banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Ordering Information.
Part No. Frequency Interface Package
VDS6632A4A-5 200Mhz LVTTL 400mil 86pin TSOPII
Features
•JEDEC standard LVTTL 3.3V power supply
•MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,3,8,& full page)
-Burst Type (sequential & Interleave)
•4 banks operation
ll inputs are sampled at the positive edge of
•
the system clock
•Burst Read single write operation
•Auto & Self refresh
•4096 refresh cycle
•DQM for masking
•Package:86-pins 400 mil TSOP-Type II
VDS6632A4A-5.5 183Mhz LVTTL 400mil 86pin TSOPII
VDS6632A4A-6 166Mhz LVTTL 400mil 86pin TSOPII
Pin Assignment
DD
V
DQ0
DDQ
V
DQ1
DQ2
SSQ
V
DQ3
DQ4
V
DDQ
DQ5
DQ6
SSQ
V
DQ7
NC
V
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
DD
V
NC
DQ16
SSQ
V
DQ17
DQ18
V
DDQ
DQ19
DQ20
SSQ
V
DQ21
DQ22
DDQ
V
DQ23
V
DD
DD
SS
V
DQ15
SSQ
V
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
DDQ
V
DQ8
NC
SS
V
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
SS
V
NC
DQ31
DDQ
V
DQ30
DQ29
V
SSQ
DQ28
DQ27
V
DDQ
DQ26
DQ25
SSQ
V
DQ24
SS
V
86-pin plastic TSOP II 400mil
Rev 1.0 April, 2001
1
Page 2
V-Data VDS6632A4A
Pin Description
PIN NAME FUNCTION
CLK System Clock Active on the positive edge to sample all inputs.
CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS Chip Select Disables or Enables device operation by masking or enabling all input
except CLK, CKE and DQM0 ~ DQM3
A0~A11 Address Row / Column address are multiplexed on the same pins.
Row address : RA0~RA10
Column address : CA0~CA7
BA0~BA1 Banks Select Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ31 Data Data inputs / outputs are multiplexed on the same pins.
DQM0~3 Data Mask Makes data output Hi-Z,
/RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low
/CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low
/WE Write Enable Enables write operation and row recharge.
VDD/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
NC No Connection This pin is recommended to be left No Connection on the device.
Block Diagram
CLK
CKE
Address
Clock
Generator
Mode
Register
Address
Buffer
&
Refresh
Counter
Decoder
Row
Bank3
Bank2
Bank1
Bank0
/CS
/RAS
/CAS
/WE
Rev 1.0 April, 2001
Decoder
Command
Logic
Control
Column
Address
Buffer
&
Refresh
Counter
Amplifier
ColumnDecoder
DataControlCircuit
Latch
Data
DQM
DQ
2
Page 3
V-Data VDS6632A4A
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, Vout -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150
Power dissipation PD 1 W
Short circuit current IOS 50 mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
℃
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH=-2mA
Output logic low voltage VOL - - 0.4 V IOL=2mA
Input leakage current IIL -5 - 5 uA 3
Output leakage current IOL -5 - 5 uA 4
Note : 1. VIH (max)=4.6V AC for pulse width ≦ 10ns acceptable.
2.V
3.Any input 0V ≦ V
4.Dout is disabled, 0V ≦ V
IL(min)=-1.5V AC for pulse width ≦ 10ns acceptable.
IN ≦ VDD + 0.3V, all other pins are not under test = 0V.
OUT ≦ VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter Symbol Value Unit Note
AC input high / low level voltage VIH / VIL 2.4 / 0.4 V
Input timing measurement reference level voltage Vtrip 1.4 V
Input rise / fall time TR / tF 1 Ns
Output timing measurement reference level Voutfef 1.4 V
Output load capacitance for access time measurement CL 30 pF 2
Note: 1. 3.15V ≦ VDD ≦ 3.6V is applied for VDS6632A4A5.
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,
refer to AC/DC output load circuit.
Rev 1.0 April, 2001
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V-Data VDS6632A4A
A
Capacitance
TA= 25℃, f-=1Mhz, VDD=3.3V
Parameter Pin Symbol Min Max Unit
CLK Cl1 2.5 4 pF Input capacitance
A0~A11,BA0,BA1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Data input / output capacitance DQM CI/O 4 6.5 pF
Cl2 2.5 5 pF
Output load circuit
3.3 V
1200 ohms
Output
870 ohms50 pF
VOH(DC) = 2.4V,IOH= -2m
VOL(DC) = 0.4V,IOL= 2mA
DC Characteristics I
Parameter Symbol Min Max Unit Note
Input leakage current ILI -1 1 uA 1
Output leakage current ILO -1.5 1.5 uA 2
Output high voltage VOH 2.4 - V IOH = -2mA
Output low voltage VOL - 0.4 V IOL = 2mA
Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V.
2.D
OUT is disabled, VOUT = 0 to 3.6.
Rev 1.0 April, 2001
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V-Data VDS6632A4A
DC Characteristics II
Parameter Symbol Test condition
Speed
Unit Note
-5 -5.5 -6
Operating Current IDD1
Precharge standby
current in power down
mode
Precharge standby
current in Non power
down mode
Active standby current
in power down mode
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
Burst length=1, One bank active
tRC≧tRC(min),I
CKE≦V
CKE≦V
CKE≧V
tCK=min input signals are
changed one time during 2clks. All
other pins ≧VDD-0.2V or ≦
0.2V
CKE≧V
Input signals are stable.
CKE≦V
CKE≦V
CKE≧V
tCK=min input signals are
OL=0mA
IL(max), tCK=min
IL(max), tCK=∞
IH(min), /CS≧VIH(min),
IH(min), tCK=∞
IL(max), tCK=min
IL(max), tCK=∞
IH(min), /CS≧VIH(min),
210 200 190 mA 1
2
mA
2
15
mA
12
6
mA
5
Active standby current
in Non power down
mode
Burst mode operating
current
Auto refresh current IDD5
Self refresh current IDD6
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
IDD3N
IDD3NS
IDD4
changed one time during 2clks. All
other pins ≧VDD-0.2V or ≦
0.2V
CKE≧V
Input signals are stable.
t
All banks active
tRRC≧tRRC(min), All banks
active
CKE≦0.2V
IH(min), tCK=∞
CK≧tCK(min),IOL=0 mA
30
mA
20
280 270 260 mA 1
250 240 230 mA 2
1 mA
Rev 1.0 April, 2001
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V-Data VDS6632A4A
AC Characteristics
Parameter Symbol
/CAS Latency = 3 tCK3 5 5.5 6 System clock
Cycle time
Clock high pulse width tCHW 2 - 2.25 - 2.5 - ns 1
Clock low pulse width tCLW 2 - 2.25 - 2.5 - ns 1
clock
/RAS cycle time
/RAS to /CAS delay tRCD 15 - 16.5 - 18 - ns
/RAS active time tRAS 40 100K 38.5 100K 42 100K ns
/RAS precharge time tRP 15 - 16.5 - 18 - ns
/RAS to /RAS bank active delay tRRD 10 - 11 - 12 - ns
/CAS to /CAS delay tCCD 1 - 1 - 1 - CLK
Write command to data – in delay tWTL 0 - 0 - 0 - CLK
/CAS Latency = 2 tCK2 10
/CAS Latency = 3 tAC3 - 4.5 - 5 - 5.5 Access time form
/CAS Latency = 2 tAC2 - 6 - 6 - 6
Operation tRC 55 - 55 - 60 -
Auto Refresh tRRC 55 - 55 - 60 -
-5 -5.5 -6
Min Max Min Max Min Max
1000
10
1000
1000 ns
10
Unit Note
ns 2
ns
Data – in to precharge command tDPL 1 - 1 - 1 - CLK
Data – in active command tDAL 5 - 5 - 5 - CLK
DQM to data – out Hi-Z tDQZ 2 - 2 - 2 - CLK
DQM to data – in mask tDQM 0 - 0 - 0 - CLK
Data – out hold time tOH 1.5 - 2 - 2 - ns
Data – input setup time tDS 1.5 - 1.5 - 1.5 - ns 1
Data – input hold time tDH 1 - 1 - 1 - ns 1
Address setup time tAS 1.5 - 1.5 - 1.5 - ns 1
Address hold time tAH 1 - 1 - 1 - ns 1
CKE setup time tCKS 1.5 - 1.5 - 1.5 - ns 1
CKE hold time tCKH 1 - 1 - 1 - ns 1
Command setup time tCS 1.5 - 1.5 - 1.5 - ns 1
Command hold time tCH 1 - 1 - 1 - ns 1
CLK to data output in low Z-time tOLZ 1 - 1 - 1 - ns
MRS to new command tMRD 2 - 2 - 2 - CLK
Power down exit time tPDE 1 - 1 - 1 - CLK
Self refresh exit time tSRE 1 - 1 - 1 - CLK 3
Refresh time tREF - 64 - 64 - 64 ms
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1.0 April, 2001
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V-Data VDS6632A4A
Command Truth-Table
Command CKEn-1 CKEn /CS /RAS /CAS /WE DQM ADDR A10/AP BA
Mode Register Set H X L L L L X OP code
No Operation H X
Bank Active H X L L H H X RA V
Read L
H X L H L H X CA
Read with Auto Precharge
Write L
H X L H L L X CA
Write with Auto Precharge
Precharge All Bank H X
H X L L H L X X
Precharge select Bank
Burst Stop H X L H H L X X
DQM H X V X
Auto Refresh H H L L L H X X
Entry H L L L L H X
Self Refresh
Exit L H
Entry H L
Precharge
Power down
Exit L H
H X X X
L H H H
H X X X
L H H H
H X X X
L H H H
H X X X
L H H H
X X
V
H
V
H
L V
X
X
X
X
X
Clock Suspend
Entry H L
Exit L H X X
Rev 1.0 April, 2001
H X X X
L V V V
7
X
X
Page 8
V-Data VDS6632A4A
Package Information
Symbol Dimension in mm Dimension in inch
Min Norm Max Min Norm Max
A
A1 0.05 0.10 0.15 0.002 0.004 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.011
b0.17
b1 0.17 0.20 0.23 0.007 0.008 0.009
c0.12
c1 0.10 0.127 0.16 0.004 0.005 0.006
D 22.22 BSC 0.875 BSC
ZD 0.61 REF 0.024 REF
E 11.76 BSC 0.463 BSC
E1 10.16 BSC 0.400 BSC
L 0.40 0.50 0.60 0.016 0.020 0.024
L1 0.80 REF 0.031 REF
e 0.50 BSC 0.020 BSC
R1 0.12
R2 0.12
0
10
2101520101520
3
10 15 20 10 15 20
1.20
0.27 0.007
0.21 0.005
0.25 0.005
80
0.005
0
400mil 86pin TSOP II Package
0.047
0.018
0.008
0.010
8
Rev 1.0 April, 2001
8
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