Datasheet UPD98401AGD-MML Datasheet (NEC)

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Page 1

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD98401A

ATM SAR CHIP

DESCRIPTION

The µPD98401A (NEASCOT-S15TM) is a high-performance SAR chip that segments and reassembles ATM cells. This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor, network hub, or router. The µPD98401A conforms to the ATM Forum Recommendation, and provides the functions of the AAL-5 SAR sublayer and ATM layer.

The µPD98401A is compatible with its predecessor, µPD98401, in terms of hardware and software.

Functions are explained in detail in the following User’s Manual. Be sure to read this manual when designing your system.

PD98401A User’s Manual: S12054E

µµµµ

FEATURES

• Conforms to ATM Forum

• AAL-5 SAR sublayer and ATM layer functions

• Hardware support of AAL-5 processing

• Processing of non-AAL-5 traffic (AAL-3/4 cell, OAM cell, RM cell) by software with raw cell processing function

• Hardware support of comparison/generation of CRC-10 for non-AAL-5 traffic

• Supports up to 32K virtual channels (VC)

• Provided with 16 traffic shapers that carry out transmission scheduling (control of average rate/peak rate) so as to

set different transmission rate for each VC

• Interface and commands for controlling PHY device

• Employs “UTOPIA interface” as cell data interface with PHY device

- Octet-level handshake

- Cell-level handshake

• 32-bit general-purpose bus interface

• High-speed DMAC (supports 1-, 2-, 4-, 8-, 12-, and 16-word burst)

• JTAG boundary scan test function (IEEE1149.1)

• CMOS technology

• +5 V single power source

Remark

In this document, an active low pin is indicated by

_B (_B after a pin name).

×××

Document No. S12100EJ3V0DS00 (3rd edition) Date Published February 1999 N CP(K) Printed in Japan

The information in this document is subject to change without notice.

The mark shows major revised points.

1997©

Page 2

ORDERING INFORMATION

Part Number Package

PD98401AGD-MML 208-pin plastic QFP (fine pitch) (28 × 28 mm)

SYSTEM CONFIGURATION

ATM interface card

PD98402A

Control memory

PD98401A

Bus interface

Reception

PMD

Transmission

ATM network

µµµµ

PD98401A

BLOCK DIAGRAM

System port

DMA controller and host interface

I/O bus

Receive data FIFO

Reception controller

Sequencer

Transmission controller

Transmit data FIFO

(10 cells)

PHY interface reception block

Control memory interface

PHY interface transmission block

PHY device transmission block

Control memory

PHY device reception block

Data Sheet S12100EJ3V0DS00

Page 3

PIN CONFIGURATION

µµµµ

PD98401A

PHY interface

Bus interface

Rx7-Rx0 RCLK RENBL_B RSOC EMPTY_B/RxCLAV Tx7-Tx0 TCLK TENBL_B TSOC FULL_B/TxCLAV

PHRW_B PHOE_B PHCE_B PHINT_B

AD31-AD0 PAR3-PAR0 OE_B

SIZE2-SIZE0 DR/W_B ATTN_B GNT_B RDY_B ABRT_B ERR_B

SR/W_B SEL_B ASEL_B CLK RST_B INTR_B

Master

Slave Power supply

CD31-CD0

CPAR3-CPAR0

CA17-CAD

CWE_B

COE_B

CBE_B3-CBE_B0

INITD

DBVC

DBMD

DBML DBMF

DBMR

JDO

JDI

JCK

JMS

JRST_B

TRF_B

GND

Control memory interface

Bus monitoring

JTAG boundary scan interface

Test pin (fixed to low level)

Data Sheet S12100EJ3V0DS00

Page 4

PIN CONFIGURATION (Top View)

µµµµ

PD98401A

208-pin plastic QFP (fine pitch) (28

VDDDBVC

DBMR

GND

VDDJRST_B

JMS

JDI

JDO

GND

VDDJCK

208

207

206

205

204

203

202

201

200

199

198

197

GND

GND AD31 AD30 AD29 AD28 AD27

GND AD26 AD25 AD24 AD23 AD22

GND

V AD21 AD20 AD19 AD18 AD17

GND AD16 AD15 AD14 AD13

GND

AD12

RST_B

GND

CLK

GND

V AD11 AD10

AD9 AD8 AD7

GND

AD6 AD5 AD4 AD3 AD2 AD1

AD0 PAR3 PAR2

GND GND

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

5354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899

28 mm)

××××

GND

VDDDBMF

196

195

194

DBML

DBMD

193

192

GND

VDDTRF_B

191

190

189

INTID

COE_B

CWE_B

CBE_B0

CBE_B1

VDDGND

188

187

186

185

184

183

182

PD98401AGD-MML

CBE_B2

CBE_B3

CA0

181

180

179

CA1

178

CA2

177

CA3

176

GND

175

VDDCA4

174

173

CA5

172

CA6

171

CA7

170

CA8

169

CA9

168

CA10

GND

167

166

VDDCA11

CA12

165

164

163

CA13

CA14

162

161

100

CA15

CA16

160

159

101

102

CA17

158

157

103

104

156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105

GND GND CPAR0 CPAR1 CPAR2 CPAR3 GND CD0 CD1 CD2 CD3 CD4 CD5 CD6

V GND CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 GND

V CD16 CD17 CD18 CD19 CD20

V GND CD21 CD22 CD23 CD24 CD25 CD26 CD27 GND

V CD28 CD29 CD30 CD31 PHRW_B PHOE_B PHINT_B GND GND

GND

PAR1

PAR0

OE_B

SIZE1

SIZE0

SIZE2

GND_B

ATTN_B

DR/W_B

RDY_B

ABRT_B

SEL_B

ERR_B

SR/W_B

INTR_B

ASEL_B

GND

Rx7

Rx6

Rx5

Rx4

Rx3

GND

Data Sheet S12100EJ3V0DS00

Rx2

Rx1

Rx0

RCLK

TSOC

RSOC

RENBL_B

TENBL_B

FULL_B/TxCLAV

EMPTY_B/RxCLAV

GND

TCLK

Tx7

Tx6

Tx5

Tx4

Tx3

Tx2

Tx1

Tx0

PHCE_B

Page 5

µµµµ

PD98401A

PIN NAMES

ABRT_B : Abort PHCE_B : PHY Chip Enable AD31_AD0 : Address/Data PHINT_B : PHY Interrupt ASEL_B : Slave Address Select PHOE_B : PHY Output Enable ATTN_B : Attention/Burst Frame PHRW_B : PHY Read/Write CA17-CA0 : Control Memory Address RCLK : Receive Clock CBE_B3_CBE_B0 : Local Port Byte Enable RDY_B : Target Ready CD31-CD0 : Control Memory Data RENBL_B : Receive Enable CLK : Clock RSOC : Receive Start Cell COE_B : Control Memory Output Enable RST_B : Reset CPAR3-CPAR0 : Control Memory Parity Rx7-Rx0 : Receive Data Bus CWE_B : Control Memory Write Enable SLE_B : Slave Select DBMD : DMA Bus Monitor Data SIZE2-SIZE0 : Burst Size DBMF : DMA Bus Monitor First SR/W_B : Slave Read/Write DBML : DMA Bus Monitor Last TCLK : Transmit Clock DBVC : DMA Bus Monitor VC TENBL_B : Transmit Enable DBMR : DMA Bus Monitor Remaining TSOC : Transmit Start of Cell DR/W_B : DMA Read/Write TRF_B : Delay Select EMPTY_B/RxCLAV: PHY Output Buffer Empty Tx7-Tx0 : Transmit Data Bus ERR_B : Error V FULL_B/TxCLAV : PHY Buffer Ful GND : Ground GNT_B : Grant INITD : Initialization Disable INTR_B : Interrupt JCK : JTAG Test Pin JDI : JTAG Test Pin JDO : JTAG Test Pin JMS : JTAG Test Pin JRST_B : JTAG Test Pin OE_B : Output Enable PAR3-PAR0 : Bus Parity

: Power Supply

Data Sheet S12100EJ3V0DS00

Page 6

µµµµ

PD98401A

CONTENTS

1. PIN FUNCTION ..................................................................................................................................... 7

1.1 PHY Device Interface Pin ............................................................................................................. 7

1.2 Bus Interface Pins ........................................................................................................................ 9

1.3 Bus Monitor Pins........................................................................................................................ 12

1.4 Control Memory Interface Pins.................................................................................................. 13

1.5 JTAG Boundary Scan Pins........................................................................................................ 14

1.6 Test Pin........................................................................................................................................ 14

1.7 Power Supply and Ground Pins................................................................................................14

1.8 Pin Status During and After Reset............................................................................................15

2. DIFFERENCES FROM

2.1 Additional Functions..................................................................................................................16

2.2 Differences from

3. ELECTRICAL SPECIFICATIONS...................................................................................................... 17

4. PACKAGE DRAWINGS ...................................................................................................................... 33

5. RECOMMENDED SOLDERING CONDITIONS..................................................................................34

PD98401....................................................................................................16

µµµµ

PD98401 (NEASCOT-S10TM)........................................................................ 16

µµµµ

Data Sheet S12100EJ3V0DS00

Page 7

1. PIN FUNCTION

µµµµ

PD98401A

The µPD98401A is housed in a package having 208 pins, of which 152 pins are function pins and 56 pins are V

and GND pins.

1.1 PHY Device Interface Pin

PHY device interfaces include a UTOPIA interface through which the µPD98401A transfers ATM cells with a PHY

device, and a PHY control interface by which the µPD98401A controls the PHY device.

(1) UTOPIA interface

Pin Name Pin No. I/ O I/O Level Function

Rx7-Rx4 Rx3-Rx0

RSOC 86 I TTL Receive Start Cell.

RENBL_B 85 O CMOS Receive Enable.

EMPTY_B/ RxCLAV

RCLK 84 O CMOS Receive Clock.

Tx7-Tx0 95 - 102 O CMOS Transmit Data Bus.

TSOC 89 O CMOS Transmit Start of Cell .

74 - 77 80 - 83

87 I TTL PHY Output Buffer Em pt y/Rx Cell Available.

I TTL Receive Data Bus.

Rx7 through Rx0 constitute an 8-bit input bus which inputs data received from a network in byte format from a PHY device. The

PD98401A loads data in at the ris i ng edge of RCLK.

The RSOC signal is input in sy nchronization with the fi rst byte of the cell data from a PHY device. This signal remains high while the first byte of the header is input t o Rx7 through Rx0.

The RENBL_B signal indicat es to a PHY device that the is ready to receive data in t he next cl ock cycle. This signal goes high during and after reset.

This signal notifies the transferred in the receive FIFO and that no receive data can be supplied to the PHY device. When the UTOPIA interface is in the octet-level handshake mode, this signal serves as EMPTY_B, indicating that the data on Rx7 t hrough Rx0 are invalid in the current clock cycle. In the cell-level handshake mode, it serves as RxCLAV, indicating that there is no cell to be supplied next after the transfer of the current cell is completed.

This is a synchroniz ation cloc k used t o transf er cell dat a with the P HY cell device at the recieve side. The system clock input to the CLK pin is output from this pi n as is, immediately after reset.

Tx7 through Tx0 constitute an 8-bit out put bus which outputs transmit data in byte format to a PHY dev ic e. The the rising edge of TCLK.

The TSOC signal is output in synchronization with the f irst byte of transmit cell data.

PD98401A that there is no cell data to be

PD98401A

PD98401A outputs data at

(1/2)

Data Sheet S12100EJ3V0DS00

Page 8

Pin Name Pin No. I/ O I/O Level Function

TENBL_B 90 O CMOS Transmit Enabl e.

The TENBL_B signal indicates t o a PHY device that data has been output to Tx7 through Tx0 in the current clock cycle. This signal remains high during reset and after res et.

FULL_B/ TxCLAV

TCLK 92 O CMOS Transmit Clock.

88 I TTL PHY Buffer Full/Tx Cell Available.

The FULL_B signal notifies t he PHY device is full and t hat the device can receive no m ore data.

When the UTOPIA interface is in the octet -level handshake mode, the PHY device inputs an inact ive lev el to receiv e cell of data. I n the cell level handshake mode, this signal indicates that t he PHY device can receive all the next one cell of data after the current cell has been completely transferred

This is a synchroniz ation cloc k used t o transf er cell dat a with the P HY device at the transmission side. The system clock input to the CLK pin is output from this pi n as is.

PD98401A that the input buffer of the

µµµµ

PD98401A

(2/2)

(2) PHY device control interface

Pin Name Pin No. I/ O I/O Level Function

PHRW_B 109 O CMOS P HY Read/Write.

PD98401A indicates the direction in which the PHY device is

The

controlled, by using PHRW_B. This signal goes low aft er reset.

1: Read 0: Write

PHOE_B 108 O CMOS PHY Output Enable.

PD98401A enables output from the PHY device by making

The

PHOE_B low

PHCE_B 103 O CMOS PHY Chip Enable.

PD98401A makes PHCE_B low to access a PHY device. This

The

signal goes high after reset.

PHINT_B 107 I TTL PHY Interrupt.

This is an interrupt input signal from a PHY device. The PHY dev ice indicates to the inputting a low level to PHI NT_B. This signal goes high aft er reset.

PD98401A that it has an interrupt source, by

Data Sheet S12100EJ3V0DS00

Page 9

µµµµ

PD98401A

1.2 Bus Interface Pins

The bus interface is a general-purpose bus interface compatible with most generally used I/O buses (such as PCI,

S bus, GIO, and AP bus).

Pin Name Pin No. I/ O I/O Level Function

(1/3)

AD31-AD27 AD26-AD22 AD21-AD17 AD16-AD13 AD12 AD11-AD7 AD6-AD0

PAR3 PAR2 PAR1 PAR0

OE_B 56 I TTL Output Enable.

SIZE2 SIZE1 SIZE0

3 - 7

9 - 13 16 - 20 22 - 25

28 35 - 39 42 - 48

I/O

3-state

I/O

3-state

O CMOS Burst Size.

TTL in

CMOS out

TTL in

CMOS out

Address/Data. AD31 through AD0 constitute a 32-bit address/data bus . These pins

are I/O pins multiplex ing an address bus and a data bus. At the first clock of input/out put, AD31 through AD0 transfer an address . They transfer data at the second c lock and onward. The AD bus goes into a high-impedance state when the bus.

Bus Parity. PAR pins indicate the parit y of AD31 through AD0. A parity check

mode is set by GMR. Enabl ing or disabli ng parit y, odd or ev en parit y, and word or byte parity can be specified. If byte parity is specified, PAR3 indicates the parit y of AD31 t hrough AD24, and PA R0 indic ates the parity of AD7 through AD0. If word parity is specified, PAR3 serves as an input/output pin. It serves as an output pin when an address is output and when data is written, and as an input pin when data is read.

When the go into a high-impedance state. Pull up these pi ns when they are not used.

When this pin is low, the PAR3 through PAR0 as 3-state I/O pins. Thes e pins go into a highimpedance state while a high level is being input to OE _B. This pin is an option pin. Fix this pin to low level in a system where it is not necessary to forcibly set the bus of the impedance state by controlling this pin.

SIZE2 through SIZE0 indicate the s ize of the current DMA transfer. These pins are used to interface a bus (such as S bus) requiring c lear burst size.

PD98401A does not access t he bus, PAR3 t hrough PAR0

PD98401A does not access the

PD98401A uses AD31 through AD0 and

PD98401A in a high-

SIZE2 SIZE1 SIZE0 Function

0 0 0 1-word transfer 0 0 1 2-word burst 0 1 0 4-word burst 0 1 1 8-word burst 1 0 0 16-word burst 1 0 1 12-word burst 1 1 0 Undefined 1 1 1 Reception side byte alignment

Data Sheet S12100EJ3V0DS00

Page 10

Pin Name Pin No. I/ O I/O Level Function

DR/W_B 62 O CMOS DMA Read/Write.

DR/W_B indicates the direction of DMA access .

1: Read access 0: Write access

This pin is set to 1 after reset.

ATTN_B 63 O CMOS Attention/Burst Frame (DMA request).

PD98401A makes the ATTN_B signal low when it performs a

The

DMA operation. The ATTN_B signal becomes inactive at the rising edge of CLK when the data to be transferred by means of DMA has decreased to 1 word.

GNT_B 64 I TTL Grant.

The GNT_B signal inputs a low level when t he bus arbiter grants the

PD98401A use of the bus in respons e to a DMA request from the

PD98401A. The µPD98401A recognizes that it has been granted

use of the bus and starts DM A operation when the GNT_B signal goes low (active). Make sure that the GNT_B signal falls at least one system clock cycle after the rising of the ATTN_B signal. The GNT_B signal must be returned to the high (inactive) level before the

PD98401A makes the ATTN_B signal low (active) t o issue the next

DMA cycle request.

RDY_B 65 I TTL Target Ready.

RDY_B indicates to the device is ready for input/out put. During the DM A read operat ion of t he

PD98401A, the RDY_B signal i s made low if valid data is on AD31

through AD0. During the DMA write operation of the

is made low if the target dev i ce is ready for receiving dat a. The sampling timing of the RDY_B and ABRT_B signals of the

PD98401A can be advanced by one clock (early mode) by using an

internal register (GMR register).

ABRT_B 66 I TTL Abort.

ABRT_B is used to abort t he DMA transfer cycle. If this signal goes low while data is being transferred in the DMA cycle, DMA transfer is aborted in that cycle, and the ATTN_B signal is briefly deasserted inactive. After that, the again, and resumes burst transfer from the data at which the DMA transfer was aborted. While a low level is input to ABRT_B, the RDY_B signal is ignored. The user can advance the sam pling timing of the RDY_B and ABRT_B signals of the (early mode) by using an internal register (GMR regis ter). Pul l up thi s pin when it is not used.

ERR_B 67 I TTL Error.

This pin is used by a device that manages the bus to stop the operation of the on the system bus.

When a low level is input to thi s pin, the operations, sets the system bus error bit (bit 25) of the GSR register (when not masked), and generates an interrupt. Pull up this pi n when it is not used.

PD98401A in the DMA cycle that the target

PD98401A asserts the ATTN_B si gnal ac ti ve

PD98401A when occurrence of an error is det ected

µµµµ

PD98401A

PD98401A, the RDY_B signal

PD98401A by one clock

PD98401A stops all bus

(2/3)

Data Sheet S12100EJ3V0DS00

Page 11

Pin Name Pin No. I/ O I/O Level Function

SR/W_B 68 I TTL Slave Read/Write.

The SR/W_B signal determines the direction in which the slave is accessed.

1: Read access 2: Write access

SEL_B 69 I TTL Slave Select.

This signal goes low (ac tive) when the slave. The SEL_B signal must goes low as soon as or after the ASEL_B signal has gone low. An inactiv e period of at least 2 system clock cycles must be inserted between when the SEL_B signal has become inactive and when it becomes active again.

ASEL_B 70 I TTL Slave Address Select.

The ASEL_B signal is us ed to selec t the direct address regist er of the

PD98401A.

When a low level is input to ASEL_B, the bus at the first ris i ng edge of CLK.

CLK 32 I T T L Clock.

This pin inputs the system clock. Input a c lock in a range of 8 to 33 MHz.

RST_B 29 I TTL Reset.

PD98401A (on starting, etc.). A fter

INTR_B 71 O Nch open-

drain output

The RST_B signal initializ es the reset, the input to RST_B, the internal state machine and registers of the

PD98401A are reset, and all 3-state signals go into a high-

impedance state. The reset input is async hronous. When this signal is input during operation, the operat ing st atus at t hat t ime i s l ost . Hol d RST_B low at least for the durat ion of one clock. Aft er reset, do not access the

Interrupt. This is an open-drain signal and must be pulled up. INTR_B informs the CPU that the interrupt bit (unmas ked) of the GSR

PD98401A can start normal operati on. When a low lev el is

PD98401A for at least 20 clock cycles.

µµµµ

PD98401A

PD98401A is accessed as a

PD98401A samples the AD

(3/3)

Data Sheet S12100EJ3V0DS00

Page 12

µµµµ

PD98401A

1.3 Bus Monitor Pins

The bus monitor pins indicate the type of data under DMA transfer. These five pins are enabled when the BME bit

of the GMR register is set to 1; they go into a high-impedance state when the BME bit is 0.

Pin Name Pin No. I/ O I/O Level Function

DBMD 192 O

3-state

DBML 193 O

3-state

DBMF 194 O

3-state

DBMR 206 O

3-state

DBVC 206 O

3-state

CMOS DMA Bus Monitor Data.

This pin indicates that the payload of an AAL-5 cell is under DMA transfer. This pin is enabl ed when the BME bit of the GM R regist er is set to 1, and goes into a high-im pedance st ate when the BM E bit is 0. The DBMD signal changes in synchronizat ion with the falling of the ATTN_B signal. The high level of this signal indicates that the payload of an ALL-5 packet transmit/receive cell is under DMA transfer, and low level indicates that the other data is being transferred.

CMOS DMA Bus M oni tor Last.

If one-word data currently under DMA transfer satisfies any of the following conditions, t his pin goes high in synchroniz ation with output of the data.

•

Last 1 word of last cell of AAL-5 packet

•

1-word data to be written to last word of receive buffer

•

Last 1-word data of last cell of receive packet in which MAX. NUMBER OF SEGMENTS error has occurred

When this pin is low, it i ndicates that the data is other than above. This pin is enabled when the BME bi t of the GMR register i s set to 1; it goes into a high-impedance stat e when the bit is 0.

CMOS DMA Bus Monitor First.

This pin indicates that the data under DMA transf er is the st art cell of a receive AAL-5 packet. This pin is enabled when t he BME bit of the GMR register is set to 1; it goes into a high-impedance s tate when t he bit is 0. This pin goes hi gh in synchronizat ion with the last word dat a of the first cell of an AAL-5 packet.

CMOS DMA Bus Monitor Remaining.

This pin indicates that the number of cells remaining in the transmit buffer is equal to, or has dropped below the value as signed to the RCS register. This pin is enabled when the BME bit of the GMR register is set to 1; it goes into a high-impedance state when the bit is 0.

CMOS DMA Bus Monitor VC.

This pin indicates that the data currently being trans ferred by DMA i s that of the VC for which the VCP bit i n the rec eive V C tabl e is s et t o 1. This pin is asserted active in synchronization with the falling of ATTN_B. It is enabled when the B ME bit of the GM R regist er is s et t o 1, and goes into a high-impedance st ate when the bit is 0.

Data Sheet S12100EJ3V0DS00

Page 13

µµµµ

PD98401A

1.4 Control Memory Interface Pins

These pins constitute an interface through which the µPD98401A accesses an external control memory and a PHY device. A 18-bit address bus and a 32-bit data bus are used. The control memory of the host is accessed only via this interface.

Pin Name Pin No. I/ O I/O Level Function

CD31-CD28 CD27-CD21 CD20-CD16 CD15-CD7 CD6-CD0

CPAR3CPAR0

CA17-C11 CA10-CA4 CA3-CA0

CWE_B 186 O CMOS Control Memory Write E nabl e.

COE_B 187 O CMOS Control Memory Output Enable

CBE_B3 CBE_B2 CBE_B1 CBE_B0

INITD 188 I TTL Initialization Di sable.

110-113 116-122 125-129 132-140 143-149

151-154 I /O TTL in,

158-164 167-173 176-179

180 181 184 185

I/O

3-state

O CMOS Control M em ory Address.

O CMOS Local Port Byte Enable.

TTL in,

CMOS out

Control Memory Data. CD31 through CD0 are 3-state I/O pins and cons titute a 32-bit data

bus which is used to transfer data with the control mem ory or a PHY device.

Control Memory Parity. CPAR3 through CPAR0 indicate the parity of CD31 through CD0 in 8-

bit units. In the read cycle, the enabled). In the write cycle, CPAR3 through CPAR0 output the parity. Pull up these pins when they are not used.

CA17 through CA0 constitut e an 18-bit address bus. They output an address to the control memory or a PHY device during read/write operation.

CWE_B signal indicates the direction in which the control memory is accessed.

1: Read access 2: Write access

COE_B enables or disables data output of the control memory.

CBE_B3 through CBE_B0 indic ate the byte on the control port to be read or written.

The INITD signal is used to disable automatic initialization of the control memory during chip t est. During normal operation other than test, directl y connect INITD to GND.

PD98401A checks the parity (when

Data Sheet S12100EJ3V0DS00

Page 14

1.5 JTAG Boundary Scan Pins

Pin Name Pin No. I/ O I/O Level Function

JDI 201 I TTL JT A G Test Data Input.

The JDI pin is used to input data to the JTAG boundary scan circuit register.

Normally, fix t hi s pin to high or low level.

JDO 200 O

3-state

JCK 197 I TTL JTAG Test Clock.

JMS 202 I TTL JTAG Test Mode Select.

JRST_B 203 I TTL JTAG Test Reset.

CMOS JTAG Test Data Output.

The JDO pin is used to output data from the JTAG boundary scan circuit register. It c hanges output at the f alling edge of the cloc k input to the JCK pin.

Normally, leave this pi n open.

This pin is used to supply a clock to the JTAG boundary scan circuit register.

Normally, fix thi s pi n to a high or low level.

This pin initializes the J TAG boundary sc an circuit register. Normal ly, fix this pin to a low level.

µµµµ

PD98401A

1.6 Test Pin

Pin Name Pin No. I/ O I/O Level Function

TRF_B 189 I TTL This pin is used to test the int ernal circuitry of the chip.

0: Normal operation 1: Test

Normally, directly connect this pin to ground and fix it to a low level.

1.7 Power Supply and Ground Pins

Pin Name Pin No. I/O Function

GND 1, 2, 8, 14, 21, 26, 31, 33,

15, 27, 30, 34, 41, 53, 58, 72, 78, 94, 104, 114, 124, 130, 142, 157, 165, 174, 183, 190, 195, 198, 204, 208

40, 51, 52, 59, 73, 79, 91, 93, 105 ,106, 115, 123, 131, 141, 150, 155, 156, 166, 175, 182, 191, 196, 199, 205



Power supply (24 pins)

These 24 V

Ground (32 pins) Connect these pins to ground.

pins supply a voltage of +5 V ± 5% to the chip.

Data Sheet S12100EJ3V0DS00

Page 15

1.8 Pin Status During and After Reset

Pin During Reset After Reset AD0-AD31 Hi-Z (input mode) Hi-Z (input mode) PAR0-PAR3 Hi-Z (input mode) Hi-Z (input mode) SIZE0-SIZE2 0 0 DR/W_B 1 1 ATTN_B 1 1 INTR_B 1 (however, pulled up) 1 (however, pulled up) CA17-CA0 0 0 CD0-CD31 All 0 (output mode) All 0 (output mode) CWE_B 1 1 COE_B 1 1 (repetition of high/low) CBE_B3-CBE_B0 All 1 All 1 PHRW_B 0 0 PHOE_B 1 1 PHCE_B 1 1 RCLK CLK output CLK output RENBL_B 1 0 Tx0-Tx7 All 0 All 0 TCLK CLK output CLK output TENBL_B 1 1 TSOC 0 0 JDO Hi -Z (3-state) Hi-Z (3-state) DBMD Hi-Z Hi-Z DBML Hi-Z Hi-Z DBMF Hi-Z Hi-Z DBMR Hi-Z Hi-Z DBVC Hi-Z Hi-Z

µµµµ

PD98401A

Data Sheet S12100EJ3V0DS00

Page 16

µµµµ

PD98401A

2. DIFFERENCES FROM

PD98401

µµµµ

2.1 Additional Functions

The µPD98401A is compatible with the µPD98401 in terms of hardware and software. However, the µPD98401A has the following additional functions as compared with the µPD98401. All the

additional functions are enabled by the setting of the GMR register.

(1) DMA 12-word burst cycle (2) Byte alignment transfer function of receive data buffer (3) Bus monitor pin (4) Mode to insert idle cell for transmission rate adjustment (5) New scheduling function Aggregate mode (6) Receive packet size indication (cell units/Length mode added) (7) Cell-level support of UTOPIA interface (8) AAL-3/4 traffic assist function (9) JTAG boundary scan support

2.2 Differences from

PD98401 (NEASCOT-S10TM)

µµµµ

(1) Increased receive FIFO size

PD98401 : 10 cells

PD98401A : 23 cells

(2) Cell processing of PTI field (1

PD98401 : Receives cells other than those of OAM F5 pattern (101, 100) as user data cells.

PD98401A : Processes as raw cell of 1XX pattern. Stores in pool 0.

(3) Changing transmission mode of unassigned cell

The µPD98401 starts transmitting unassigned cells immediately after power application and continues transmitting the unassigned cells while there is no active transmission VC. It also has a function to stop transmitting unassigned cells while there is not an active VC, by using the UCE bit of the GMR register. The µPD98401A deletes this UCE bit function, makes the TENBL_B signal inactive on power application and when there is no active VC, and does not transmit unassigned cells. The µPD98401A transmits unassigned cells only when there is an active VC and when the unassigned cell generator function is enabled.

)

Data Sheet S12100EJ3V0DS00

Page 17

3. ELECTRICAL SPECIFICATIONS

An asterisk (*) mark indicates portion which have been revised from µPD98401.

Absolute Maximum Ratings

Parameter Symbol Condition Ratings Unit

µµµµ

PD98401A

Supply voltage V Input voltage V

∗

Output current

∗ ∗

Operating ambient temperature T Storage temperature T

Note 1

Note 2

stg

0.5 to +6.5 V

−

0.5 to V

−

+0.5 V 24 mA 36 mA

0 to +80

65 to +150

−

Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality

of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings.

DC Characteristics (T

∗

= 0 to +80

Parameter Symbol Condition MIN. TYP. MAX. Unit Low level input voltage V High level input voltage V

High level output voltage

Low level output voltage

Supply current I Input leakage current I Output leakage current I

OH1

OH2

OL1

OL2

IH1

IH2

°°°°

Note 1

Note 2

Note 1

Note 2

C, V

= 5 V

5 %)

±±±±

0.5 +0.8 V

−

Except pins RST_B or CLK +2.2 VDD + 0.5 V Pins RST_B or CLK + 3. 3 VDD + 0.5 V IOH = −4.0 mA VDD × 0.7 V IOH = −6.0 mA VDD × 0.7 V IOL = 8.0 mA 0.4 V IOL = 12.0 mA 0.4 V Normal operation 350 500 mA VI = VDD or GND Vo = VDD or GND

10 +10

−

10 +10

−

Notes 1.

OH1

, V

and V

OL1

apply to the following pins: CD31 - CD0, CPAR3 - CPAR0, CA17 - CA0, CBE_B3 - CBE_B0, CWE_B, COE_B, RCLK, RENBL_B, TSOC, TENBL_B, TCLK, Tx7 - Tx0, PHCE_B, PHOE_B, PHRW_B, JDO

IO2, V

OH2

and V

OL2

apply to the following pins: AD31 - AD0, PAR3 - PAR0, SIZE2 - SIZE0, DR/W, ATTN_B, INTR_B, DBMD, DBML, DBMF, DBMR, DBVC

Data Sheet S12100EJ3V0DS00

Page 18

µµµµ

PD98401A

Capacitance (TA = 25

C, VDD = 0 V, f = 1 MHz)

°°°°

Parameter Symbol Condition MIN. TYP. MAX. Unit Output capacitance C Input capacitance C I/O capacitance C

f = 1 MHz 7 10 pF

AC Characteristics (TA = 0 to +80 °C, VDD = 5 V

AC Test Condition

2.5 V 2.5 V

0 V

Load Condition

∗

D.U.T

(Device to be tested)

5 %)

±±±±

Test point

CLK Input

Parameter Symbol Condition MIN. TYP. MAX. Unit CLK cycle time t

∗

CLK high level width t

∗

CLK low level width t

∗

CLK rise time t

∗

CLK fall time t

CLK

CYCLK

CLKH

CLKL

= 50 pF

30 125 ns 11 ns 11 ns

4ns 4ns

CYCLK

CLKH

CLKL

Data Sheet S12100EJ3V0DS00

Page 19

PHY Interface (1/2)

(1) Transmission operation

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD98401A

TCLK TCLK TCLK

∗

FULL_B setup time t

TX delay time

↑

→

TSOC delay time

↑

→

TEMBL_B delay time

↑

→

FULL_B hold time t

TCLK

DTX

Tx7-Tx0

H1 H2 H3 H4 P1 P2 P3 P4 P5 P6 P7 P8 P9

TSOC

DTSOC

TENBL_B

SFULL

FULL_B

DTX

DTSOC

DTEN

SFULL

HFULL

‘00H’ INVALID

DTEN

HFULL

DTEN

318ns 318ns 318ns 8ns 1ns

H4-H1

: ATM Header

P9-P1

: Payload Data

Data Sheet S12100EJ3V0DS00

Page 20

PHY Interface (2/2)

(2) Reception operation

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD98401A

∗

RX setup time t

hold time t

∗

RSOC setup time t RSOC hold time t RCLK

∗

EMPTY_B setup time t

RENBL_B delay time

↑

→

EMPTY_B hold time t

RCLK

SRXtHRX

Rx7-Rx0

H1 H2 H3 H4 H5 P1 P2 P3 P4 P5 P6 P7

RSOC

SRSOC

HRSOC

RENBL_B

SRX

HRX

SRSOC

HRSOC

DREN

SEMPT

HEMPT

INVALID INVALID

SEMPT

HEMPT

DREN

8ns 1ns 8ns 1ns 318ns 8ns 1ns

DREN

EMPTY_B

H4-H1

: ATM Header

P7-P1

: Payload Data

Data Sheet S12100EJ3V0DS00

Page 21

Host Slave Access (1/2)

(1) Write

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD98401A

ASEL_B setup time t ASEL_B hold time t SEL_B setup time t SEL_B hold time t Address setup time t Address hold time t Data setup time t Data hold time t PAR setup time t PAR hold time t SR/W_B setup time t SR/W_B hold time t

Write timing

CLK

SASEL

HASEL

SSEL

HSEL

SDADD

HDADD

SDDAT

HDDAT

SPAR1

HPAR1

SSRW

HSRW

SASEL

HASEL

8ns 3ns 8ns

CYCLK

ns 8ns 3ns 8ns 3ns 8ns 3ns 8ns 3ns

ASEL_B

SEL_B

AD31-AD0

SR/W_B

PAR3-PAR0

SDADD

SSEL

HDADD

HSEL

SDDAT

ADDRESS DATA

SSRW

SPAR1

HSRW

HPAR1

SPAR1

(input) (input)

HDDAT

HPAR1

Data Sheet S12100EJ3V0DS00

Page 22

Host Slave Access (2/2)

(2) Read

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD98401A

ASEL_B setup time t ASEL_B hold time t SEL_B setup time t SEL_B hold time t Address setup time t Address hold time t CLK

data delay time

↑

∗

CLK

→

↑

→

data floating time PAR setup time t PAR hold time t CLK

PAR delay time

↑

∗

CLK

→

↑

→

PAR floating time SR/W_B setup time t SR/W_B hold time t

Read timing

CLK

SASEL

HASEL

SSEL

HSEL

SDADD

HDADD

DDDAT

FDDAT

SPAR1

HPAR1

DPAR1

FPAR1

SSRW

HSRW

8ns 3ns 8ns

CYCLK

ns 8ns 3ns

20 ns 318ns 8ns 3ns

ASEL_B

SEL_B

AD31-AD0

SR/W_B

PAR3-PAR0

SASEL

SSEL

SDADD

ADDRESS (input)

SSRW

SPAR1

(input) (output)

HASEL

HDADD

HSRW

HPAR1

HSEL

DPAR1

DDDAT

DATA (output)

FDDAT

FPAR1

Data Sheet S12100EJ3V0DS00

Page 23

DMA Access (1/2)

(1) Write

Parameter Symbol Condition MIN. TYP. MAX. Unit

CLK

ATTN_B delay time

↑

→

GNT_B setup time t GNT_B hold time t CLK

DR/W_B delay time

↑

→

CLK

SIZE delay time

↑

→

CLK

address delay time

↑

∗

→

CLK

address/data floating t i m e

↑

→

CLK

PAR delay time

↑

→

CLK

PAR floating time

↑

→

RDY_B setup time t RDY_B hold time t

DATTN

SGNT

HGNT

DDRW

DSIZE

DSADD

FSADD

DPAR2

FPAR2

SRDY

HRDY

µµµµ

PD98401A

18 ns 8ns 3ns 318ns 318ns

20 ns 318ns

20 ns 318ns 8ns 3ns

Write timing ( Example: 2 word burst)

CLK

DATTN

ATTN_B

GNT_B

DDRW

DR/W_B

DSIZE

SIZE2-SIZE0

AD31-AD0

RDY_B

(Normal mode)

RDY_B

(Early mode)

PAR3-PAR0

Hi-Z

SGNT

DPAR2

DSADD

HGNT

ADDRESS

(output)

FSADD

DATA 0 (output)

FPAR2

SRDY

DATTN

DDRW

DSIZE

FSADD

DATA 1

(output)

SRDY

HRDY

(output)(output)

HRDY

DPAR2

(output)

Data Sheet S12100EJ3V0DS00

Page 24

DMA Access (2/2)

(2) Read

Parameter Symbol Condition MIN. TYP. MAX. Unit

CLK

ATTN B_delay time

↑

→

GNT_B setup time t GNT_B hold time t CLK

DR/W_B delay time

↑

→

CLK

SIZE delay time

↑

→

CLK

address delay time

↑

∗

∗ ∗

→

CLK

address/data floating t i m e

↑

→

CLK

PAR delay time

↑

→

RDY_B setup time t RDY_B hold time t Data setup time t Data hold time t PAR setup time t PAR hold time t

DATTN

SGNT

HGNT

DDRW

DSIZE

DSADD

FSADD

DPAR2

SRDY

HRDY

SSDAT

HSDAT

SPAR2

HPAR2

µµµµ

PD98401A

18 ns 8ns 3ns 318ns 318ns

20 ns 318ns

20 ns 8ns 3ns 8ns 3ns 8ns 3ns

Read timing (Example: 2 word burst)

CLK

DATTN

ATTN_B

GNT_B

DDRW

DR/W_B

DSIZE

SIZE2-SIZE0

AD31-AD0

RDY_B

(Normal mode)

RDY_B

(Early mode)

PAR3-PAR0

Hi-Z

SGNT

DPAR2

DSADD

HGNT

ADDRESS

(output)

FSADD

SRDY

SPAR2

SRDY

SSDAT

DATA 0

(input)

HRDY

DATTN

HSDAT

HRDY

HPAR2

DDRW

DSIZE

DATA 1

(input)

(input)(input)(output)

Data Sheet S12100EJ3V0DS00

Page 25

Signals ABRT B, ERR B, and OE_B

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD98401A

∗

ABRT_B setup time t ABRT_B hold time t

∗

ERR_B setup time t ERR_B hold time t OE_B

∗

AD, PAR output

↓

→

definition time

∗

OE_B

AD, PAR Hi-Z definition

↑

→

time

DMA abort/ERR B timing

CLK

ATTN_B

GNT_B

SABRT

HABRT

SERR

HERR

DADOE

FADOE

SABRT

8ns 3ns 8ns 3ns

18 ns

HABRT

ABRT_B

ERR_B

OE_B timing

AD31-AD0

PAR3-PAR0

OE_B

DATA 0 (Output)

FADOE

Hi-Z

SERR

DADOE

HERR

DATA 0

(Output)

Data Sheet S12100EJ3V0DS00

Page 26

Bus Monitoring Signal

Parameter Symbol Condition MIN. TYP. MAX. Unit

CLK

DBMD delay time

↑

∗ ∗ ∗ ∗

Bus monitoring signal timing

CLK CLK CLK

→

↑

→

↑

→

↑

→

ATTN_B

DBMD

DBML delay time DBMF delay time DBMR delay time

CLK

tDDBMD

DDBMD

DDBML

DDBMF

DDBMR

µµµµ

PD98401A

18 ns

19 ns

18 ns

DBML

DBMF

DBMR

tDDBML tDDBML

tDDBMF tDDBMF

tDDBMR

Data Sheet S12100EJ3V0DS00

Page 27

Control Memory Access (1/2)

(1) Write

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD98401A

∗

CA→CWE_B↓ setup time t

∗

CBE_B→CWE_B↓ setup time t

∗

CWE_B low level width t

∗

CWE_B↑→CD floating time t

∗

CWE_B↑→COE_B delay time t

∗

CA hold time (vs. CWE_B↑)t CBE_B hold time (vs. CWE_B↑)t CD output time (vs. CWE _ B↑)t CWE_B↑→CPAR floating time t CPAR output time (vs. CWE_B↑)t

SCWE

SCWE2

CWEL

FCD

DCOE

HCA

HCBE

SCD

FCPAR

SCPAR

Write timing

CLK

CBE_B3-CBE_B0

SCWE2

0ns 0ns

CLKH

2ns

−

01t

CLKL

+10 ns 0ns 0ns 0ns 8ns 01t

CLKL

+10 ns 8ns

HCBE

CA17-CA0

CWE_B

COE_B

CD31-CD0

CPAR3-CPAR0

SCWE

SCD

SCPAR

CWEL

(output)

FCD

FCPAR

HCA

DCOE

Data Sheet S12100EJ3V0DS00

Page 28

Control Memory Access (2/2)

(2) Read

Parameter Symbol Condition MIN. TYP. MAX. Unit

CD delay enable time (vs. CBE_B↓)

∗ ∗

CD delay enable time (vs. CA) t

∗

CD delay enable time (vs. COE_B↓)

∗

CD hold time (vs. CBE_B↑)t

∗

CD hold time (vs. CA) t

∗

CD hold time (vs. COE_B↑)t

∗

CPAR hold enable time (vs. CBE_B↓)

∗

CPAR hold enable time (vs. CA ) t

∗

CPAR hold enable time (vs. COE_

∗

CPAR hold time (vs. CBE_B↑)t

∗

CPAR hold time (vs. CA) t

∗

CPAR hold time (vs. COE _B↑)t

B↓)t

DCDCB

DCDCA

DCDCO

HCDCB

HCDCA

HCDCO

DCPCB

DCPCA

DCPCO

HCPCB

HCPCA

HCPCO

µµµµ

PD98401A

−

CYCLK

−

CYCLK

−

CYCLK

1t 0ns 0ns 0ns

−

CYCLK

−

CYCLK

−

CYCLK

1t 0ns 0ns 0ns

Read timing

CLK

CBE_B3-CBE_B0

CA17-CA0

CWE_B

COE_B

CD31-CD0

‘H’

tDCDCB tDCDCA tDCDCO

tHCDCB tHCDCA tHCDCO

(input)

CPAR3-CPAR0

tDCPCO tDCPCA tDCPCB

Data Sheet S12100EJ3V0DS00

(input)

tHCPCO tHCPCA tHCPCB

Page 29

PHY Status Access (1/2)

(1) Write

Parameter Symbol Condition MIN. TYP. MAX. Unit

CLK

CA delay time

↑

→

CLK

PHRW_B delay time

↑

∗ ∗

Write timing

→

CLK

PHCE_B delay time

↑

→

CLK

CD delay time

↑

→

PHCE_B

↑

CA17-CA0

CD floating time

→

CLK

DPCA

DPHRW

DPHCE

DPCD

FPCD

1 clock 1 clock4 clocks

DPCA

CYCLK

µµµµ

PD98401A

−

10 1t

20 ns 20 ns 20 ns 20 ns

CYCLK

+10

PHRW_B

PHCE_B

PHOE_B

CD31-CD0

‘H’

DPCD

DPHRW

DPHCE

(output)

DPHCE

FPCD

DPHRW

Data Sheet S12100EJ3V0DS00

Page 30

PHY Status Access (2/2)

(2) Read

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD98401A

CD setup time t CD hold time t CLK

CA delay time

↑

→

CLK

PHRW_B delay time

↑

∗ ∗ ∗

→

CLK

PHCE_B delay time

↑

→

CLK

PHOE_B delay time

↑

→

Read timing

1 clock 6 clocks 4 clocks5 clocks

CLK

DPCA

CA17-CA0

DPHRW

PHRW_B

PHCE_B

PHOE_B

CD31-CD0

DPHCE

SPCD

HPOECD

DPCA

DPHRW

DPHCE

DPHOE

DPCA

0ns 0ns

20 ns 20 ns 20 ns 20 ns

DPHCE

DPHOE

SPCD

DPHOE

HPOECD

(input)

Data Sheet S12100EJ3V0DS00

Page 31

JTAG Boundary Scan

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD98401A

JCK cycle time t JCK high-level width t JCK low-level width t JMS setup time t JMS hold time t JDI setup time t JDI hold time t Capture_DR data input setup time t

∗

Capture_DR data input hold time t

↓

JCK

Up Date_DR output delay time

→

∗

JCK

JDO delay time

↓

→

JRST_B low-level width t

JTAG boundary scan timing

JCK

JCKH

CYJCK

JCKH

JCKL

SJMS

HJMS

DJOUT

DJDO

JRSTL

SJDI

HJDI

SJIN

HJIN

CYJCK

JCKL

100 ns

40 ns 40 ns 10 ns 10 ns 10 ns 10 ns 15 ns 15 ns

25 ns 20 ns

CYJCK

JRST_B

JMS

JDI

JDO

All input

All output

JRSTL

DJDO

DJOUT

SJMS

SJDI

SJIN

HJMS

HJDI

HJIN

Data Sheet S12100EJ3V0DS00

Page 32

Others

µµµµ

PD98401A

Parameter Symbol Condition MIN. TYP. MAX. Unit

SEL_B recovery time t SEL_B RDY_B

GNT_B↓ recovery time

↑

→

SEL_B↓ recovery time

↑

→

PHINT_B setup time t PHINT_B hold time t RST_B input pulse width t RST_B

SEL_B↓ recovery time

↑

→

Other timing

CLK

SEL_B

GNT_B

RDY_B

RVSEL

RVSM

RVMS

SPHI

HPHI

RSTL

RSTSL

2t 1t

RDY_B mode in normal operation 1 t

8ns 1ns 1t

20 t

tRVSEL

tRVMS

tRVSM

tSPHI

CYCLK

tHPHI

PHINT_B

RST_B

SEL_B

tRSTL

tRSTSL

Data Sheet S12100EJ3V0DS00

Page 33

4. PACKAGE DRAWINGS

208-PIN PLASTIC QFP (FINE PITCH) (28x28)

A B

µµµµ

PD98401A

157

156

105

104

detail of lead end

208

NOTE

Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A 30.6±0.2

28.0±0.2

C 28.0±0.2

D 30.6±0.2

1.25

G 1.25 H 0.22

I 0.10

J 0.5 (T.P.) K 1.3±0.2 L 0.5±0.2

M 0.17

N 0.10 P 3.2±0.1

Q 0.4±0.1

R5°±5° S 3.8 MAX.

P208GD-50-LML, MML, SML-6

+0.05

−0.04

+0.03

−0.07

Data Sheet S12100EJ3V0DS00

Page 34

µµµµ

PD98401A

5. RECOMMENDED SOLDERING CONDITIONS

Solder the product under the following recommended conditions. For details of the recommended soldering conditions, refer to Information Document

Mounting Technology Manual (C10535E)

For soldering methods and soldering conditions other than those recommended, consult NEC.

Surface Mount Type

PD98401AGD-MML: 208-pin plastic QFP (Fine pitch) (28 x 28 mm)

µµµµ

Soldering Method S ol deri ng Condi t i ons Symbol of Recommended Condi t i on

Semiconductor Device

Infrared reflow Package peak tem perat ure: 235 °C, Time: 30 seconds max . (210 °C

min.), Number of times : 2 max., Number of days: 7 prebaking is necessary at 125 °C for 36 hours.)

Partial heating Pin temperature: 300 °C max., Time: 3 sec onds max. (per side of device)

The number of days during which the product can be stored at 25 °C, 65 % RH max. after the dry pack has

Note

been opened.

Note

(Afterwards,

IR35-367-2

−

Data Sheet S12100EJ3V0DS00

Page 35

µµµµ

PD98401A

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

or GND with a

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

Data Sheet S12100EJ3V0DS00

Page 36

µµµµ

PD98401A

NEASCOT-S10 and NEASCOT-S15 are trademarks of NEC Corporation.

The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.

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