Datasheet UPD8049 Specification

NEe

Microcomputers,

Inc.

NEe

p.PD8049 p.PD8039L

DESCRIPTION

CONFIGURATION

EATU

F

HIGH SINGLE

The NEC /.IPDS049

differ of feature new, high performance

R ES • High Performance

• Full',' Compatible

•

• Programmable Interval Timer/Event Counter

•

• Single Level

• 96 Instructions: 70 Percent Single Byte

•

• I nternal Clock Generator

• Expandable

• Available in Both Ceramic

XTALl XTAL2

PERFORMANCE

CHIP8-BIT

and

/.IPDS039L

only in their internal program memory options: the /.IPDS049

mask

ROM

and the /.IPDS039L

11

MHz

with

Industry Standard S049/S039 Pin Compatible :'JMOS

1.36/.1s

2K

x 8 Bytes

27

I/O

TO

RESET

ss

INT

EA

RD

PsEN

WR

ALE

DBO DBl DB2 DB3 DB4 DB5 DB6 DB7

Vss

with

Silicon Gate Technology Requiring a Single

Cycle Time.

Lines

the./.IPD8048/S74S/S035

All

Instructions 1 or 2 Bytes

of

ROM, 12S x S Bytes

Interrupt

with

SOSOA/SOS5A

/.IPD

8049/

8039L

MICROCOMPUTERS

are

single chip 8-bit microcomputers. The processors

has

external program memory. Both

11

MHz operation.

Operation

+5V

of

RAM

Peripherals

and

Plastic 40-Pin

Vee Tl P27

P26 P25

P24 P17 P16 P15 P14 P13 P12 Pll Pl0 V

DD

PROG P23 P22

P21 P20

Packages

.

has

±10%Supply

2K

x S bytes

of

these devices

II

357

J.L

PD8049/8039L

The

NEC IlPDS049

parallel

microcomputers using N-channel

and

pPDS039L

and

function powerful instruction set eases and

BCD arithmetic.

large variety

The

pPDS049

with over

70

instruction with over

The

pPDS049 computers. peripherals

The devices: memory;

Their

and

pPDS049

204S x S bits

27 I/O lines; an S-bit interval

of

branch

and

percent

and

memories.

contains

Standard

pPDS039L

single-byte.

50

pPDS039L

functions

circuitry.

The

pPDS039L contains external program

is

intended for applications using external program

all

the

features

memory

products.

POWER

(UPPL

Y

I

IVDD

PROGRAM

SUPPLY

·w

flOW

STANDBYI

Ivcc

POWER

pPDS039L

are high performance, single

sil

efficiently

and

in

bit

control

handling applications and provides facilities for

logic

functions

table look-up instructions.

instruction set

The

instruction set requires

percent single-cycle.

microprocessors will

the

of

can easily

following

mask

ROM

be

functions

program

timer/event

of

the

pPDS049

can be

except

implemented

icon gate MOS technology_

component,

as well as

is

arithmetic

implementation

comprised

of

1 and 2

is

only 1 or

expanded

usually

memory;

the

using

function using standard SOSOA/SOB5A

counter;

204S

as stand-alone micro·

found

in

external peripheral

12S x S bits

and oscillator

x S-bit internal ROM.

standard

SOSOA/SOS5A

S-bit

T,he

pPDS049

applications.

facilitated by

byte

instructions

2 cycles per

of

RAM

data

and

memory

only.

memory

The binary

the

clock

The

FUNCTIONAL DESCRIPTION

It

BLOCK

DIAGRAM

EXPANSION

EXTERNAL

TO

ADDITIONAL

MEMORY

AND'

0

358

INTERRUPT

PAOMIEXPANOER

STROBE

CONTROL AIIIO

TIMING

ADDRESS

STROBEl

CYCLE

PROORAM

MEMORY

ENABLE

SINGLE

READ

STEP STROBES

WRITE

Aee

ACCStT

TEST

REGISTER

REGISTER 2

REGISTER

REGISTER 6

REGISTER

8-LEVELSTACK IVARIABLE

RESIDENT

PTIONAl

EGISTEA

DATA

(128 x

1

3

7

WORD

SECOND

BANK

MEMORY

81

LENGTH)

AND

PORT

1

IDENTIFICATION

NO. SYMBOL

1

2

3

4

5

6

7

8

9

10

11

12·19

20

21·24,

35·38 PORT 2 data

25 PROG PROG

26

27·34

39 T1 Testable

40

TO

XTAl1

XTAL2

RESET

SS

INT

EA

RD

PSEN Program Store Enable

WR

ALE

DO·D7 BUS

VSS

P20,P27:

VDD

P10,P17:

PORT 1

VCC

Testable internal State

instruction.

One side compatible

The sources, the

Active

PROM programming verification and power·down patible

Single Step

processor to "single-step" through memory.

Interrupt interrupt rupt.

External Access

mands the processor to perform all program external memory.

READ sor performs a BUS

·processor BUS STROBE

during an external memory fetch.

WR processor performs a STROBE

Address Latch Enable the peripherals.

8-bit,

formed DO·D7 BUS can During significant

addressed instruction. Also, for an external

tion

address and data information.

Processor's

Port 2

counter 4·bit

sian. When the can

VDD normal operation V functions at

Port 1 is

can be made the Primary

input

using conditional transferfunctionsJTOand,JNTO. The

Clock

(ClK)

TO

can

of

the crystal,

VIH')

other

side

of

XTAl

XTAl 1 input.

INT

ITE

falling

the DO·D7 BUS,

memory

I/O

be

is used

+5V

2 must

low

input from processor

VIH).

input

(active·low).

instruction

can

be

tested

input

strobe

outputs

from

for

external

strobe

output

for

external

edge

of

ALE

bidirectional port. Synchronous

on this

port

be

an

external memory

bits

of

GROUND

is

the second

fetches, the

are contained in P20·P23'

bus

for

the

is

used

as

an

"PD8049

allowed

to

provide

in the device.

while

VCC

one

of

two

input

using conditional transfer

counter/timer

Power supply. VCe.

is

also

be

used

lC,

or

the crystal

be

driven

(active·low).

has

been

by

issuing a

(active·high). A logic

(active·low).

READ.

a peripheral device and

DATA output

(active·low). WR

BUS

WR

DATA

output

ALE

latches

can

also

be

using

RD

latched in a static mode.

the program counter. PSEN

controlled

potential.

of

two

8-bit

four

"PD8243,INPUT/OUTPUT

output

strobe

is

used

float.

+5V

CC

must

~Iso

During

is

at ground

8·bit

quasi·bidirectional ports,

is

"

fL'

PD8049/8039L

FUNCTION

available

to

TO

using

RESET

with

ALE

instruction

an

interrupt

will jump

"1"

at

memory

pulse

low

function

will

pulse

also

function

for

external

output.

and writes can

controls

RAM

data store instruc-

R15

and WR, contains

bits

EXPANDER, during

bit

RAM

to

provide

functions

STRT

normal

the ENTO

complement

this

ports.

VDD

JTl

operation.

during programming

external frequency source.

or

LC frequency source.

with

the logical

initiali~ation.

SS

together

each

INT

will

start

executed. A reset

conditional

RD

will

m5

will

also enable data

MEMORY.

(active·low). PSEN becomes active

ITE.

WR

can

MEMORY. (active·high). Occurring once each cycle,

the

address

used

as a clock

reads

and WR strobes. The contents

fetch,

the DO·D7 BUS holds the least

by

ALE,

quasi~bidirectional

most significant

Bits P20,P23 are also used

for

"PD8243's

in a stand·alone mode the PROG pan

to

the

128 x 8

be

+5V

stand·by operation

potential.

input

using the

+5V

during

ClK

as

a testable flag.

(Non·TTl

For

external

is

also

used

(non·TTl

low

of

power

com·

allows the

in

program

if

an

enable

disable the

instruction.

input

com·

fetches from

when the proces·

onto

the

as a READ

when the

as a WR

memory

be

of

the

incoming'

For

external

the program

as

I/O

expan·

section.

During

to

the

must

remain

and

JNT1.

CNT

instruction.

of

inter·

only

ITE

or

per-

a

other

T1

for

II

359

J.L

PD8049/8039L

Operating Temperature

.........

Storage Temperature (Ceramic Package) . Storage Temperature (Plastic Package) . Voltage on Any Pin Power

Dissipation

CD

Note:

With respect

COMMENT: Stress above those listed

damage

to

the

any

other

implied.

reliability. 'Ta

= 25°C

Ta

'"

Input

Except

(AU

Input

(AI!

Except

Input

(RESET,

Output

WR.

Output

Outputs

Output Output

WR,

Output Outputsl

Input

(Tl.

EA. INT)

Output (BUS,

Power Down Supply Total

device. This

conditions

Exposure

O°C

to

+70°C; Vee'" VOD

PARAMETER

Low

Voltage

XTAL

1,

High Voltage

XTAL

1,

High Voltage

XTAL

1.

XTAl

Low

Voltage (BUS. AD.

PSEN.

ALE)

Low Voltage (All Other

Except

PROG)

Low

Voltage (PROG)

High Voltage (BUS, RD,

PSEN.

ALE)

High Voltage

Leakage Current

Leakage

Current

TO -High

Impedance

Supply

Current

to

XTAL

(AI!

Current

above

absolute

'"

+5V ± 10%;

2)

2.

RESET)

2)

Other

State)

-

to

ground.

is

a stress

those

rating

indicated

maximum

Vss

'"

SYMBOL

VIL

VIH

VIHl

VOL

VOLl

VOl2

VOH

VOHl

III

IOl

IDD

IDO + ICC

under"

rating

OV

o°C

to

.

-65°C

.

-65°Cto+125°C

to

+150°C

+70°C

- 0.5 to +7 Volts

. . . . . .

Absolute Maximum Ratings" may cause permanent

only

and

in

the

conditions

MIN

-0.5

2.0

3.8

2.4

functional

operational

LIMITS

TYP

I'

25

100

MAX

Vee

±10

±lO

50

170

0.8

0.45

for

UNIT

operation sections extended

V

IOl

V

IOL=1.6mA

IOL = 1.0

V

IOH = -lOO"A

V

IOH = -50

VSS';

"A

Vee;;'

"A

mA

Ta"" 2S"C

mA

Ta

of

this

periods

TEST CONDITIONS

= 2.0 mA

VIN

VIN;;'

= 25°e

the

device

specification

may

rnA

"A

.;

Vee

VSS + O.45V

..

at

affect

these

CD

1.5 W

or

is

not

device

ABSOLUTE

MAXIMUM

RATINGS*

DC

CHARACTERISTICS

360

RESET

SINGLE

STEP

sus

LOGIC

PORT

#1

PORT

s

I'PD

B049/

8039L

s

#2

READ WRITE

PROGRAM STORE

ENABLE

ADDRESS

PORT

LATCH

ENABLE

EXPANOER

STROBE

SYMBOL

}L:PD8049/803IL

AC

CHARACTERISTICS

Ta

0'

C

ALE

Pulse

Address

Control

Data

Setup

Data

Hold

Cycle

Time

Data

Hold

PSEN,

RD

Address Address Address

Notes

T a =

O'c

Port

Control

Edge

of

Port

Control

Edge

of

PROG

to

Valid

Output

Output Input

Data

PROG Pulse

Port

2 110

Port

2 1/0

READ, WRITE

to

+70"C;

PARAMETER

Width

Setup

before

Hold

from

Pulse

Width

before

WR

after

WR

to

Data

Setup

before

Setup

before

Float

to

RD,

CD

For

Control

@

For

Bus

@

tCY

= 1,361's

to

+70'C;

PARAMETER

Setup

PROG

Hold

after

PROG

Time

P2 I

Data

Setup

Data

Hold

Time

Hold

Time

Width

Data

Setup

Data

Hold

AND

DATA

AND

VCC c VDD ~ +5V

ALE

IPSEN,

RD,

WRI

In

WR Data

In

PSEN

Outputs:

Failing

must

CL = 80

CL = 150

± 10%; VSS =

be

Outputs

Vcc = +5V

before

nput

Time

INSTRUCTION FETCH -

PROGRAM MEMORY

± 10%; VSS

SYMBOL

tLL tAL tLA tcc tnw two tCY tOR tRD tAW tAD tAFC

pF

PORT 2

SYMBOL

tcp

tpr:

tpR top tpD tPF tpp

tPL

tLP

pF

OV

~

OV

LIMITS MIN 150

70

50 300 250

40

1,36

0

200

-40

TIMING

LIMITS

MIN

TYP

100

60

200

20

0 700 150

20

TYP

EXTERNAL

MAX

15,0 100

200

400

MAX

UNIT

650

150

UNIT

ns ns ns

I'S

ns ns ns ns ns

ns

ns ns ns ns ns ns ns

TEST

CONDITIONS

CL=20pF@

TEST

CONDITIONS

II

TIMING

WAVEFORMS

ALE

BUS

t---~tLL~-tCY-~·1

~

INSTRUCTION

~I

____________

FETCH

FROM

EXTERrlAL

MEMORY

~I

--~L_

FLOATING

361

J.L

PD8049/8039L

ALE

BUS

ALE

BUS

--1

FLOATING

-'

FLOATING

READ

FROM

EXTERNAL

DATA

MEMORY

FLOATING

TIMING WAVEFORMS

L

(CaNT.)

L

-

WRITE

TO

EXTERNAL

ALE

EXPANDER

OUTPUT

EXPANDER

PORT

PCH

I

PORT 20-3

DATA

!

INPUT

PROG--------------------------------~

PCH

PORT 2

TIMING

362

MEMORY

'--

______

PORT CONTROL

-_

...

tDP

OUTPUT

1

----<tPD-

DATA

INSTRUCTION SET

MNEMONIC

AOD

A,

ADO

A,

ADOA,@Rr

ADOC

A,

AODC

A, Rr

ADOC

A,@

ANL

A.

ANL

A.

ANLA,@Ar

CPL A

CLA A

OAA

DEC A

INC A

ORL

A.

ORL

A,

ORLA,@Rr

RL

A

RLe

A

RR

A

RAC

A

SWAP A

XRL

A,

XRL

A,

XRL

A,@

DJNZ

Ar.

JBb

addr

JC

addr

JFO

addr

JF'

addr

JMP

addr

JMPP@A

JNC

addr

JNI

add,

FUNCTION

==

data

{AI'

IAI

+

data

Rr

::

Rr

-"

Rr

-=

Ar

'"'

data

Rr

addr

data

Rr

(AI·

(AI

+

(Ad

for r '"

0 7

(AI·

(AI

..

(lRdl

tor r "0

,

(AI,

(AI + (Cl +

IAl'

IAl + (el + (Rr)

for r = 0 7 (AI·

\AI t ICI t

for r

"0

,

IAI·

IAI

AND

data

(AI·

(AI

AND

r

~

(AI

'"

-

NOT

0

(AI ,

(AI

(AI OA

(AI OA IAr!

"0

(Al OR

"0

11·

)

~

O

N"

(A71

(AOI

IAI

IAI XOR

r

~

0 - 7

(AI

r

~

0 - 1

(Rd

0

11)'

0 7

AND

0 ,

(AI

+'

7

,

IANI

(A7

1

0 - 6

IAOI

ICI

(A

O

XOR

oF

0

7)

-.

addr

71 -addr

(PCI"

7) -addr

(PC) + 2

7) --addr

71 -addr

(PC) t 2

101·

71·

'ilddr 0 7

DBF

7)·

(1M)

7)·

addr

IPC) +

n·

addr

(PC) t 2

(Ar)

((Ad)

data

HRd)

31

data

(Rr)

!lRr))

1; r =-0 7

2"

of

If

addr

:?

of

If

for (AI·

for r

IAI

(AI·

tAl

tAl'

(AI· for r

IAN"

(A

for (AN+ll·-(ANI;N=O

(AO) - ICI

ICI' (ANI ~ (AN + 1 I;

IA71· (AN) - IAN + 1 i; N

(A7i' IC)'

IA4-71.·

(AI·

(AI· for

(AI·

for

IRd -(Rd

If

(PC (PC 0

(PCI· (PC 0 -

IPC)' (PC 0

(PC) . )(PC) + 2 (PC 0

IPC)' IPC a

(PC 0 (PC

(PCO

(PC 0 IPC)'

(PC 0 (PC)·

data

ItRrl)

6

N"

0 6

'"

0 - 6

If

Bb" 1 Jump

Bb

0 0

II

C ~ ,

C - 0 If

FO

~,

FO

0 set. a7

,I

F,

~,

F,

0 a7

a

10

of

CoO

C 1 low

,\ I 0

I'

DESCRIPTION

Anc1lmmedlatli'

Accumulator, Add

COntents

the

Accumulator.

Add

Indirect

memory

location

Add

Immediate

data

10

the

Add With

carry

deSignated

register

Add

Indirect

data

memory

Accumulator. Logical

and

With

Accumulator

Logical

and

reg,ster

With

logical

and

memory

With

Complement

Accumulator

CLEAR

the

DECIMAL

ADJUST

ACCumulato,

DECREMENT

Increment

by 1 the

Logical

OR

With

Accumulator

Logical OR

contents

register

WIth

Logical

OR

memory

locat,on

Rotate

Accumulator

carry.

Rotate

AccumUlator

carry.

Rotate

Accumulator

Without

carry

Rotate

Accumulator

through

carry.

Swap

the 2 4'blt

Accumulator.

With

Accumulator

Logical XOR

register With

Logical XOR

memory

location

Decrement

the

to

speclhed

Accumulator Jump

to

specified

Jump

to

specof,ed

Jump

to

speCified

O"e,ct

Jump

the

2K

address

Jump

Indorect

wtth

address

Jump

to

spec,fled

Jump

to

5pec,j,ed

,<;

low

the

specified

of

deSignated

register

the

contents

the

to

the

Accumulator.

With

carry

Accumulator

specified

conlenl~

Indirect

contents

specified

Accumulator.

Indirect

Accumulator

to speClf,ed

paqe

the

contents

of

to

the

Accumulator.

With

carry

the

contents

location

to

the

ImmedIate

of

designated

Accumulator.

the

contents

Accumulator.

the

contents

of

the

Accumulator

the

contents

by 1

the

accumulator's

Immediate

of

deSignated

the

contents

With

AccumulaTor,

left by

'·b,t

left by

l·bl'

roght

by

fight by

nibbles

In

the

contents

oj

deSignated

Indirect

the

Conlents

With

Accumulato!

specdled

register

address

d

bit's

set. a7

address

If

carfY Ilatj , 0

address

,I

Flag

address

of

Flag

",dd,p'~s

block

10

specd'~d

ildd,e~~

addre~~

of

~;(lIrY

add,e,\

of

,n!""upl

ACCUMULATOR

Data

to

the

to

data

specified

the

of

Data

of

data

the

of

the

date.

of

data

Without

through

l·b,t

'·b,t

of

data

BRANCH

and

FO

IS

F,

I,

Within

wlih

!I':lIj

1\

INSTRUCTION

07 06 05 04 03 02

0

d7 d6

dS

0 0

d7

d6

dS

0

d7

d6

dS

o 0

1

d7

d'6

dS

o 0

dS

o

,

b2

tJ,

bO

a6

a5

<17

a6 a5

0

a6

as

, 0

a6 a5

alO

a9

aa

a7

"6

af>

27

d6 il5

iJ7

il6 il5

CODE

rJ4

rl3 d:?

1

d4 d3

d4 d3 d2

<14

iJ3

34

a3 ;;2

a4

iJ3

"4

"3

a4 "3

"4

ilJ

14

"3

0,

dl

{12

d,

1

d2

d,

<12

a,

a2

'"

a2

a,

1 0

"2

a,

"2

J,

1

;02

,q

DO

CYCLES

dO

{JO

dO

SYTES C At

FLAGS

FO

Fl

II

"0

aO

ao

aO

,10

363

,.,.

PD8049/8039L

INSTRUCTION

SET

(CONT.)

MNEMONIC

JNTO

addr

JNT1

addr

JNZ

addr

JTF

addr

JTO

addr

JTl

addr

JZ

addr

EN

I

DIS I

ENTO

eLK

SEL

MBO

SEL

M8l

SEL

RBO

SEL

RSl

MOV

A,

"data

MOV

A,

Rr

MOV

A,@Rr

MOV

A, PSW

MOV

Rr,

MOV

Rr,

MOV@Rr,A

MOV@

Rr, .:

MOVPSW,

MOVP

A.@A

MOVP3

A.@

MOVX

A,@R

MOVX@R,A

XCH

A,

Rr

xeH

A,@Rr

XCHO

A,@Rr

ePL

e

CPL

FO

CPL

Fl

CLR C

FO

CLR

Fl

FUNCTION

(PC 0 --71·

add!'

if

TO

~-

addr

If

21f

T1

addr

If

21f

A 0

addr

if

211

TF 0

-,

addr

if

If

TO

addr

If

T1

if

0 7

r

'"

0 1

r = 0 7

r

'"

0 7

r

~

0

(AI

0'11

r = 0 1

0 1

r"

0 - 7

r'"

0 - 1

((Rd) 0-3));

IC)

(Fa) (F1i

Tl

A

..

TF ~ 1

TO

"'-

T1

= 1

0

A

'"

,..

- 0

~

0

1

0

= 1

0

(PCi

.- (PC) + 2 If TO'" 1

(PC 0

-.

7)

(PC)-

(PC) +

{PC

0

7\·

(PC)·

(PC) t

(PC 0 7) -

(PC)·

(PC) t

(PC 0 .

7i

(PC)~·

(PC) + 2

(PC 0

7)·

(PC)·

(PC) t 2

(PC 0

7)·-addr

(PC)'

(PC) + 2 If A 0

(OBF)·

a

(OBF)·

1

18S) - 0

(8SI·

1

(A):

data

(AI-

(Rrl;r

(A) -

((Rrli;

(Af

- (PSWI

."':

data

(Rr)·

data;

(Rrl--

A

data

A

(A};

((Rr))·-

(AI; ro<O 1

((Rdl

-

data;

(PSWI- (AI

(PC a

71 -fA)

(AI·

HPC}J

(PC 0 71·

(PCS

10) -

(A)

- ((PC)!

(A)

•. -((Rd);

((Rd) -(A);r"

(AI;:

(Rr);

{Ai

.---:

{(Rd);

(A 0-3i':;'r

'"

Or

1

(CI'

NOT

(FO) ~ NOT

(Fl)·

NOT

(el'

0

(Fa)

--a

(F1)·

0

DESCRIPTION

Jump

to

specified

address

Jump

to

specified

address

Jump

to

~pecdll;ld

address

Jump

to

sfjl!cilled

to

1

to

specified address

to

speCified

to

specified

the

External

the

Clock

Bank

0 (iocations 0

Memory.

{locations

Bank 1 (locations

Memory,

Immediate

the

conte!"'ts of

Into

the

Indirect

the

location

contents

of

mto

the

Accumulator.

Immediate

Accumul<ltor

Indirect

Accumulator

data

memory

Immediate

memory.

contents

of

status

word.

data m the

Pr~w:am

da~a

Indirect

the

memory

mto

Indirect

th"e

Into

the

Accumulator

Indirect

and

locatIon

Indirect

and

Content Content Content

content

of

content

of

content

of

address

address " Test 1 IS a 1.

address

Interrupt

Output

the

speCified

Accumulator.

contents

Into

the

speCified

Contents

location.

the

Accumulator

current

In

contents the

conteQts external

contents.

contents

in

data

4·blt

data

carry Flag a to Flag 1

IS

set

Jump

is

O.

Enable

Disable the Enable Select

Program Select Bank 1 (locatiOns

Program

Select Bank 0 Memory.

Select

Data.

Move the

Accumulator'.

Move registers

Move memory

Move Word

Move the

deSignated register.

Move deSignated register.

Move mto

Move data

Move program

Move Accumulator.

Move data

Move Accumulator

Exchange deSignated register's

Exchange lator

Exchange Accumulator

Complement Complement Complement Clear Clear Clear

II

Test 0 IS

If

Test t

If

accumulator

If

Timer

If

Test 0

if

Accumulator

Interrupt

TO.

2047)

2048

0 - 7)

24

31)

the

deSignated

of

the

Accumulator.

Program

Into

Contents

specified

page

Page

3.

Into

of

Accumulator.

of data

and

of

memory.

contents

memory

of

carry

of

Flag

FO.

of Flag F 1

bit

to

O.

to

O.

BRANCH

IS

Flag

IS

,'(lput.

input.

of

4095)

of

Data

of

DATA

data

Into

data

Status

data

Into

the

data

Into

mto

the

external

the

memory.

Accumu-

of

bit.

low.

a

CONTROL

of

MOVES

the

FLAGS

07 06

(CQNT.)

'7

0

'7

1

'7

d7

INSTRUCTION

05

'6

'5

'6

0

'6

'5

0

'6

'5

0

1 0

'6

'5

'6

0

'6

'5

0

d6

d5

0

d6

d5

1 0 0 0

d6

d5

D.

'0

'.

'0

dO

0

dO

CODe

03

'3

0

'3 '2

0

'3

'3 '2

d3

0,

02

'1

'2

'1

'2

'1

1 0

'1

'2

1 0

'1

'2

1

'1

'2

1

'1

d2

dl

d2

dl

CYCLES

DO

'0

0

'0

BYTES

'0

1

dO

C

FLAGS

AC

Fl

FO

364

INSTRUCTION SET (CONT.)

JLPD8049/8039L

MNEMONIC

ANl

ANL

ANlD

IN

A.

INS

A,

MOVD

MOVO

OR L BUS, "

ORlO

OR

l PP. ::

OUTL

DEC

Ar

INC

Ar

INC@Rr

CALL

RET

AETR

EN

TCNTI

DIS

TCNT!

MOVA,

MOV T, A

STOP STAT STATT

NOP

Notes'

BUS,

::

dillS

pp.

=

data

Pp, A

Pp

BUS

A,

Pp

PP. A

data

Pp, A

data

BUS, A

rp.

A

fAr)

addr

T

TeNT

CNT

<D

Instruction

®

The

dot

@ Aeferences

@)

Numerical

(SUS) •

(Ppl·

p . 1

(Pp) p"

(A)

(AI,

(A

a -

IA4

(Pp)

(BUS)

(Ppl

P"

(Pp) • p

~

IBUS) .

(Pp) .

(Rr)-

IRrl-(Ar)+l.r"O

((Ar)) . r"

0

((SPII' (SP) .

(PC 8

(PC 0 (PC

(SP) • (PC)

(SPI· fPC) . (PSW4

(A)·

(T) .

Code

under

the

to

the

Subscrtpts

FUNCTION

(BUS)

IPp)

2

~

(Ppj

7

4

•

(Ppl.

(BUS)

31 -IPp);

7) - 0

- A 0

.'

(BUS)

...

(Pp) OR (A 0

7

4

(PpJ OA

1

2

IAI

(AI. p

(Ad

((Ad)

1

(PCI. (PSW 4

(SP) + 1

10)'

7)

-addr

111·

DB'

(SPI

.

USPII (SP)

((SP))

71·

ITI

IAI

Oeslgnallons

approprtate

address

appearing

AND

p-

3,

1

and

p

~

1

1; r

+ 1.

addr

(fSPll

AND

1

OR

data

(A

0

2

P"

4 7

-=

4

data

2

"0

8

0

7

rand p form flag bit

data

are

in

the

Symbol Definitions;

SYMBOL

A The Accumulator

The

AC

addr Program Memory Address (12 bits)

BUS

ClK eNT Event Counter

data

OBF

FO.

Bit

Bb BS

C

0

Fl

I Interru t·

P

Designator (b

The Bank Switch

The

Carry Flag Clock 5i nal

Nibble Designator (4 bits) Number Memory Bank Flip-Flop

Flags

"In-Page" Operation Designator

DESCRIPTION

Auxiliary

Carry Flag

'"

0 - 7)

BUS

Port TF Timer Flag

or

Expression (8 bits)

O.

1

31

7

31

7

71

10

Indicates spec FUNCTION

Logical

and

\/Vlth

contents

Logical

and

with

deSignated

Logtcat

and

deSignated

Input

data

Into

Accumulator.

Input

strobed

Move

contents

Into

Accumulator.

Move

contents

deSignated

Logical

or

contents

of

Logical or deSignated

Output

contents

BUS. Output

contents

deSignated

Decrement reg,ster.

Increment register.

Increment data

memory

Call deSignated

Return

from

restoring

Program

Return

from

Prograln

Status

Enable

Internal

Timer/Counter Disable

Internal

Timer/Counter Move

contents

Accumulator. Move

contents

Timer/Counter.

Stqp

Count

Start

Count

Start

Count

No

Opl>ratlon

the

binary

that

Its

If

ted

In

bytes

column

DESCRIPTION

Immedlate'$pec",ed

01

BUS.

Immediate

specified

port

f 1

or

contents

01

Accumulator

port

14

71.

from

deSignated

BUS data

mto

of

deSignated

of

Accumulator

port

14

71.

Immediate

specified

BUS.

contents

of

Accumulator

port

14

71.

Immediate

specified

Pori

(1

21

of

AccumUlator

01

Accumulator

port

11

21.

by 1

contl!nts

by 1 contents

Indirect

of deSignated

by 1

the

location.

Subrout.ne.

Subroutine

Wl\hout

Status

WorCi.

Subroutlno! restOflnq

Word.

Interrupt

output.

Interrupt

output.

of

Timer/Counter

of

Accumulator

for Event

Counter

for Event

Counter.

for Timer

performed.

representat,on content

IS

subject

'2

and/or

1 of

r,ference

INSTRUCTION

01

d7

d7 d6

with 1

21

0

71

"7

d7

of

'10

'7

0 0

and

Ports

by

the

InstrUCtion

affected.

Port DeSignator (p Program Status Word Register Designator (r Stack Pointer

Testable External RAM Prefix Prefix

Contents Contents

by

Replaced

06 05 04

0

d,

d6

dS

0

d,

dS

1

0 0

0

d4

d6

"S

0 0

d4

dS

"6

0 0

'9

'R

'6

'4

's

InvOlved

It

appears

DESCRIPTION

Flags

0, 1

for

Immediate Data

for

Indirect Address

Of

External RAM Location

of

Memory Location Addressed

the Contents

Bv

INPUT/OUTPUT

data

21

port

i 1

Accumulator.

port

(4

to

data

With

data

With

onto

to

REGISTERS

of deslqna!ed

contents

SUBROUTINE

TIMER/COUNTER

Flag for

,nto

Into

MISCELLANEOUS

of

The

Registers

to

change

the

InstruCtton

the

spec;iflc bits

SYMBOL

Pp

PSW

Rr SP

T Timer

TO.

Tl

X

=

@

S Program Counter's Current Value

(x)

lix))

-

CODE

03 02

01

d3

d2

dl

p

0

d,

d3

,j3

dl

"2

1

d2

"1

"3

0

'2

'1

'3

,n

1, 2 or

4 -

7)

'"

0, 1

or

0 - 7)

of

External RAM Location.

DO

CYCLES

BYTES

0

dO

p

dO

p

dO

C

'0

C AC

FLAGS

FO

Fl

II

365

J.L

PD8049/8039L

I,

...

l

~TT'

H-

A . I

I I

~~

t--------

E

--------l

FK~

1.='

'=±6-

G •

(PLASTIC)

ITEM

A

B

C

D 0.5 ±

E 48.26 +

F

G 2.54

H

I

J 5.72

K 15.24 TYP. 0.600 TYP.

L 13.2 TYP.

M

MILLIMETERS

MMC

51.5

1.62

MAX.

2.54 +

0.1

1.2 MIN. MIN.

0.5 MIN.

5-:2-2

MAX. MAX.

025

+0.1

• -0.05

G

,"_"J

INCHES

2.028

0.064 MAX.,

0.10 ± 0.004

0.019 ± 0.004

1.9 ± 0.004

0.047

0.10MIN.

0.019

0.206

0.225

0.520 TYP. 0010

.

-

~

MAX.

MIN.

MIN. MAX. MAX.

+0.004

-0.002

PACKAGE OUTLINES

J.lPD8049C J.lPD8039LC

J.lPD8049D J.lPD8039LD

366

ITEM

A 51.5

B

C D

E

F 1.02

G

H

I 3.5

J

K

L

M

MILLIMETERS

(CERAMIC)

MAX.

1.62

MAX.

2.54 ±

0.1 0.1

0.5 ±

0.1

±

0.1

48.26 MIN.

3.2MIN.

1.0MIN. MAX.

4.5

MAX.

15.24 TYP.

14.93 TYP.

0.25 ± 0.05

INCHES

2.03

MAX.

0.06

MAX.

± 0.004

0.02 ± 0.004

1.9 ± 0.004

0.04

MIN.'

0.13MIN.

0.04

MIN.

0.14

MAX.

0.18

MAX.

0.6

TYP.

0.59 TYP.

± 0.0019

0.01

8049/8039 LDS-1 2-80-CAT