Datasheet UPD78P4908GF-3BA Datasheet (NEC)

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD78P4908

16-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The µPD78P4908, 78K/IV series' product, is a one-time PROM version of the µPD784907 and µPD784908 with

internal mask ROM.

Since user programs can be written to PROM, this microcomputer is best suited for evaluation in system

development, manufacture of small quantities of multiple products, and fast start-up of applications.

For specific functions and other detailed information, consult the following user's manuals.
These manuals are required reading for design work.

µ

PD784908 Subseries User's Manual - Hardware : U11787E

78K/IV Series User's Manual - Instruction : U10905E

FEATURES

• 78K/IV series

• Internal PROM: 128 Kbytes

• Internal RAM: 4,352 bytes

• Supply voltage: VDD = 4.5 to 5.5 V

(At main clock: f
V

DD = 4.0 to 5.5 V

(Other than above: f

ORDERING INFORMATION

Part number Package Internal ROM

µ

PD78P4908GF-3BA 100-pin plastic QFP (14 × 20 mm) One-time PROM

XX = 12.58 MHz, internal system clock = fXX: fCYK = 79 ns)

CYK = 159 ns)

The information in this document is subject to change without notice.

Document No. U11681EJ2V0DS00 (2nd edition)
Date Published February 1999 N CP(K)
Printed in Japan

The mark shows major revised points.

©

1996

78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM

: Under mass production

: Under development

µ

PD78P4908

Standard models

PD784026

µ

Enhanced A/D,
16-bit timer,
and power
management

ASSP models

PD784955

µ

For DC inverter control

PD784908

µ

Equipped with IEBus
controller

I2C bus supported

PD784038Y

µ

PD784038

µ

Enhanced internal memory capacity,
pin compatible with the PD784026

µ

PD784216Y

µ

PD784216

100 pins,
enhanced I/O and
internal memory capacity

µ

PD784054

µ

PD784046

Equipped with 10-bit A/D

PD784938

µ

Enhanced function of the PD784908,

TM

enhanced internal memory capacity,
added ROM correction

µ

µ

Multimaster I2C bus supported

PD784225Y

µ

PD784225

µ

80 pins,
added ROM correction

Multimaster I2C bus supportedMultimaster I2C bus supported

PD784218Y

µ

PD784218

µ

Enhanced internal memory capacity,
added ROM correction

µ

PD784915

For software servo control,
equipped with analog circuit
for VCR,
enhanced timer

Multimaster I2C bus supported

PD784928Y

µ

PD784928

µ

Enhanced function of the PD784915

µ

2

Data Sheet U11681EJ2V0DS00

FUNCTIONS

µ

PD78P4908

(1/2)

Item

Number of basic instructions
(mnemonics)

General-purpose register
Minimum instruction execution

time
Internal

memory

Memory space
I/O ports

Additional
function

Note

pins

Real-time output ports
IEBus controller
Timer/counter

Clock timer

Clock output
PWM outputs
Serial interface

ROM
RAM

Total
Input
Input/output
LED direct

drive outputs
Transistor

direct drive
N-ch open

drain

Function

113

8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping)

• 320 ns/636 ns/1.27

• 160 ns/320 ns/636 ns/1.27

128 Kbytes
4,352 bytes
Program and data: 1 Mbyte
80
8
72
24

8

4

4 bits × 2, or 8 bits × 1
Incorporated (simple version)
Timer/counter 0: Timer register × 1 Pulse output capability

(16 bits) Capture register × 1 • Toggle output

Timer/counter 1: Timer register × 1 Real-time output port
(16 bits) Capture register × 1

Timer/counter 2: Timer register × 1 Pulse output capability
(16 bits) Capture register × 1 • Toggle output

Timer 3: Timer register × 1
(16 bits) Compare register × 1

Interrupt requests are generated at 0.5-second intervals. (A clock timer oscillator is
incorporated.)
Either the main clock (6.29 MHz/12.58 MHz) or real-time clock (32.768 kHz) can be
selected as the input clock.

Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (can be used as a 1-bit output port)
12-bit resolution × 2 channels
UART/IOE (3-wire serial I/O) : 2 channels (incorporating baud rate generator)

CSI (3-wire serial I/O) : 2 channels

µ

s/2.54 µs (at 6.29 MHz)

µ

s (at 12.58 MHz)

Compare register × 2 • PWM/PPG output

• One-shot pulse output

Capture/compare register × 1
Compare register × 1

Capture/compare register × 1 • PWM/PPG output
Compare register × 1

Note Additional function pins are included in the I/O pins.

Data Sheet U11681EJ2V0DS00

3

µ

PD78P4908

(2/2)

Item

A/D converter
Watchdog timer
Standby
Interrupt

Power supply voltage

Package

Hardware source
Software source
Nonmaskable
Maskable

Function

8-bit resolution × 8 channels
1 channel
HALT/STOP/IDLE mode
27 (20 internal, 7 external (sampling clock variable input: 1))
BRK or BRKCS instruction, operand error
1 internal, 1 external
19 internal, 6 external

• 4-level programmable priority

• 3 operation statuses: vectored interrupt, macro service, context switching

• VDD = 4.5 to 5.5 V (At main clock: fXX = 12.58 MHz, internal system clock = fXX: fCYK =

79 ns)

• VDD = 4.0 to 5.5 V (Other than above: fCYK = 159 ns)

100-pin plastic QFP (14 × 20 mm)

4

Data Sheet U11681EJ2V0DS00

µ

PD78P4908

CONTENTS

1. DIFFERENCES BETWEEN µPD78P4908 AND MASK ROM PRODUCTS ............................ 6

2. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 7

3. BLOCK DIAGRAM ..................................................................................................................... 1 0

4. PIN FUNCTIONS ........................................................................................................................ 1 1

4.1 PINS FOR NORMAL OPERATING MODE.................................................................................... 11

4.2 PINS FOR PROM PROGRAMMING MODE (V

4.2.1 Pin Functions ................................................................................................................. 14

4.2.2 Pin Functions ................................................................................................................. 15

4.3 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS ................................................. 16

PP ≥ +5 V or +12.5 V, RESET = L) .................... 14

5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS).......................................................... 19

6. PROM PROGRAMMING ............................................................................................................ 20

6.1 OPERATION MODE........................................................................................................................ 20

6.2 PROM WRITE SEQUENCE ............................................................................................................ 2 2

6.3 PROM READ SEQUENCE ............................................................................................................. 26

7. SCREENING ONE-TIME PROM PRODUCTS .......................................................................... 26

8. ELECTRICAL CHARACTERISTICS ......................................................................................... 27

9. PACKAGE DRAWING ................................................................................................................ 51

10. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 52

APPENDIX A DEVELOPMENT TOOLS .......................................................................................... 53

APPENDIX B CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWING ..................... 56

APPENDIX C RELATED DOCUMENTS ......................................................................................... 58

Data Sheet U11681EJ2V0DS00

5

µ

PD78P4908

1. DIFFERENCES BETWEEN µPD78P4908 AND MASK ROM PRODUCTS

The µPD78P4908 is produced by replacing the mask ROM in the µPD784907 or µPD784908 with PROM to which

µ

data can be written. The functions of the
for the PROM specification such as writing and verification, except that the PROM size can be changed to 96 or 128
Kbytes, and except that the internal RAM size can be changed to 3,584 or 4,352 bytes.

Table 1-1 shows the differences between these products.

Table 1-1. Differences Between the

PD78P4908 are the same as those of the µPD784907 or µPD784908 except

µ

PD78P4908 and Mask ROM Products

Product name
Item
Internal program

memory

Internal RAM

Pin connection
Power supply voltage

Electrical
characteristics

µ

µ

PD78P4908

• 128-Kbyte PROM

• 96-Kbyte mask ROM

PD784907

µ

PD784908

• 128-Kbyte mask ROM

• Can be changed to 96

Kbytes by IMS

• 4,352-byte internal RAM

• 3,584-byte internal RAM

• 4,352-byte internal RAM

• Can be changed to 3,584

bytes by IMS

Pin functions related to writing or reading of PROM have been added to the µPD78P4908.

• VDD = 4.5 to 5.5 V • VDD = 4.0 to 5.5 V

(At main clock: fXX = 12.58 (At main clock: fXX = 12.58 MHz, internal system clock = fXX:
MHz, internal system clock = fCYK = 79 ns)
fXX: fCYK = 79 ns • VDD = 3.5 to 5.5 V

• VDD = 4.0 to 5.5 V (Other than above: fCYK = 159 ns)

(Other than above: fCYK =
159 ns)

Partially differs between these products.

6

Data Sheet U11681EJ2V0DS00

2. PIN CONFIGURATION (TOP VIEW)

(1) Normal operation mode

• 100-pin plastic QFP (14 × 20 mm)

µ

PD78P4908GF-3BA

P35/TO1

P34/TO0

P33/SO0

P32/SCK0

100

99

98

97

96

P37/TO3

P100

Note 2
Note 3

2
3
4P101
5P102
6P103
7P104
8P105/SCK3
9P106/SI3
10P107/SO3
11RESET
12XT2
13XT1
14V

SS

15X2
16X1
17REGOFF
18REGC
19VDD
20P00
21P01
22P02
23P03
24P04
25P05
26P06
27P07
28P67/REFRQ/HLDAK
29P66/WAIT/HLDRQ
30P65/WR

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

P31/TxD/SO1

P30/RxD/SI1

P27/SI094P26/INTP5

95

93

92

P25/INTP4/ASCK/SCK1

P24/INTP3

P23/INTP2/CI

P22/INTP1

P21/INTP0

P20/NMI87TX86RX85AVSS84AVREF183AVDD82P77/ANI7

91

90

89

88

µ

PD78P4908

81

80 P76/ANI61P36/TO2
79 P75/ANI5
78 P74/ANI4
77 P73/ANI3
76 P72/ANI2
75 P71/ANI1
74 P70/ANI0
73 TEST
72 PWM1
71 PWM0
70 P17
69 P16
68 P15
67 P14/TxD2/SO2
66 P13/RxD2/SI2
65 P12/ASCK2/SCK2
64 P11
63 P10
62 ASTB/CLKOUT
61 P90
60 P91
59 P92
58 P93
57 P94
56 P95
55 P96
54 P97
53 P40/AD0
52 P41/AD1
51 P42/AD2

Note 1

P64/RD

P63/A19

P62/A18

Notes 1. Connect the TEST pin to V

2. Connect the REGOFF pin to V

3. Connect the REGC pin to V

SS

V

VDD

P61/A17

P60/A16

P57/A15

P56/A14

P55/A13

P54/A12

SS directly.

SS directly (select regulator operation)

SS through a 1-

Data Sheet U11681EJ2V0DS00

µ

F capacitor.

P53/A11

P52/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

7

µ

PD78P4908

A8-A19 : Address bus
AD0-AD7 : Address/data bus
ANI0-ANI7 : Analog input
ASCK, ASCK2 : Asynchronous serial clock
ASTB : Address strobe

DD : Analog power supply

AV

REF1 : Reference voltage

AV

SS : Analog ground

AV
CI : Clock input
CLKOUT : Clock output
HLDAK : Hold acknowledge
HLDRQ : Hold request
INTP0-INTP5 : Interrupt from peripherals
NMI : Non-maskable interrupt
P00-P07 : Port 0
P10-P17 : Port 1
P20-P27 : Port 2
P30-P37 : Port 3
P40-P47 : Port 4
P50-P57 : Port 5
P60-P67 : Port 6
P70-P77 : Port 7
P90-P97 : Port 9
P100-P107 : Port 10

PWM0, PWM1 : Pulse width modulation output
RD : Read strobe
REFRQ : Refresh request
REGC : Regulator capacitance
REGOFF : Regulator off
RESET : Reset
RX : IEBus receive data
RxD, RxD2 : Receive data
SCK0-SCK3 : Serial clock
SI0-SI3 : Serial input
SO0-SO3 : Serial output
TEST : Test
TO0-TO3 : Timer output
TX : IEBus transmit data
TxD, TxD2 : Transmit data

DD : Power supply

V

SS : Ground

V
WAIT : Wait
WR : Write strobe
X1, X2 : Crystal (main system clock)
XT1, XT2 : Crystal (watch)

8

Data Sheet U11681EJ2V0DS00

(2) PROM programming mode

• 100-pin plastic QFP (14 × 20 mm)

µ

PD78P4908GF-3BA

µ

PD78P4908

OPEN

RESET

OPEN

OPEN

V

PGM

OPEN

SS

V

(L)A9V

SS

OPEN

OPEN

VSSVSS

VDD

OPEN

81828384858687888990919293949596979899100

1
2
3

4
5
6

7
8
9
10
11
12
13

SS

V
VSS

14
15

V

16

SS

17

DD

18

19
D0
D1
D2
D3
D4
D5
D6
D7
(L)

20

21

22

23

24

25

26

27

28

29

CE

30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

80
79
78

77
76
75

74
73
72
71
70
69
68
67
66
65
64
63
62

61
60
59
58
57
56
55
54
53
52

51

OPEN

PP

V

OPEN

A0
A1

A2

OE

(L)

A15

A14

A13

A12

SS

V

VDD

A11

A8A7A6A5A4

A10

A16

A3

Caution L : Connect these pins separately to the VSS pins through 10-kΩ pull-down resistors.

SS : To be connected to the ground.

V
Open : Nothing should be connected on these pins.
RESET: Set a low-level input.

A0-A16 : Address bus RESET : Reset
CE : Chip enable V
D0-D7 : Data bus V
OE : Output enable V

DD : Power supply
PP : Programming power supply
SS : Ground

PGM : Program

Data Sheet U11681EJ2V0DS00

9

3. BLOCK DIAGRAM

µ

PD78P4908

NMI

INTP0-INTP5

INTP3

TO0
TO1

INTP0

INTP1

INTP2/CI

TO2
TO3

P00-P03

P04-P07

PWM0
PWM1

ANI0-ANI7

AVDD

AVREF1

AVSS

INTP5

TX

RX

RESET

TEST

X1
X2

REGC

REGOFF

Note

VPP

VDD

VSS

Programmable
interrupt controller

Timer/counter 0

(16 bits)

Timer/counter 1

(16 bits)

Timer/counter 2

(16 bits)

Timer 3

(16 bits)

Real-time output
port

PWM

A/D converter

IEBus controller

System control

(regulator)

78K/IV

CPU core

(RAM 512 bytes)

RAM

(3,840 bytes)

Watchdog timer

ROM

(128 Kbytes)

UART/IOE2

Baud-rate
generator

UART/IOE1

Baud-rate
generator

Clocked serial
interface

Clocked serial
interface 3

Clock output

Bus interface

Port 0
Port 1

Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 9

Port 10

RxD/SI1
TxD/SO1

ASCK/SCK1

RxD2/SI2
TxD2/SO2

ASCK2/SCK2

SCK0
SO0
SI0

SCK3
SO3
SI3

ASTB/CLKOUT
AD0-AD7
A8-A15
A16-A19

RD
WR
WAIT/HLDRQ
REFRQ/HLDAK

Note

D0-D7

Note

A0-A16

Note

CE

Note

OE

Note

PGM

P00-P07
P10-P17

P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P77
P90-P97
P100-P107

XT1

Watch timer

XT2

Note In the PROM programming mode.

10

Data Sheet U11681EJ2V0DS00

4. PIN FUNCTIONS

4.1 PINS FOR NORMAL OPERATING MODE

(1) Port pins (1/2)

µ

PD78P4908

Pin

P00-P07

P10
P11
P12
P13
P14
P15-P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34-P37
P40-P47

I/O

I/O

Input

I/O

I/O

I/O

Also used as

—

—

—
ASCK2/SCK2
RxD2/SI2
TxD2/SO2

—
NMI
INTP0
INTP1
INTP2/CI
INTP3
INTP4/ASCK/SCK1
INTP5
SI0
RxD/SI1
TxD/SO1
SCK0
SO0
TO0-TO3
AD0-AD7

Function

Port 0 (P0):

• 8-bit I/O port.

• Functions as a real-time output port (4 bits × 2).

• Inputs and outputs can be specified bit by bit.

• The use of built-in pull-up resistors can be simultaneously specified by

software for all pins in input mode.

• Can drive a transistor.
Port 1 (P1):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of built-in pull-up resistors can be simultaneously specified by

software for all pins in input mode.

• Can drive LED.

Port 2 (P2):

• 8-bit input-only port.

• P20 does not function as a general-purpose port (nonmaskable

interrupt). However, the input level can be checked by an interrupt
service routine.

• The use of built-in pull-up resistors can be specified by software for pins
P22 to P27 (in units of 6 bits).

• The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 input/output pin
by CSIM1.

Port 3 (P3):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of built-in pull-up resistors can be simultaneously specified by

software for all pins in input mode.

• P32 and P33 can be set as the N-ch open-drain pin.

Port 4 (P4):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of built-in pull-up resistors can be simultaneously specified by

software for all pins in input mode.

• Can drive LED.

Data Sheet U11681EJ2V0DS00

11

(1) Port pins (2/2)

µ

PD78P4908

Pin

P50-P57

P60-P63
P64
P65
P66
P67
P70-P77

P90-P97

P100-P104
P105
P106
P107

I/O

I/O

I/O

I/O

I/O

I/O

Also used as

A8-A15

A16-A19
RD
WR
WAIT/HLDRQ
REFRQ/HLDAK
ANI0-ANI7

—

—
SCK3
SI3
SO3

Function

Port 5 (P5):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of built-in pull-up resistors can be simultaneously specified by

software for all pins in input mode.

• Can drive LED.
Port 6 (P6):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of built-in pull-up resistors can be simultaneously specified by

software for all pins in input mode.

Port 7 (P7):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

Port 9 (P9):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of built-in pull-up resistors can be simultaneously specified by

software for all pins in input mode.

Port 10 (P10):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of built-in pull-up resistors can be simultaneously specified by

software for all pins in input mode.

• P105 and P107 can be set as the N-ch open-drain pin.

12

Data Sheet U11681EJ2V0DS00

(2) Non-port pins (1/2)

µ

PD78P4908

Pin
TO0-TO3
CI
RxD
RxD2
TxD
TxD2
ASCK
ASCK2
SI0
SI1
SI2
SI3
SO0
SO1
SO2
SO3
SCK0
SCK1
SCK2
SCK3
NMI
INTP0

INTP1

INTP2

INTP3

INTP4
INTP5
AD0-AD7
A8-A15
A16-A19
RD
WR
WAIT
REFRQ
HLDRQ
HLDAK
ASTB

I/O
Output
Input
Input

Output

Input

Input

Output

I/O

Input

I/O
Output
Output
Output
Output
Input
Output
Input
Output
Output

Also used as
P34-P37
P23/INTP2
P30/SI1
P13/SI2
P31/SO1
P14/SO2
P25/INTP4/SCK1
P12/SCK2
P27
P30/RxD
P13/RxD2
P106
P33
P31/TxD
P14/TxD2
P107
P32
P25/INTP4/ASCK
P12/ASCK2
P105
P20
P21

P22

P23/CI

P24

P25/ASCK/SCK1
P26
P40-P47
P50-P57
P60-P63
P64
P65
P66/HLDRQ
P67/HLDAK
P66/WAIT
P67/REFRQ
CLKOUT

Function
Timer output
Input of a count clock for timer/counter 2
Serial data input (UART0)
Serial data input (UART2)
Serial data output (UART0)
Serial data output (UART2)
Baud rate clock input (UART0)
Baud rate clock input (UART2)
Serial data input (3-wire serial I/O 0)
Serial data input (3-wire serial I/O 1)
Serial data input (3-wire serial I/O 2)
Serial data input (3-wire serial I/O 3)
Serial data output (3-wire serial I/O 0)
Serial data output (3-wire serial I/O 1)
Serial data output (3-wire serial I/O 2)
Serial data output (3-wire serial I/O 3)
Serial clock I/O (3-wire serial I/O 0)
Serial clock I/O (3-wire serial I/O 1)
Serial clock I/O (3-wire serial I/O 2)
Serial clock I/O (3-wire serial I/O 3)
External interrupt request —

• Input of a count clock for timer/counter 1

• Capture/trigger signal for CR11 or CR12

• Input of a count clock for timer/counter 2

• Capture/trigger signal for CR22

• Input of a count clock for timer/counter 2

• Capture/trigger signal for CR21

• Input of a count clock for timer/counter 0

• Capture/trigger signal for CR02

—

Input of a conversion start trigger for A/D converter
Time multiplexing address/data bus (for connecting external memory)
High-order address bus (for connecting external memory)
High-order address during address expansion (for connecting external memory)
Strobe signal output for reading the contents of external memory
Strobe signal output for writing on external memory
Wait signal insertion
Refresh pulse output to external pseudo static memory
Input of bus hold request
Output of bus hold response
Latch timing output of time multiplexing address (A0-A7) (for connecting

external memory)

Data Sheet U11681EJ2V0DS00

13

(2) Non-port pins (2/2)

µ

PD78P4908

Pin
CLKOUT
PWM0
PWM1
RX
TX
REGC

REGOFF

RESET
X1
X2
XT1
XT2
ANI0-ANI7
AV

REF1

AVDD
AVSS
VDD
VSS
TEST

I/O
Output
Output
Output
Input
Output

—

—

Input
Input

—

Input

—

Input

—

Input

Also used as

ASTB

P70-P77

—
—
—
—
—

—

—
—

—
—

—

Function
Clock output
PWM output 0
PWM output 1
Data input (IEBus)
Data output (IEBus)
Capacitor connection for stabilizing the regulator output/Power supply

when the regulator is stopped. Connect to V
Signal for specifying regulator operation. Directly connect to VSS (regulator

selected).
Chip reset
Crystal input for system clock oscillation (A clock pulse can also be input

to the X1 pin.)

Real-time clock connection

Analog voltage inputs for the A/D converter
Application of A/D converter reference voltage
Positive power supply for the A/D converter
Ground for the A/D converter
Positive power supply
Ground
Directly connect to V

SS. (The TEST pin is for the IC test.)

SS via a 1-

µ

F capacitor.

4.2 PINS FOR PROM PROGRAMMING MODE (VPP ≥ +5 V or +12.5 V, RESET = L)

4.2.1 Pin Functions

Pin name

V

PP

RESET
A0-A16
D0-D7
CE
OE
PGM
V

DD

VSS

Input

I/O
Input

I/O

—

—
—

PROM programming mode selection
High voltage input during program write or verification

PROM programming mode selection
Address bus
Data bus
PROM enable input/program pulse input
Read strobe input to PROM
Program/program inhibit input during PROM programming mode
Positive power supply
GND

Function

14

Data Sheet U11681EJ2V0DS00

4.2.2 Pin Functions

(1) V

PP (Programming power supply): Input

µ

Input pin for setting the
+6.5 V or more and when RESET input goes low, the
When CE is made low for V

PD78P4908 to the PROM programming mode. When the input voltage on this pin is

µ

PD78P4908 enters the PROM programming mode.

PP = +12.5 V and OE = high, program data on D0 to D7 can be written into the internal

PROM cell selected by A0 to A16.

(2) RESET (Reset): Input

µ

Input pin for setting the
the input voltage on the V

PD78P4908 to the PROM programming mode. When input on this pin is low, and when

PP pin goes +5 V or more, the

µ

PD78P4908 enters the PROM programming mode.

(3) A0 to A16 (Address bus): Input

Address bus that selects an internal PROM address (0000H to 1FFFFH)

(4) D0 to D7 (Data bus): I/O

Data bus through which a program is written on or read from internal PROM

µ

PD78P4908

(5) CE (Chip enable): Input

This pin inputs the enable signal from internal PROM. When this signal is active, a program can be written or
read.

(6) OE (Output enable): Input

This pin inputs the read strobe signal to internal PROM. When this signal is made active for CE = low, a one­byte program in the internal PROM cell selected by A0 to A16 can be read onto D0 to D7.

(7) PGM (Program): Input

The input pin for the operation mode control signal of the internal PROM.
Upon activation, writing to the internal PROM is enabled.
Upon inactivation, reading from the internal PROM is enabled.

DD

(8) V

Positive power supply pin

(9) V

SS

Ground potential pin

Data Sheet U11681EJ2V0DS00

15

4.3 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS

Table 4-1 describes the types of I/O circuits for pins and the handling of unused pins.
Figure 4-1 shows the configuration of these various types of I/O circuits.

Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)

µ

PD78P4908

Pin

P00-P07
P10, P11
P12/ASCK2/SCK2
P13/RXD2/SI2
P14/TXD2/SO2
P15-P17
P20/NMI
P21/INTP0
P22/INTP1
P23/INTP2/CI
P24/INTP3
P25/INTP4/ASCK/SCK1

P26/INTP5
P27/SI0
P30/R

XD/SI1

P31/TXD/SO1
P32/SCK0
P33/SO0
P34/TO0-P37/TO3
P40/AD0-P47/AD7
P50/A8-P57/A15
P60/A16-P63/A19
P64/RD
P65/WR
P66/WAIT/HLDRQ
P67/REFRQ/HLDAK
P70/ANI0-P77/ANI7
P90-P97
P100-P104
P105/SCK3
P106/SI3
P107/SO3
ASTB/CLKOUT

I/O circuit type

5-A

8-A
5-A

2

2-A

8-A

2-A

5-A

10-A

5-A

20
5-A

10-A
8-A
10-A
4

I/O

I/O

Input

I/O

Input

I/O

I/O

Output

Recommended connection method for unused pins

Input state: To be connected to VDD
Output state: To be left open

To be connected to VDD or VSS

To be connected to VDD

Input state: To be connected to VDD
Output state: To be left open

To be connected to VDD

Input state: To be connected to VDD
Output state: To be left open

Input state: To be connected to V
Output state : To be left open

To be left open

DD or VSS

16

Data Sheet U11681EJ2V0DS00

µ

PD78P4908

Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)

Pin

RESET
TEST
XT2
XT1
PWM0, PWM1
RX
TX
AV

REF1

AVSS
AVDD

I/O circuit type

2
1

—

3
1
3

—

I/O

Input

—
Input
Output
Input
Output

—

Caution When the I/O mode of an I/O dual-function pin is unpredictable, connect the pin to V

Recommended connection method for unused pins

—
To be connected to V
To be left open
To be connected to VSS
To be left open
To be connected to VDD or VSS
To be left open
To be connected to VSS

To be connected to VDD

SS directly

DD through

a resistor of 10 to 100 kΩ (particularly when the voltage of the reset input pin becomes higher
than that of the low level input at power-on or when I/O is switched by software).

Remark Since type numbers are consistent in the 78K series, those numbers are not always serial in each product.

(Some circuits are not included.)

Data Sheet U11681EJ2V0DS00

17

Figure 4-1. I/O Circuits for Pins

Data

V

DD

P

N

IN/OUT

Output
disable

VDD

P

Pull-up
enable

Input
enable

Data

V

DD

P

N

IN/OUT

Output
disable

VDD

P

Pull-up
enable

µ

PD78P4908

Type 1

VDD

P

IN

N

Type 2

IN

Schmitt trigger input with hysteresis characteristics

Type 3

V

DD

P-ch

Data OUT

N-ch

Type 4

VDD

Data

P

Type 2-A

VDD

P

Pull-up
enable

IN

Schmitt trigger input with hysteresis characteristics

Type 5-A

Type 8-A

Output
disable

Push-pull output which can output high impedance
(both the positive and negative channels are off.)

Type 10-A

Pull-up
enable

Data

P

Open
drain
Output

N

disable

Type 12

Analog output
voltage

P

N

18

OUT

N

VDD

P

Type 20

V

V

DD

Data

IN/OUT

Output
disable

DD

P

IN/OUT

N

Comparator

P

N

OUT

+
–

(Threshold voltage)

VREF

Input
enable

Data Sheet U11681EJ2V0DS00

µ

PD78P4908

5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS)

This register enables the software to avoid using part of the internal memory. The IMS can be set to establish
the same memory mapping as used in mask ROM products that have different internal memory (ROM and RAM)
configurations.

The IMS is set using 8-bit memory operation instructions.

A RESET input sets the IMS to FFH.

Figure 5-1. Internal Memory Size Select Register (IMS)

76543210

IMS IMS7 IMS6

The IMS is not contained in a mask ROM product (

IMS5

IMS4 IMS3 IMS2 IMS1 IMS0

IMS0-7

FFH

EEH

Other than
the above

µ

PD784907 or µPD784908). But the action is not affected if

Same as the PD784908
Same as the PD784907

Not to be set

the write command to the IMS is executed to the mask ROM product.

Address

0FFFCH

Memory size

µ
µ

Reset valueWR/W

FFH

Data Sheet U11681EJ2V0DS00

19

µ

PD78P4908

6. PROM PROGRAMMING

The µPD78P4908 has an on-chip 128-KB PROM device for use as program memory. When programming, set

PP and RESET pins for PROM programming mode. See 2. PIN CONFIGURATION (TOP VIEW) (2) PROM

the V

programming mode with regard to handling of other, unused pins.

6.1 OPERATION MODE

PROM programming mode is selected when +6.5 V is added to the V
low-level input is added to the RESET pin. This mode can be set to operation mode by setting the CE pin, OE pin,
and PGM pin as shown in Table 6-1 below.

In addition, the PROM contents can be read by setting read mode.

Table 6-1. PROM Programming Operation Mode

Pin RESET VPP VDD CE OE PGM D0-D7

Operation mode
Page data latch L +12.5 V +6.5 V H L H Data input
Page write H H L High impedance

DD pin, +12.5 V is added to the VPP pin, or

Byte write L H L Data input
Program verify L L H Data output
Program inhibit × H H High impedance

× LL
Read +5 V +5 V L L H Data output
Output disable L H × High impedance
Standby H ×× High impedance

Remark × = L or H

20

Data Sheet U11681EJ2V0DS00

µ

PD78P4908

(1) Read mode

Set CE to L and OE to L to set read mode.

(2) Output disable mode

Set OE to H to set high impedance for data output and output disable mode.

µ

Consequently, if several
select data output from any of the devices.

(3) Standby mode

Set CE to H to set standby mode.
In this mode, data output is set to high impedance regardless of the OE setting.

(4) Page data latch mode

At the beginning of page write mode, set CE to H, PGM to H, and OE to L to set page data latch mode.
In this mode, 1 page (4 bytes) of data are latched to the internal address/data latch circuit.

(5) Page write mode

After latching the address and data for one page (4 bytes) using page data latch mode, adding a 0.1 ms program
pulse (active, low) to the PGM pin with both CE and OE set to H causes page write to be executed. Later, setting
both CE and OE to L causes program verification to be executed.
If programming is not completed after one program pulse, the write and verify operations may be repeated X times
(where X ≤ 10).

PD78P4908 devices are connected to a data bus, the OE pins can be controlled to

(6) Byte write mode

Adding a 0.1 ms program pulse (active, low) to the PGM pin with setting CE to L and OE to H causes byte write
to be executed. Later, setting OE to L causes program verification to be executed.
If programming is not completed after one program pulse, the write and verify operations may be repeated X times
(where X ≤ 10).

(7) Program verify mode

Set CE to L, PGM to H, and OE to L to set program verify mode. Use verify mode for verification following each
write operation.

(8) Program inhibit mode

µ

Program inhibit mode is used to write to a single device when several
parallel to OE , V
Use the page write mode or byte write mode described above for each write operation. Write operations cannot
be done for devices in which the PGM pin has been set to H.

PP, and D0 to D7 pins.

PD78P4908 devices are connected in

Data Sheet U11681EJ2V0DS00

21

6.2 PROM WRITE SEQUENCE

Figure 6-1. Page Program Mode Flowchart

Start

Address = G

DD = +6.5 V, VPP = +12.5 V

V

X = 0

Latch

Address = Address + 1

Latch

Address = Address + 1

µ

PD78P4908

Address = Address + 1

Latch

Address = Address + 1

Latch

X = X + 1

0.1 ms program pulse

Verify 4 bytes

No

Pass

Address = N ?

DD = 4.0 to 5.5 V, VPP = VDD

V

Verify all bytes

Pass

Yes

All pass

Fail

Fail

No

X = 10 ?

Yes

Remark G = Start address

N = Program end address

22

Write end

Data Sheet U11681EJ2V0DS00

Defective

Figure 6-2. Page Program Mode Timing

µ

PD78P4908

A2-A16

A0, A1

D0-D7

VPP

VDD

CE

Page data latch

Hi-Z Hi-Z

Data input Data output

PP

V

VDD

VDD + 1.5

DD

V

VIH

VIL

Page program Program verify

PGM

OE

VIH

VIL

VIH

VIL

Data Sheet U11681EJ2V0DS00

23

Figure 6-3. Byte Program Mode Flowchart

Start

Address = G

DD = +6.5 V, VPP = +12.5 V

V

= 0

X

µ

PD78P4908

Address = Address + 1

Remark G = Start address

N = Program end address

= X + 1

X

0.1 ms program pulse

Verify

No

Pass

Address = N ?

V

DD = 4.0 to 5.5 V, VPP = VDD

Verify all bytes

Write end Defective

Pass

Yes

All pass

Fail

Fail

X

= 10 ?

No

Yes

24

Data Sheet U11681EJ2V0DS00

Figure 6-4. Byte Program Mode Timing

µ

PD78P4908

A0-A16

D0-D7

VPP

VDD

CE

Program

Hi-Z Hi-Z Hi-Z

V

PP

VDD

VDD + 1.5

V

DD

VIH

VIL

Data input Data output

Program verify

VIH

PGM

VIL

VIH

OE

VIL

Cautions 1. Add V

2. Do not allow V

3. Reliability problems may result if the device is inserted or pulled out while 12.5 V is applied

PP.

at V

DD before VPP, and turn off the VDD after VPP.

PP to exceed 13.5 V including overshoot.

Data Sheet U11681EJ2V0DS00

25

6.3 PROM READ SEQUENCE

Follow this sequence to read the PROM contents to an external data bus (D0 to D7).

µ

PD78P4908

(1) Set the RESET pin to low level and add 5 V to the V

PP pin. See 2. PIN CONFIGURATION (TOP VIEW) (2) PROM

programming mode with regard to handling of other, unused pins.

(2) Add 5 V to the V

DD and VPP pins.

(3) Input the data address to be read to pins A0 to A16.
(4) Set read mode.
(5) Output the data to pins D0 to D7.

Figure 6-5 shows the timing of steps (2) to (5) above.

Figure 6-5. PROM Read Timing

A0-A16

CE (input)

OE (input)

Address input

D0-D7

Hi-Z Hi-Z

Data output

7. SCREENING ONE-TIME PROM PRODUCTS

NEC cannot execute a complete test of one-time PROM products (µPD78P4908GF-3BA) due to their structure
before shipment. It is recommended that you screen (verify) PROM products after writing necessary data into them
and storing them at 125°C for 24 hours.

26

Data Sheet U11681EJ2V0DS00

µ

PD78P4908

8. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

Parameter Symbol Conditions Rating Unit

Supply voltage VDD –0.3 to +7.0 V

AVDD –0.3 to VDD + 0.3 V
AVSS –0.3 to +0.3 V

Input voltage VI1 For pins other than VPP, A9 –0.3 to VDD + 0.3 V

VI2 VPP, A9 –0.3 to +13.5 V
Analog input voltage VAN AVSS – 0.3 to AVREF1 + 0.3 V
Output voltage VO –0.3 to VDD + 0.3 V
Output low current I OL One pin 10 mA

Total for the P00-P07, P30- 50 mA
P37, P54-P57, P60-P67, and
P100-P107 pins

Total for the P10-P17, P40- 50 mA
P47, P50-P53, P70-P77,
P90-P97, PWM0, PWM1,
and TX pins

Output high current IOH One pin –6 mA

Total for the P00-P07, P30- –30 mA
P37, P54-P57, P60-P67, and
P100-P107 pins

Total for the P10-P17, P40- –30 mA
P47, P50-P53, P70-P77,
P90-P97, PWM0, PWM1,
and TX pins

A/D converter reference input AVREF1 –0.3 to VDD + 0.3 V
voltage

Operating ambient temperature TA –40 to +85 °C
Storage temperature Tstg –65 to +150 °C

Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to

the product; if the rated value of any of the parameters in the above table is exceeded, even
momentarily, the quality of the product may deteriorate. Always use the product within its rated
values.

Remark Unless otherwise stated, the characteristics of a dual-function pin are the same as those of a port pin.

Data Sheet U11681EJ2V0DS00

27

OPERATING CONDITIONS

• Operating ambient temperature (T

A): –40 °C to +85 °C

• Power supply voltage and clock cycle time: See Figure 8-1.

• Internal regulator operation selected (REGOFF pin: low level)

Figure 8-1. Power Supply Voltage and Clock Cycle Time

10,000

4,000

µ

PD78P4908

CAPACITANCE (T

Parameter
Input capacitance
Output capacitance
I/O capacitance

1,000

159
100

79

Clock cycle time tCYK [ns]

10

01234567

A = 25 °C, VDD = VSS = 0 V)

Symbol

C

I

CO
CIO

f = 1 MHz
0 V on pins other than measured pins

Guaran­teed
opera­ting
range

Power supply voltage [V]

Conditions

MIN. TYP. MAX.

15
15
15

Unit

pF
pF
pF

28

Data Sheet U11681EJ2V0DS00

µ

PD78P4908

MAIN OSCILLATOR CHARACTERISTICS (TA = –40 °C to +85 °C, VDD = 4.0 to 5.5 V, VSS = 0 V)

Parameter

Oscillator frequency

fXX

Symbol

Conditions

Ceramic or crystal resonator

MIN.

2

MAX.

12.58

Caution When using the clock generator, run wires according to the following rules to avoid effects such

as stray capacitance:

• Minimize the wiring length.

• Never cause the wires to cross other signal lines.

• Never cause the wires to run near a line carrying a large varying current.

• The grounding point of the capacitor of the oscillator circuit must always be the same potential

SS1. Never connect the capacitor to a ground pattern carrying a large current.

as V

• Never extract a signal from the oscillator.

Remark Connect a 12.582912 or 6.291456 MHz oscillator to operate the internal clock timer with the main clock.

CLOCK OSCILLATOR CHARACTERISTICS (T

Parameter
Oscillator frequency
Oscillation settling time

Oscillation hold voltage
Watch timer operating

voltage

Symbol
fXT
tSXT

VDDXT
VDDW

Ceramic or crystal resonator
VDD = 4.5 to 5.5 V

A = –40 °C to +85 °C, VDD = 4.0 to 5.5 V, VSS = 0 V)

Conditions

MIN.

32

4.0

4.0

TYP.

32.768

1.2

MAX.

35

2

10

5.5

5.5

Unit

MHz

Unit
kHz

s

s
V
V

Data Sheet U11681EJ2V0DS00

29

µ

DC CHARACTERISTICS (TA = –40 °C to +85 °C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V) (1/2)

PD78P4908

Parameter

Input low voltage

Input high voltage

Output low voltage

Output high voltage

Note 5

Symbol

VIL1

VIL2
VIL3

VIH1

VIH2
VIH3

VOL1

VOL2

VOH1

VOH2

Conditions

For pins other than those described in

Notes 1 and 2

For pins described in Note 1
VDD = 4.5 to 5.5 V

For pins described in Note 2
For pins other than those described in

Notes 1 and 2

For pins described in Note 1
V

DD = 4.5 to 5.5 V

For pins described in Note 2
IOL = 20 µA
IOL = 100 µA
IOL = 2 mA
IOL = 8 mA

For pins described in Note 4
VDD = 4.5 to 5.5 V

IOH = -20 µA
IOH = -100 µA
IOH = -2 mA
VDD = 4.5 to 5.5 V

IOH = -5 mA
For pins described in Note 3

MIN.
–0.3

–0.3
–0.3

DD

0.7 V

0.8 VDD

2.2

VDD – 0.1
VDD – 0.2
VDD – 1.0
VDD – 2.4

TYP. MAX.

0.3 V

0.2 VDD
+0.8

VDD + 0.3

DD + 0.3

V
VDD + 0.3

0.1

0.2

0.4

1.0

Unit

DD

V

V
V

V

V
V

V
V
V
V

V
V
V
V

Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,

P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3,
P107/SO3, XT1, XT2

2. P40/AD0-P47/AD7, P50/A8-P57/A15, P60/A16-P67/REFRQ/HLDAK, P00-P07

3. P00-P07

4. P10-P17, P40/AD0-P47/AD7, P50/A8-P57/A15

5. Other than pull-up resistors

30

Data Sheet U11681EJ2V0DS00

µ

PD78P4908

DC CHARACTERISTICS (TA = –40 °C to +85 °C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V) (2/2)

Parameter

Input leakage current

Output leakage current
V

DD supply current

Pull-up resistor

Note

Symbol

LI1

I

ILI2
ILO
IDD1

IDD2

IDD3

RL

Conditions

0 V ≤ VI ≤ VDD For pins other than

X1 and XT1
X1, XT1

0 V ≤ V

O ≤ VDD

Operation mode fXX = 12.58 MHz

VDD = 4.5 to 5.5 V
fXX = 6.29 MHz
VDD = 4.0 to 5.5 V

HALT mode fXX = 12.58 MHz

VDD = 4.5 to 5.5 V
fCLK = fXX/8
(STBC = B1H)
Peripheral operation
stops.

fXX = 6.29 MHz
VDD = 4.0 to 5.5 V
fCLK = fXX/8
(STBC = 31H)
Peripheral operation
stops.

IDLE mode fXX = 12.58 MHz

VDD = 4.5 to 5.5 V
fXX = 6.29 MHz
VDD = 4.0 to 5.5 V

VI = 0 V

MIN.

15

TYP.

20

10

5.2

2.6

2.4

1.8

MAX.

±10

±20
±10

40

20

10.4

5.2

4.8

3.6

80

Unit

µ

µ
µ

mA

mA

mA

mA

mA

mA

kΩ

A

A
A

Note These values are valid when the internal regulator is ON (REGOFF pin = low level). They do not include

DD and AVREF1 currents.

the AV

Data Sheet U11681EJ2V0DS00

31

AC CHARACTERISTICS (TA = –40°C to +85°C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)

(1) Read/write operation

µ

PD78P4908

Parameter

Address setup time
(to ASTB↓)

ASTB high-level width
Address hold time (to ASTB↓)
Address hold time (to RD↑)
Delay from address to RD↓
Address float time (to RD↓)
Delay from address to data

input
Delay from ASTB↓ to data input
Delay from RD↓ to data input
Delay from ASTB↓ to RD↓
Data hold time (to RD↑)
Delay from RD↑ to address

active
Delay from RD↑ to ASTB↑
RD low-level width
Delay from address↓ to WR↓
Address hold time (to WR↑)
Delay from ASTB↓ to data

output
Delay from WR↓ to data output
Delay from ASTB↓ to WR↓
Data setup time (to WR↑)
Data hold time (to WR↑)
Delay from WR↑ to ASTB↑
WR low-level width

Symbol

tSAST

tWSTH
tHSTLA
tHRA
tDAR
tFRA
tDAID

tDSTID
tDRID
tDSTR
tHRID
tDRA

tDRST
tWRL
tDAW
tHWA
tDSTOD

tDWOD
tDSTW
tSODWR
tHWOD
tDWST
tWWL

Conditions

VDD = 5.0 V (0.5 + a)T – 11

VDD = 5.0 V (0.5 + a)T – 17
VDD = 5.0 V 0.5T – 19
VDD = 5.0 V 0.5T – 14
VDD = 5.0 V (1 + a)T – 5

VDD = 5.0 V (2.5 + a + n)T – 37

DD = 5.0 V (2 + n)T – 35

V
VDD = 5.0 V (1.5 + n)T – 40
VDD = 5.0 V 0.5T – 9

VDD = 5.0 V 0.5T – 2

VDD = 5.0 V 0.5T – 9
VDD = 5.0 V (1.5 + n)T – 25
VDD = 5.0 V (1 + a)T – 5
VDD = 5.0 V 0.5T – 14
VDD = 5.0 V 0.5T + 15

V

DD = 5.0 V 0.5T – 9

VDD = 5.0 V (1.5 + n)T – 20
VDD = 5.0 V 0.5T – 14
VDD = 5.0 V 0.5T – 9
VDD = 5.0 V (1.5 + n)T – 25

MIN.

29

23
21
26
74

0

31

0

38

31
94
74
26

31
99
26
31
94

MAX.

400

283
238

55

15

Unit

ns

ns
ns
ns
ns
ns
ns

ns
ns
ns
ns
ns

ns
ns
ns
ns
ns

ns
ns
ns
ns
ns
ns

Remark T: tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.)

a: 1 during address wait, otherwise, 0
n: Number of wait states (n ≥ 0)

32

Data Sheet U11681EJ2V0DS00

(2) External wait timing

µ

PD78P4908

Parameter

Delay from address to WAIT↓
input

Delay from ASTB↓ to WAIT↓
input

Hold time from ASTB↓ to WAIT
Delay from ASTB↓ to WAIT↑
Delay from RD↓ to WAIT↓

input
Hold time from RD↓ to WAIT
Delay from RD↓ to WAIT↑
Delay from WAIT↑ to data

input
Delay from WAIT↑ to RD↑
Delay from WAIT↑ to WR↑
Delay from WR↓ to WAIT↓

input
Hold time from WR↓ to WAIT
Delay from WR↓ to WAIT↑

Symbol

tDAWT

tDSTWT

tHSTWT
tDSTWTH
tDRWTL

tHRWT
tDRWTH
tDWTID

tDWTR
tDWTW
tDWWTL

tHWWT
tDWWTH

Conditions

VDD = 5.0 V (2 + a)T – 40

VDD = 5.0 V 1.5T – 40

VDD = 5.0 V (0.5 + n)T + 5
VDD = 5.0 V (1.5 + n)T – 40
VDD = 5.0 V T – 40

VDD = 5.0 V nT + 5
VDD = 5.0 V (1 + n)T – 40
V

DD = 5.0 V 0.5T – 5

VDD = 5.0 V 0.5T
VDD = 5.0 V 0.5T
VDD = 5.0 V T – 40

VDD = 5.0 V nT + 5
VDD = 5.0 V (1 + n)T – 40

MIN.

124

84

40
40

84

MAX.

198

79

238

39

198

35

39

198

Unit

ns

ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns

Remark T: t

a: 1 during address wait, otherwise, 0
n: Number of wait states (n ≥ 0)

CYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.)

Data Sheet U11681EJ2V0DS00

33

(3) Bus hold timing

µ

PD78P4908

Parameter
Delay from HLDRQ↑ to float
Delay from HLDRQ↑ to HLDAK↑
Delay from float to HLDAK↑
Delay from HLDRQ↓ to HLDAK↓
Delay from HLDRQ↓ to active

Remark T: t

CYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.)

a: 1 during address wait, otherwise, 0
n: Number of wait states (n ≥ 0)

(4) Refresh timing

Parameter
Random read/write cycle time
REFRQ low-level pulse width
Delay from ASTB↓ to REFRQ
Delay from RD↑ to REFRQ
Delay from WR↑ to REFRQ
Delay from REFRQ↑ to ASTB
REFRQ high-level pulse width

Symbol
tFHQC
tDHQHHAH
tDCFHA
tDHQLHAL
tDHAC

Symbol
tRC
tWRFQL
tDSTRFQ
tDRRFQ
tDWRFQ
tDRFQST
tWRFQH

Conditions
VDD = 5.0 V (2 + 4 + a + n)T + 50
VDD = 5.0 V (3 + 4 + a + n)T + 30
V

DD = 5.0 V T + 30

VDD = 5.0 V 2T + 40
VDD = 5.0 V T – 20

Conditions
VDD = 5.0 V 3T
VDD = 5.0 V 1.5T – 25
VDD = 5.0 V 0.5T – 9
VDD = 5.0 V 1.5T – 9
V

DD = 5.0 V 1.5T – 9

VDD = 5.0 V 0.5T – 9
VDD = 5.0 V 1.5T – 25

MIN.

59

MIN.

238

94

31
110
110

31

94

MAX.

765
825
109
199

MAX.

Unit

ns
ns
ns
ns
ns

Unit

ns
ns
ns
ns
ns
ns
ns

Remark T: t

CYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.)

34

Data Sheet U11681EJ2V0DS00

SERIAL OPERATION (TA = –40 °C to +85 °C, VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)

(1) CSI, CSI3

µ

PD78P4908

Parameter

Serial clock cycle time
(SCK0, SCK3)

Serial clock low-level width
(SCK0, SCK3)

Serial clock high-level width
(SCK0, SCK3)

Setup time for SI0, SI3
(to SCK0, SCK3↑)

Hold time for SI0, SI3
(to SCK0, SCK3↑)

Output delay time for SO0,
SO3 (to SCK0, SCK3↓)

Output hold time for SO0,
SO3 (to SCK0, SCK3↑)

Symbol

tCYSK0

tWSKL0

tWSKH0

tSSSK0

tHSSK0

tDSBSK1

tDSBSK2

tHSBSK

Conditions

Input fCLK = fXX

Other than fCLK = fXX

Output Other than f CLK = fXX/8

fCLK = fXX/8

Input fCLK = fXX

Other than fCLK = fXX

Output Other than f CLK = fXX/8

fCLK = fXX/8

Input fCLK = fXX

Other than fCLK = fXX

Output Other than f CLK = fXX/8

f

CLK = fXX/8

External clock
Internal clock
CMOS push-pull output External clock

Internal clock

Open-drain output External clock
RL = 1 kΩ

When data is transferred

Internal clock

MIN.
8/fXX

4/fCLK

8/fXX

16/fXX

4/fXX – 40

2/fCLK – 40

4/fXX – 40
8/fXX – 40
4/fXX – 40

2/fCLK – 40

4/f

XX – 40

8/fXX – 40

80

1/fCLK + 80

80

0
0
0
0

0.5tCYSK0 – 40

MAX.

1/fCLK + 150

150

1/fCLK + 400

400

Unit

ns
ns
ns
ns
ns

µ

ns

µ

ns

ns

ns
ns
ns
ns
ns

s

s

Remarks 1. The values in this table are those when f

CLK: System clock frequency (selectable from fXX, fXX/2, fXX/4, and fXX/8 by the standby control

2. f
register (STBC))

XX : Oscillation frequency (fXX = 12.58 MHz or fXX = 6.29 MHz)

3. f

Data Sheet U11681EJ2V0DS00

XX = 12.58 MHz, CL is 100 pF.

35

(2) IOE1, IOE2 (TA = –40 °C to +85 °C, V DD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)

µ

PD78P4908

Parameter

Serial clock cycle time
(SCK1, SCK2)

Serial clock low-level width
(SCK1, SCK2)

Serial clock high-level width
(SCK1, SCK2)

Setup time for SI1 and SI2
(to SCK1, SCK2↑)

Hold time for SI1 and SI2
(to SCK1, SCK2↑)

Output delay time for SO1 and
SO2 (to SCK1, SCK2↓)

Output hold time for SO1 and
SO2 (to SCK1, SCK2↑)

Symbol

tCYSK1

tWSKL1

tWSKH1

tSSSK1

tHSSK1

tDSOSK

tHSOSK

Conditions

Input VDD = 4.5 to 5.5 V

Output Internal, divided by 8
Input V

Output Internal, divided by 8
Input VDD = 4.5 to 5.5 V

Output Internal, divided by 8

When data is transferred

DD = 4.5 to 5.5 V

Remarks 1. The values in this table are those when C

2. T: Serial clock cycle set by software. The minimum value is 8/f

L is 100 pF.

MIN.

640

1,280

280
600

0.5T – 40
280
600

0.5T – 40

40

40

0.5t

CYSK1 – 40

XX.

MAX.

T

0

50

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns

ns

ns

(3) UART, UART2 (T

Parameter

ASCK clock input cycle time

ASCK clock low-level width

ASCK clock high-level width

A = –40 °C to +85 °C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)

Symbol

tCYASK

tWASKL

tWASKH

Conditions

VDD = 4.5 to 5.5 V

VDD = 4.5 to 5.5 V

DD = 4.5 to 5.5 V

V

MIN.

160
320

65

120

65

120

MAX.

Unit

ns
ns
ns
ns
ns
ns

36

Data Sheet U11681EJ2V0DS00

µ

PD78P4908

CLOCK OUTPUT OPERATION (TA = –40°C to +85°C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)

Parameter
CLKOUT cycle time
CLKOUT low-level width

CLKOUT high-level width

CLKOUT rise time

CLKOUT fall time

Symbol
tCYCL
tCLL

tCLH

tCLR

tCLF

Conditions
nT
VDD = 4.5 to 5.5 V, 0.5T – 10

0.5T – 20
VDD = 4.5 to 5.5 V, 0.5T – 10

0.5T – 20

4.5 V ≤ VDD < 5.5 V

4.0 V ≤ VDD < 4.5 V

4.5 V ≤ VDD < 5.5 V

4.0 V ≤ VDD < 4.5 V

Remark n: Dividing ratio set by software in the CPU (n = 1, 2, 4, 8, and 16)

CYK (system clock cycle time)

T: t

OTHER OPERATIONS (T

Parameter
NMI low-level width
NMI high-level width
INTP0 low-level width
INTP0 high-level width
Low-level width for INTP1-

INTP3 and CI
High-level width for INTP1-

INTP3 and CI
Low-level width for INTP4 and

INTP5
High-level width for INTP4 and

INTP5
RESET low-level width
RESET high-level width

A = –40 °C to +85 °C, VDD = AVDD = 4.0 to 5.5 V, AV SS = VSS = 0 V)

Note

Symbol
tWNIL
tWNIH
tWIT0L
tWIT0H
tWIT1L

tWIT1H

tWIT2L

tWIT2H

tWRSL
tWRSH

Conditions

MIN.

79
30
20
30
20

MIN.

10

10
4 tCYSMP
4 tCYSMP
4 tCYCPU

4 tCYCPU

10

10

10

10

MAX.

32,000

10
20
10
20

MAX.

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns

Unit

µ
µ

ns
ns
ns

ns

µ

µ

µ
µ

s
s

s

s

s
s

Note Use the RESET low-level width to ensure the lapse of the oscillation settling time when the power is applied.

Remark t

CYSMP: Sampling clock set by software
CYCPU: CPU operation clock set by software in the CPU

t

Data Sheet U11681EJ2V0DS00

37

µ

PD78P4908

A/D CONVERTER CHARACTERISTICS (TA = –40 °C to +85 °C, VDD = AVDD = AVREF1 = 4.0 to 5.5 V, AVSS = VSS = 0 V)

Parameter
Resolution
Total error

Quantization error
Conversion time

Sampling time

Analog input impedance
AV
AVDD power supply

voltage

Note

REF1 impedance

Symbol

tCONV

tSAMP

RAN
RREF1
AIDD1
AIDD2

IEAD = 00H FR = 0

IEAD = 01H VDD = 4.5 to 5.5 V

FR = 1 120/fCLK
FR = 0 240/fCLK
FR = 1 18/fCLK
FR = 0 36/fCLK

CS = 1
CS = 0, STOP mode

Conditions

FR = 1

MIN.

8

9.5

19.1

1.4

2.9

3

TYP.

1

1,000

10

2.0

1.0

MAX.

0.6

1.5

2.2

±1/2

480
960

72

144

5.0
20

Unit

bit

%
%
%

LSB

µ

s

µ

s

µ

s

µ

s

MΩ

kΩ

mA

µ

A

Note Quantization error is not included. This parameter is indicated as the ratio to the full-scale value.

Caution To execute the conversion by the A/D converter set port 7, multiplexed with the A/D input lines,

to output mode to prevent data from being inverted.

Remark f

CLK: System clock frequency (selectable from fXX, fXX/2, fXX/4, and fXX/8 by the standby control register

(STBC))

IEBus CONTROLLER CHARACTERISTICS (TA = –40°C to +85°C, VDD = AVDD = AVREF1 = 4.5 to 5.5 V, AVSS = VSS = 0 V)

Parameter

IEBus standard
frequency

Driver delay time (delay from
TX output to bus line)

Receiver delay time
(delay from bus line to
RX output)

Transmission delay on
bus

Note 1

Note 2

Note 2

Note 2

Symbol

fS

tDTX

tDRX

tDBUS

Conditions

Transfer speed: mode 1

C

L = 50 pF

Note 3

MIN.

6.20

TYP.

6.29

MAX.

6.39

1.5

0.7

0.85

Unit

MHz

µ

s

µ

s

µ

s

Notes 1. The value conforms to the IEBus standard. The IEBus controller is operable within the range of the

oscillator frequency of oscillator characteristics.

2. The value is measured when IEBus system clock: f

L is the load capacitance of TX output line.

3. C

X = 6.29 MHz.

38

Data Sheet U11681EJ2V0DS00

DATA RETENTION CHARACTERISTICS (TA = –40 °C to +85 °C)

µ

PD78P4908

Parameter
Data retention voltage
Data retention current

VDD rise time
VDD fall time
VDD hold time

(to STOP mode setting)
STOP clear signal input time
Oscillation settling time

Input low voltage
Input high voltage

Symbol
VDDDR
IDDDR

tRVD
tFVD
tHVD

tDREL
tWAIT

VIL
VIH

Conditions
STOP mode
STOP mode V

Crystal resonator
Ceramic resonator
Specific pins

DDDR = 2.5 V, AVREF =

0 V
VDDDR = 4.0 to 5.5 V,

AVREF1 = 0 V

Note 2

Note 1

Note 1

Notes 1. Valid when input voltages to the pins described in Note 2 satisfy V

2. RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,

P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, and
P107/SO3 pins

MIN.

2.5

200
200

0.9 V

0

0

30

5
0

DDDR

TYP.

2

10

IL or VIH in the above table.

MAX.

5.5

0.1 V
VDDDR

10

50

DDDR

Unit

V

µ

µ

µ
µ

ms

ms
ms
ms

V
V

A

A

s
s

AC TIMING TEST POINTS

V

DD – 1 V

0.45 V

0.8 VDD or 2.2 V

0.8 V

0.8 VDD or 2.2 V

Test points

0.8 V

Data Sheet U11681EJ2V0DS00

39

TIMING WAVEFORM

(1) Read operation

ASTB

tWSTH

µ

PD78P4908

A8-A19

AD0-AD7

RD

(2) Write operation

ASTB

tSAST

tWSTH

tSAST

tDAR

tDSTID

tHSTLA

tDAID tHRA

tDSTR

tHSTLA

tFRA

tDRID

tWRL

tDSTOD

tDRST

tHRID

tDRA

tDWST

A8-A19

AD0-AD7

WR

tDSTW tHWOD

tDAW

tDWOD

tSODWR

tWWL

tHWA

40

Data Sheet U11681EJ2V0DS00

HOLD TIMING

ASTB

A8-A19

AD0-AD7

WR

WAIT

tDSTWT

tHSTWTH

tDSTWTH

tDAWT

tDWTW

tDWWTL

tHWWT

tDWWTH

ASTB, A8-A19,
AD0-AD7, RD, WR

HLDRQ

tFHQC

tDCFHA

tDHAC

µ

PD78P4908

tDHQHHAH

HLDAK

EXTERNAL WAIT SIGNAL INPUT TIMING

(1) Read operation

ASTB

tDSTWT

A8-A19

AD0-AD7

tDAWT tDWTID

RD

WAIT

tDSTWTH

tHSTWTH

tDRWTL

tDHQLHAL

tDWTR

(2) Write operation

tHRWT

tDRWTH

Data Sheet U11681EJ2V0DS00

41

REFRESH TIMING WAVEFORM

(1) Random read/write cycle

tRC

ASTB

WR

RD

(2) When refresh memory is accessed for a read and write at the same time

ASTB

RD, WR

µ

PD78P4908

tRCtRC tRC tRC

REFRQ

(3) Refresh after a read

ASTB

RD

REFRQ

(4) Refresh after a write

ASTB

tDSTRFQ tDRFQST

tWRFQL

tWRFQH

tDRRFQ

tDRFQST

tWRFQL

42

tDRFQST

WR

tDWRFQ

REFRQ

tWRFQL

Data Sheet U11681EJ2V0DS00

SERIAL OPERATION (CSI, CSI3)

SCK0, SCK3

SI0, SI3

SO0, SO3

Output data

Input data

t

SSSK0tHSSK0

t

DSBSK1

t

WSKL0

t

WSKH0

t

HSBSK1

t

CYSK0

SERIAL OPERATION (IOE1, IOE2)

SCK1, SCK2

t

WSKL1

t

CYSK1

t

WSKH1

SSSK1tHSSK1

t

µ

PD78P4908

SI1, SI2

SO1, SO2

SERIAL OPERATION (UART, UART2)

ASCK,
ASCK2

CLOCK OUTPUT TIMING

CLKOUT

t

DSOSK

Output data

tWASKH tWASKL

tCYASK

tCLH tCLL

tCLFtCLR

tCYCL

t

HSOSK

Input data

Data Sheet U11681EJ2V0DS00

43

INTERRUPT REQUEST INPUT TIMING

NMI

INTP0

tWNIH tWNIL

tWIT0H tWIT0L

tWIT1H tWIT1L

µ

PD78P4908

INTP1-INTP3

CI,

INTP4, INTP5

RESET INPUT TIMING

RESET

tWIT2H tWIT2L

tWRSH tWRSL

44

Data Sheet U11681EJ2V0DS00

EXTERNAL CLOCK TIMING

tWXH tWXL

X1

DATA RETENTION CHARACTERISTICS

STOP mode setting

tCYX

µ

PD78P4908

tXFtXR

VDD

tHVD tFVD tRVD

RESET

NMI

(Clearing by falling edge)

NMI

(Clearing by rising edge)

VDDDR

tDREL

tWAIT

Data Sheet U11681EJ2V0DS00

45

DC PROGRAMMING CHARACTERISTICS (TA = 25°C ±5°C, VSS = 0 V)

µ

PD78P4908

Parameter

High-level input
voltage

Low-level input
voltage

Input leakage current
High-level output

voltage
Low-level output

voltage
Output leakage

current
VDDP supply voltage

VPP supply voltage

VDDP supply current

VPP supply current

Symbol

VIH

VIL

ILIP

VOH

VOL

ILO

VDDP

VPP

IDD

IPP

Symbol

VIH

VIL

ILI

VOH

VOL

–

VCC

VPP

IDD

IPP

Note 1

Conditions

0 ≤ VI ≤ VDDP
IOH = –400 µA

IOL = 2.1 mA

0 ≤ VO ≤ VDDP, OE = VIH

Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode

Note 2

MIN.

2.2

–0.3

2.4

6.25

4.5

12.2

TYP.

6.5

5.0

12.5

VPP = VDDP

10
10

5

1.0

MAX.

VDDP + 0.3

+0.8

±10

0.45

±10

6.75

5.5

12.8

40
40
50

100

Unit

V

V

µ

V

V

µ

V
V
V

V
mA
mA
mA

µ

A

A

A

Notes 1. Symbols for the corresponding

2. The V

DDP represents the VDD pin as viewed in the programming mode.

µ

PD27C1001A

46

Data Sheet U11681EJ2V0DS00

AC PROGRAMMING CHARACTERISTICS (TA = 25°C ±5°C, VSS = 0 V)

PROM Write Mode (Page Program Mode)

µ

PD78P4908

Parameter
Address setup time
CE set time
Input data setup time
Address hold time

Input data hold time
Output data hold time
VPP setup time
VDDP setup time
Initial program pulse width
OE set time
Valid data delay time from OE
OE pulse width in the data latch
PGM setup time
CE hold time
OE hold time

Symbol

tVDS

tPGMS

Note 1

tAS

tCES

tDS

tAH
tAHL
tAHV

tDH

tDF
tVPS

Note 2

tPW
tOES

tOE

tLW

tCEH
tOEH

Conditions Unit

MIN.

2
2
2
2
2
0
2
0
2
2

0.095
2

1
2
2
2

TYP.

0.1

1

MAX.

130

0.105

2

µ
µ
µ
µ
µ
µ
µ

ns

µ
µ

ms

µ

ns

µ
µ
µ
µ

s
s
s
s
s
s
s

s
s

s

s
s
s
s

Notes 1. These symbols (except t

µ

2. For

PD27C1001A, read tVDS as tVCS.

VDS) correspond to those of the corresponding

µ

PD27C1001A.

Data Sheet U11681EJ2V0DS00

47

PROM Write Mode (Byte Program Mode)

µ

PD78P4908

Parameter
Address setup time
CE set time
Input data setup time
Address hold time
Input data hold time
Output data hold time
VPP setup time
VDDP setup time
Initial program pulse width
OE set time
Valid data delay time from OE

Notes 1. These symbols (except t

µ

2. For

PD27C1001A, read tVDS as tVCS.

PROM Read Mode

Parameter

Data output time from address
Delay from CE ↓ to data output

Delay from OE ↓ to data output
Data hold time to OE↑ or CE↑

Data hold time to address

Note 2

Note 1

Symbol

tAS

tCES

tDS
tAH
tDH

tDF

tVPS

Note 2

tVDS

tPW

tOES

tOE

VDS) correspond to those of the corresponding

Note 1

Symbol

tACC

tCE
tOE
tDF
tOH

Conditions MAX.

Conditions

CE = OE = VIL
OE = VIL
CE = VIL
CE = VIL or OE = VIL
CE = OE = VIL

MIN.

2
2
2
2
2
0
2
2

0.095
2

MIN.

0
0

TYP.

0.1

1

µ

PD27C1001A.

TYP.

1
1

130

0.105

2

MAX.

200

2
2

60

Unit

µ
µ
µ
µ
µ

ns

µ
µ

ms

µ

ns

Unit

ns

µ
µ

ns
ns

s
s
s
s
s

s
s

s

s
s

Notes 1. These symbols correspond to those of the corresponding

DF is the time measured from when either OE or CE reaches VIH, whichever is faster.

2. t

µ

PD27C1001A.

48

Data Sheet U11681EJ2V0DS00

PROM Write Mode Timing (Page Program Mode)

Page data latch Page program Program verify

A2-A16

µ

PD78P4908

VPP

VDDP

CE

PGM

OE

A0, A1

D0-D7

V

VDDP

VDDP + 1.5

VDDP

VIH

VIL

VIH

VIL

VIH

VIL

tAS tAHL

tDS tDH

Hi-Z Hi-ZHi-Z

tVPS Data input

PP

tVDS

tLW

tPGMS

tPW

tCEH

tCES

tOE

tAHV

tDF

Data
output

tAH

tOEH

tOES

Data Sheet U11681EJ2V0DS00

49

PROM Write Mode Timing (Byte Program Mode)

Program Program verify

A0-A16

µ

PD78P4908

D0-D7

V

VPP

VDDP

VDDP + 1.5

VDDP

VDDP

CE

PGM

OE

Cautions 1. V

2. V

3. Plugging in or out the board with the V
reliability.

tAS

Hi-Z Hi-ZHi-Z

tDS

PP

Data input

tDS

tVPS

tVDS

VIH

VIL

tCES

tPW

VIH

VIL

tOES tOE

VIH

VIL

DDP must be applied before VPP, and must be cut after VPP.
PP including overshoot must not exceed 13.5 V.

PP pin supplied with 12.5 V may adversely affect its

tDF

Data output

tAHtDH

PROM Read Mode Timing

A0-A16

CE

OE

D0-D7

Notes 1. For reading within t

DF is the time measured from when either OE or CE reaches VIH, whichever is faster.

2. t

50

Valid address

tCE

Note 2

Note 1

tACC

Hi-Z Hi-Z

ACC, the delay of the OE input from falling edge of CE must be within tACC-tOE.

Note 1

tOE

Data output

Data Sheet U11681EJ2V0DS00

tOH

tDF

9. PACKAGE DRAWING

100PIN PLASTIC QFP (14x20)

µ

PD78P4908

A
B

80

81

100

1

51

30

50

31

F

G

H

M

I

J

P

N

NOTE

Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.

Remark The shape and material of the ES version are the same

as those of the corresponding mass-produced product.

CD

K

M

L

detail of lead end

S

Q

ITEM MILLIMETERS INCHES

A 23.6±0.4 0.929±0.016
B 20.0±0.2 0.795

C 14.0±0.2 0.551
D 17.6±0.4 0.693±0.016

F 0.8 0.031
G 0.6 0.024

H 0.30±0.10 0.012

I 0.15 0.006
J 0.65 (T.P.) 0.026 (T.P.)

K 1.8±0.2 0.071

L 0.8±0.2 0.031

M 0.15 0.006
N 0.10 0.004

P 2.7±0.1 0.106
Q 0.1±0.1 0.004±0.004

R5°±5° 5°±5°
S 3.0 MAX. 0.119 MAX.

R

+0.10
–0.05

P100GF-65-3BA1-3

+0.009
–0.008

+0.009
–0.008

+0.004
–0.005

+0.008
–0.009

+0.009
–0.008

+0.004
–0.003

+0.005
–0.004

Data Sheet U11681EJ2V0DS00

51

µ

PD78P4908

10. RECOMMENDED SOLDERING CONDITIONS

The conditions listed below shall be met when soldering the µPD78P4908.
For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting

Technology Manual (C10535E).

Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under

different conditions.

Table 10-1. Soldering Conditions for Surface-Mount Devices

µ

PD78P4908GF-3BA: 100-pin plastic QFP (14 × 20 mm)

Soldering process

Infrared ray reflow

VPS

Wave soldering

Partial heating method

Soldering conditions

Peak package's surface temperature: 235°C
Reflow time: 30 seconds or less (210°C or more)
Maximum allowable number of reflow processes: 2
Exposure limit: 7 days
afterward)

Peak package's surface temperature: 215°C
Reflow time: 40 seconds or less (200°C or more)
Maximum allowable number of reflow processes: 2
Exposure limit: 7 days
afterward)

Solder temperature: 260°C or less
Flow time: 10 seconds or less
Number of flow processes: 1

Preheating temperature: 120°C MAX. (measured on the package
surface)

Exposure limit: 7 days
afterward)

Terminal temperature: 300°C or less
Heat time: 3 seconds or less (for one side of a device)

Note

(20 hours of pre-baking is required at 125°C

Note

(20 hours of pre-baking is required at 125°C

Note

(20 hours of pre-baking is required at 125°C

Symbol

IR35-207-2

VP15-207-2

WS60-207-1

–

Note Maximum number of days during which the product can be stored at a temperature of 25°C and a relative

humidity of 65% or less after dry-pack package is opened.

Caution Do not apply two or more different soldering methods to one chip (except for partial heating

method for terminal sections).

52

Data Sheet U11681EJ2V0DS00

APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for system development using the µPD78P4908.
See also (5) Notes on using development tools.

(1) Language processing software

RA78K4 Assembler package for all 78K/IV series models
CC78K4 C compiler package for all 78K/IV series models
DF784908 Device file for µPD784908 subseries models
CC78K4-L C compiler library source file for all 78K/IV series models

(2) PROM write tools

PG-1500 PROM programmer
PA-78P4908GF Programmer adapter, connects to PG-1500
PG-1500 controller Control program for PG-1500

(3) Debugging tools

µ

PD78P4908

• When using the in-circuit emulator IE-78K4-NS

IE-78K4-NS In-circuit emulator for all 78K/IV series models
IE-70000-MC-PS-B Power supply unit for IE-78K4-NS

IE-70000-98-IF-C Interface adapter when the PC-9800 series computer (other than a notebook)

is used as the host machine (C bus compatible)

IE-70000-CD-IF-A PC card and interface cable when a notebook is used as the host machine

(PCMCIA socket compatible)

IE-70000-PC-IF-C Interface adapter when the IBM PC/ATTM compatible is used as the host

machine (ISA compatible)
IE-7000-PCI-IF Adapter when a computer with a PCI bus as the host machine
IE-784908-NS-EM1
NP-100GF
EV-9200GF-100 Socket for mounting on target system board made for 100-pin plastic QFP

ID78K4-NS Integrated debugger for IE-78K4-NS
SM78K4 System simulator for all 78K/IV series models
DF784908 Device file for µPD784908 subseries models

Note

Note

Emulation board for evaluating µPD784908 subseries models

Emulation probe for 100-pin plastic QFP (GF-3BA type)

(GF-3BA type). Used in LCC mode.

Note Under development

Data Sheet U11681EJ2V0DS00

53

µ

PD78P4908

• When using the in-circuit emulator IE-784000-R

IE-784000-R In-circuit emulator for all 78K/IV series models
IE-70000-98-IF-C Interface adapter when the PC-9800 series computer (other than a notebook)

is used as the host machine (C bus compatible)

IE-70000-PC-IF-C Interface adapter when the IBM PC/AT compatible is used as the host

machine (ISA bus compatible)
IE-7000-PCI-IF Adapter when a computer with a PCI bus as the host machine
IE-78000-R-SV3 Interface adapter and cable when the EWS is used as the host machine
IE-784908-NS-EM1 Emulation board for evaluating µPD784908 subseries models

IE-784908-R-EM1
IE-784000-R-EM Emulation board for all 78K/IV series models
IE-78K4-R-EX2 Conversion board for emulation probes required to use the IE-784908-NS-

EM1 on the IE-784000-R. The board is not needed when the conventional

product IE-784908-R-EM1 is used.
EP-78064-GF-R Emulation probe for 100-pin plastic QFP (GF-3BA type)
EV-9200GF-100 Socket for mounting on target system board made for 100-pin plastic QFP

(GF-3BA type)
ID78K4 Integrated debugger for IE-784000-R
SM78K4 System simulator for all 78K/IV series models
DF784908 Device file for µPD784908 subseries models

(4) Real-time OS

RX78K/IV Real-time OS for 78K/IV series models
MX78K4 OS for 78K/IV series models

54

Data Sheet U11681EJ2V0DS00

µ

PD78P4908

(5) Notes when using development tools

• The ID78K4-NS, ID78K4, and SM78K4 can be used in combination with the DF784908.

• The CC78K4 and RX78K/IV can be used in combination with the RA78K4 and DF784908.

• The NP-100GF is a product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult the NEC sales
representative for purchasing.

• The host machines and operating systems corresponding to each software are shown below.

Host machine PC EWS

[OS]

Software NEWSTM (RISC) [NEWS-OSTM]
RA78K4
CC78K4
PG-1500 controller
ID78K4-NS –
ID78K4
SM78K4 –
RX78K/IV
MX78K4

PC-9800 series [WindowsTM] HP9000 series 700TM [HP-UXTM]
IBM PC/AT compatibles [Windows] SPARCstationTM [SunOSTM, SolarisTM]

Note

Note

Note

Note

Note

–

Note Software under MS-DOS

Data Sheet U11681EJ2V0DS00

55

µ

PD78P4908

APPENDIX B CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWING

Connect the µPD78P4908GF-3BA (100-pin plastic QFP (14 × 20 mm)) to the circuit board in combination with the

EV-9200GF-100.

Figure B-1. Package Drawings of EV-9200GF-100 (Reference)

E

D

C

No.1 pin index

EV-9200GF-100

1

A
B

F

G
H

I

ITEM MILLIMETERS INCHES

A
B
C
D
E
F
G
H

I

J

K

L

M

N
O
P
Q
R
S

24.6
21
15

18.6
4-C 2

0.8

12.0

22.6

25.3

6.0

16.6

19.3

8.2

8.0

2.5

2.0

0.35

φ

2.3

φ

1.5

M
N O

P

EV-9200GF-100-G0

R

J

Q

0.969

0.827

0.591

0.732
4-C 0.079

0.031

0.472

0.89

0.996

0.236

0.654
076

0.323

0.315

0.098

0.079

0.014

φ

0.091

φ

0.059

S

L

K

56

Data Sheet U11681EJ2V0DS00

µ

PD78P4908

Figure B-2. Recommended Pattern to Mount EV-9200GF-100 on a Substrate (Reference)

G

J

K

F

E

D

H

L

I

C
B

A

EV-9200GF-100-P1E

ITEM MILLIMETERS INCHES

+0.001
–0.002

+0.001
–0.002

1.035

0.85

0.614

0.799

0.472

0.236

0.014

φ

0.093

φ

0.091

φ

0.062

+0.003
–0.002

+0.003
–0.002

+0.001
–0.001

+0.001
–0.002

+0.001
–0.002

A
B
C
D
E
F

G

H

I

J
K
L

Caution

26.3

21.6

0.65±0.02 × 29=18.85±0.05

0.65±0.02 × 19=12.35±0.05

15.6

20.3
12±0.05
6±0.05

0.35±0.02

φ

2.36±0.03

φ

2.3

φ

1.57±0.03

Dimensions of mount pad for EV-9200 and that for target

0.026 × 1.142=0.742

0.026 × 0.748=0.486

device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING
TECHNOLOGY MANUAL" (C10535E).

+0.002
–0.002

+0.003
–0.002

Data Sheet U11681EJ2V0DS00

57

APPENDIX C RELATED DOCUMENTS

Documents Related to Devices

µ

PD78P4908

Document name

µ

PD784907, 784908 Data Sheet U11680J U11680E

µ

PD78P4908 Data Sheet U11681J This document

µ

PD784908 Subseries User's Manual – Hardware U11787J U11787E

µ

PD784908 Subseries Special Function Registers U11589J —
78K/IV Series User's Manual – Instruction U10905J U10905E
78K/IV Series Instruction Table U10594J —
78K/IV Series Instruction Set U10595J —
78K/IV Series Application Note Software Basic U10095J U10095E

Document No.

Japanese English

Documents Related to Development Tools (User's Manual)

Document name

RA78K4 Assembler Package Operation U11334J U11334E

Language U11162J U11162E
RA78K Series Structured Assembler Preprocessor U11743J U11743E
CC78K4 C Compiler Operation U11572J U11572E

Language U11571J U11571E
PG-1500 PROM Programmer U11940J U11940E
PG-1500 Controller PC-9800 Series (MS-DOSTM) Base EEU-704 EEU-1291
PG-1500 Controller IBM PC Series (PC DOSTM) Base EEU-5008 U10540E
IE-78K4-NS U13356J U13356E
IE-784000-R U12903J U12903E
IE-784908-R-EM1 U11876J —
IE-784908-NS-EM1 U13743J On preparation
EP-78064 EEU-934 EEU-1469
SM78K4 System Simulator Windows Base Reference U10093J U10093E
SM78K Series System Simulator

ID78K4-NS Integrated Debugger PC Base Reference U12796J U12796E
ID78K4 Integrated Debugger Windows Base Reference U10440J U10440E
ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Base Reference U11960J U11960E

External Part User Open

Interface Specifications

Document No.

Japanese English

U10092J U10092E

Caution The above documents may be revised without notice. Use the latest versions when you design

application systems.

58

Data Sheet U11681EJ2V0DS00

Documents Related to Software to Be Incorporated into the Product (User's Manual)

µ

PD78P4908

Document name

78K/IV Series Real-Time OS Fundamental U10603J U10603E

Installation U10604J U10604E
Debugger U10364J —

OS for 78K/IV Series MX78K4 Fundamental U11779J —

Document No.

Japanese English

Other Documents

Document name

NEC IC Package Manual (CD-ROM) – C13388E
Semiconductor Device Mounting Technology Manual C10535J C10535E
Quality Grades on NEC Semiconductor Device C11531J C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Guide to Quality Assurance for Semiconductor Devices — MEI-1202
Guide for Products Related to Microcomputer: Other Companies U11416J —

Document No.

Japanese English

C11892J C11892E

Caution The above documents may be revised without notice. Use the latest versions when you design

application systems.

Data Sheet U11681EJ2V0DS00

59

[MEMO]

µ

PD78P4908

60

Data Sheet U11681EJ2V0DS00

[MEMO]

µ

PD78P4908

Data Sheet U11681EJ2V0DS00

61

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconduc­tor devices must not be touched with bare hands. Similar precautions need to
be taken for PW boards with semiconductor devices on it.

µ

PD78P4908

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS device
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.

62

Data Sheet U11681EJ2V0DS00

µ

PD78P4908

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]

800-366-9782

Fax: [phone]

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel:[phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel:[phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: [phone]
Fax: [phone]

J99.1

Data Sheet U11681EJ2V0DS00

63

µ

PD78P4908

IEBus is a trademark of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.

Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated
in this document.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96. 5