Datasheet UPD78P328GF-3BE Datasheet (NEC)

DATA SHEET

MOS Integrated Circuit

µ

PD78P328

16/8-BIT SINGLE-CHIP MICROCONTROLLER

The µPD78P328 is a product provided by replacing the µPD75328's internal mask ROM with one-time

PROM or EPROM.

The one-time PROM version is programmable only once and is useful for small-lot production of many

different products and early development and time-to-market of application sets.

The EPROM version is reprogrammable, and suited for the evaluation of systems.

Functions are described in detail in the following user's manual. Be sure to read it before designing.

µ

PD78328 User's Manual: IEU-1268

FEATURES

•

µ

PD78328 compatible

• For mass-production, the µPD78P328 can be replaced with the µPD78328 incorporating mask ROM

• Internal PROM: 16,384 x 8 bits

• Programmable once only (one-time PROM version without window)

• Erasable with ultraviolet rays and electrically programmable (EPROM version with window)

• PROM programming characteristics:

• The µPD78P328 is a QTOP

Remark QTOP microcontroller is a general term for microcontrollers which incorporates one-time PROM, and

are totally supported by NEC's programming service (from programming to marking, screening, and
verification).

ORDERING INFORMATION

Part Number Package Internal ROM

µ

PD78P328CW 64-pin plastic shrink DIP (750 mils) One-time PROM

µ

PD78P328GF-3BE 64-pin plastic QFP (14 x 20 mm) One-time PROM

µ

PD78P328DW 64-pin ceramic shrink DIP (750 mils) (with window) EPROM

TM

microcontroller.

µ

PD27C256A compatible

Functions common to the one-time PROM and EPROM versions are referred to as PROM functions throughout this document.

Document No. U10209EJ4V0DS00 (4th edition)

(Previous No. IC-2486)
Date Published October 1995 P
Printed in Japan

The information in this document is subject to change without notice.

The mark

shows revised points.

*



NEC Corporation

1990

PIN CONFIGURATIONS

(1) Normal operating mode

• 64-pin plastic shrink DIP (750 mils)

µ

PD78P328CW

• 64-pin ceramic shrink DIP (750 mils) (with window)

µ

PD78P328DW

µ

PD78P328

P20/NM1
P21/INTP0
P22/INTP1

P30/TxD

P31/RxD

P32/SO/SB0

P33/SI/SB1

P34/SCK

P80/TO0
P81/TO1
P82/TO2

P83/TO3
P84/TO4
P85/TO5

P86/TO6/INTP2

P87/TO7/PWM

V

X1
X2

RESET
P00/RTP0
P01/RTP1
P02/RTP2
P03/RTP3

P04/RTP4
P05/RTP5
P06/RTP6

P07/RTP7

EA

P93/TMD

P92/TAS

V

1
2
3
4
5
6
7
8

9
10
11

12
13
14
15
16

SS

SS

17
18
19

20
21
22
23
24

25
26
27

28
29

30
31

32

64
63
62
61
60
59
58
57
56
55
54

53
52
51
50
49

48
47
46

45
44
43
42
41

40
39
38

37
36

35
34

33

V

DD

AVDD
AVREF
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
AV

SS

VDD
P57/A15

P56/A14
P55/A13

P54/A12
P53/A11
P52/A10

P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5

P44/AD4
P43/AD3
P42/AD2

P41/AD1
P40/AD0

ASTB
P90/RD

P91/WR

Remark These pins are compatible with the

2

µ

PD78328CW pins.

• 64-pin plastic QFP (14 x 20 mm)

µ

PD78P328GF-3BE

P33/SI/SB1

P34/SCK

P80/TO0
P81/TO1
P82/TO2

P83TO3
P84/TO4
P85/TO5

P86/TO6/INTP2

P87/TO7/PWM

V

SS

X1
X2

RESET
P00/RTP0
P01/RTP1
P02/RTP2
P03/RTP3

P04/RTP4

REF

P32/SO/SB0

P31/RxD

P30/RxD

P22/INTP/TI

P21/INTP0

P20/NMI

VDDAVDDAV

64 6362 61 60 59 58 57 56 55 54 53 52

1
2
3
4
5
6
7
8

9
10
11

12
13
14
15

16
17
18
19

20 21 22 2324 25 26 27 28 29 30 31 32

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

51
50
49

48
47

46
45
44

43
42
41
40

39
38
37
36
35
34
33

P73/ANI3
P72/ANI2
P71/ANI1

P70/ANI0

SS

AV
V

DD

P57/A15
P56/A14
P55/A13

P54/A12
P53/A11
P52/A10

P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5

P44/AD4
P43/AD3

µ

PD78P328

SS

V

P92/TAS

P93/TMD

P91/WR

P05/RTP5

P06/RTP6

P07/RTP7

EA

Remark These pins are compatible with the µPD78328GF pins.

ASTB

P90/RD

P40/AD0

P41/AD1

P42/AD2

3

µ

P00-P07 : Port 0 SI : Serial Input
P20-P22 : Port 2 SO : Serial Output
P30-P34 : Port 3 SB0-SB1 : Serial Bus0-1
P40-P47 : Port 4 RD : Read Strobe
P50-P57 : Port 5 WR : Write Strobe
P70-P77 : Port 7 ASTB : Address Strobe
P80-P87 : Port 8 EA : External Access
P90-P93 : Port 9 RESET : Reset
A8-A15 : Address8-15 SCK : Serial Clock
AD0-AD7 : Address0-7/Data0-7 TAS : Turbo Access Strobe
ANI0-ANI7 : Analog Input0-7 TMD : Turbo Mode
TO0-TO7 : Timer Output0-7 X1, X2 : Crystal1, 2
NMI : Nonmaskable Interrupt AV
PWM : Pulse Wide Modulation Output AVREF : Analog Reference Voltage
INTP0-INTP2 : Interrupt From Peripherals0-2 AV
RTP0-RTP7 : Real-Time Port0-7 VDD : Power Supply
TxD : Transmit Data VSS : Ground
RxD : Receive Data

DD : Analog VDD

SS : Analog VSS

PD78P328

4

(2) PROM programming mode (RESET = H, AVDD = L)

• 64-pin plastic shrink DIP (750 mils)

µ

PD78P328CW

• 64-pin ceramic shrink DIP (750 mils) (with window)

µ

PD78P328DW

µ

PD78P328

A9

(G)

(L)

OE
CE

(L)

A8
A10
A11

A12
A13
A14

(L)

V
(G)

(Open)

RESET

A0

A1

A2

A3

A4

A5

A6

A7

V

(L)

V

1
2
3
4
5
6
7
8

9
10
11

12
13
14
15
16

SS

PP

SS

17
18
19

20
21
22
23
24

25
26
27

28
29

30
31

32

64
63
62
61
60
59
58
57
56
55
54

53
52
51
50
49

48
47
46

45
44
43
42
41

40
39
38

37
36

35
34

33

V

DD

AV

DD

(G)

DD

V

(L)

D7
D6
D5

D4
D3
D2

D1
D0

(Open)

(L)

Caution The recommended connection of the unused pins in the PROM programming mode are indicated

in parentheses.
L : Connect each pin to V

SS via a resistor.

G : Connect the pin to VSS.
Open : Leave the pin unconnected.

5

• 64-pin plastic QFP (14 x 20 mm)

µ

PD78P328GF-3BE

µ

PD78P328

CE

(L)

A8
A10
A11
A12
A13
A14

(L)

V
(G)

(Open)

RESET

A0

A1

A2

A3

A4

(L)

OE

64 63 62 61 60 59 58 57 56 55 54 53 52

1
2
3
4
5
6
7
8
9

10

SS

11
12
13
14
15

16
17
18
19

20 21 22 2324 25 26 27 2829 30 31 32

(G)

A9

DD

DD

AV

V

(G)

51
50
49

48
47

46
45
44

43
42
41
40

39
38
37
36
35
34
33

V

D7
D6
D5

D4
D3

(G)

DD

(L)

A5A6A7

PP

V

(L)

SS

V

(L)

D0D1D2

(Open)

Caution The recommended connection of the unused pins in the PROM programming mode are indicated

in parentheses.
L : Connect each pin to VSS via a resistor.
G : Connect the pin to V

SS.

Open : Leave the pin unconnected.

A0-A14 : Address0-14 AV

DD : Analog VDD

D0-D7 : Data0-7 VDD : Power Supply
CE : Chip Enable VSS : Ground
OE : Output Enable V

PP : Programming Power Supply

RESET : Reset

6

BLOCK DIAGRAM

µ

PD78P328

(P20) NMI

INTP0-INTP2

(P21, P22, P86)

(P80) TO0
(P81) TO1

(P82) TO2
(P83) TO3
(P84) TO4
(P85) TO5
(P86) TO6

(P87) TO7/PWM

(P22) TI/INTP1

(P34) SCK

(P32) SO/SB0

(P33) SI/SB1

(P30) TxD
(P31) RxD

Programmable

Interrupt

Controller

Timer/Counter Unit

(Real-Time

Pulse Unit)

Serial Interface

(SBI)

(UART)

Main RAM

General

Registers

128 x 8

&

Data

Memory

128 x 8

Micro Sequence

Control

Micro ROM

A/D Converter

(10-bit)

EXU PROM/RAM

ALU

PROM

16K x 8

&

Peripheral

RAM

256 X 8

REF

AV
AV

AV

SS
DD

WDT

INTP0
ANI0-ANI7

(P70-P77)

/

/

2

2

DD

SS

V

V

BCU

System
Control

&

Bus

Control

&

Prefetch

Control

Ports

X1
X2

RESET
ASTB

RD (P90)
WR (P91)
TAS (P92)

TMD (P93)
A8-A15 (P50-P57)
AD0-AD7 (P40-P47)

A0-A14
D0-D7
CE

Note

OE

Note

EA/V

PP

P00-P07
(Real-Time Port)

P20-P22
P30-P34

P40-P47
P50-P57
P70-P77
P80-P87
P90-P93

Note During PROM programming mode

7

CONTENTS

1. PIN FUNCTIONS ... 9

1.1 Normal Operating Mode ... 9

1.2 PROM Programming Mode (RESET = H, AVDD = L) ... 11

1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ... 12

2. DIFFERENCES BETWEEN µPD78P328 and µPD78328 ... 14

3. PROM PROGRAMMING ... 15

3.1 Operation Mode ... 15

3.2 PROM Write Procedure ... 16

3.3 PROM Read Procedure ... 18

4. ERASURE CHARACTERISTICS (EPROM VERSION ONLY) ... 19

5. WINDOW SEAL (EPROM VERSION ONLY) ... 19

µ

PD78P328

6. ONE-TIME PROM VERSION SCREENING ... 19

7. ELECTRICAL SPECIFICATIONS ... 20

8. PACKAGE DRAWINGS ... 35

9. RECOMMENDED SOLDERING CONDITIONS ... 37

APPENDIX A. DRAWINGS OF CONVERSION SOCKET AND RECOMMENDED FOOTPRINT... 38

APPENDIX B. TOOLS ... 40

B.1 Development Tools ... 40
B.2 Evaluation Tools ... 43
B.3 Embedded Software ... 43

*

8

µ

PD78P328

1. PIN FUNCTIONS

1.1 Normal Operating Mode

(1) Port Pins

Pin Name Input/Output Function Alternate

Function

P00-P07 Input/Output PORT0 RTP0-RTP7

4-/8-bit input/output port
Input or output mode can be specified bit-wise.

The port can also operate as a real-time output port.
P20 Input PORT 2 NMI
P21 3-bit input-only port INTP0
P22 INTP1/TI
P30 Input/Output PORT 3 TxD
P31 5-bit input/output port RxD
P32 Input or output mode can be specified bit-wise. SO/SB0
P33 SI/SB1
P34 SCK
P40-P47 Input/Output PORT 4 AD0-AD7

8-bit input/output port

Input or output mode can be specified in 8-bit units.
P50-P57 Input/Output PORT 5 A8-A15

8-bit input/output port

Input or output mode can be specified bit-wise.
P70-P77 Input PORT 7 ANI0-ANI7

8-bit input-only port
P80 Input/Output PORT 8 TO0
P81 8-bit input/output port TO1
P82 Input or output mode can be specified bit-wise. TO2
P83 TO3
P84 TO4
P85 TO5
P86 TO6/INTP2
P87 TO7/PWM
P90 Input/Output PORT 9 RD
P91 4-bit input/output port WR
P92 Input or output mode can be specified bit-wise. TAS
P93 TMD

9

(2) Non-Port Pins (1/2)

Pin Name Input/Output Function Alternate

RTP0-RTP7 Output Real-time output port which outputs a pulse in synchronization with the trigger signal from P00-P07

NMI Input Edge-detected nonmaskable interrupt request input. P20

INTP0 Input Edge-detected external interrupt request input. P21
INTP1 The valid edge can be specified in the mode register. P22/T1
INTP2 P86/TO6
TI Input External count clock input pin to timer 1 (TM1). S22/INTP1
RxD Input Serial data input pin to asynchronous serial interface (UART). P30
TxD Output Serial data output pin from asynchronous serial interface (UART). P31
SO Output Serial data output pin from clocked serial interface in 3-wire mode. P32/SB0
SI Input Serial data input pin to clocked serial interface in 3-wire mode. P33/SB1
SB0 Input/Output Serial data input/output pins to/from clocked serial interface in SBI mode. P32/SO
SB1 P33/SI
SCK Input/Output Serial clock input/output pin to/from clocked serial interface. P34
AD0-AD7 Input/Output Multiplexed address/data bus used when external memory is added. P40-P47
A8-A15 Output Address bus used when external memory is added. P50-P57
TO0 Output Pulse output from real-time pulse unit. P80
TO1 P81
TO2 P82
TO3 P83
TO4 P84
TO5 P85
TO6 P86/INTP2
TO7 P87/PWM
PWM Output PWM signal output from real-time pulse unit. P87/TO7
RD Output Strobe signal output for external memory read operation. P90
WR Strobe signal output for external memory write operation. P91

*

TAS Control signal output pins to access turbo access manager (µPD71P301).
TMD P93
ASTB Output Timing signal output pin to externally latch an address information output to port 4 for —

EA Input For µPD78P328, normally connect the EA pin to VDD. When the EA pin is connected to —

real-time pulse unit (RPU).

The rising or falling edge can be selected for the valid edge by setting the mode register.

Note

external memory access.

VSS, the µPD78P328 enters the ROMless mode and external memory is accessed.
The EA pin level cannot be changed during operation.

µ

PD78P328

Function

P92

Note Turbo access manager (µPD71P301) is available for maintenance purposes only.

10

µ

PD78P328

(2) Non-Port Pins (2/2)

Pin Name Input/Output Function Alternate

Function

ANI0-ANI7 Input Analog input to A/D converter. P70-P77

AVREF Input A/D converter reference voltage input. —
AVDD — A/D converter analog power supply. —
AVSS — A/D converter GND. —
RESET Input System reset input. —
X1 Input Crystal connection pin for system clock generation. To supply external clock, —
X2 — input to the X1 and input reverse signal to the X2 pin (X2 pin can be unconnected.) —
VDD — Positive power supply pin. —
VSS — GND pin. —

1.2 PROM Programming Mode (RESET = H, AVDD = L)

Pin Name Input/Output Function
AVDD Input PROM programming mode setting.
RESET
A0-A14 — Address bus.
D0-D7 — Data bus.
CE Input PROM enable to PROM.
OE Input Read strobe to PROM.
VPP — Write power supply.
VDD Positive power supply.
VSS GND.

11

1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins

Table 1-1 and Figure 1-1 show the pin input/output circuit schematically.

Table 1-1. Pin Input/Output Circuits and Recommended Connection of Unused Pins

Pin Input/Output Recommended connection of unused pins

circuit type

P00P07/RTP0-RTP7 5 Input state: Independently connect to VDD or VSS via a resistor.

Output state: Leave Open.
P21/NMI 2 Connect to VSS.
P21/INTP0
P27/INTP6/TI
P30/TxD 5 Input state: Independently connect to VDD or VSS via a resistor.
P31/RxD Output state: Leave Open.
P32/SO/SB0 8
P33/SI/SB1
P34/SCK
P40/AD0-P47/AD0-AD7 5
P50/P57/A8-A15
P70-P77/ANI0-ANI7 9 Connect to VSS.
P80-P85/TO0-TO5 5 Input state: Independently connect to VDD or VSS via a resistor.
P86/TO6/INTP2 6 Output state: Leave Open.
P87/TO7/PWM 5
P90/RD 5
P91/WR
P92/TAS
P93/TMD
ASTB 4 Leave Open.
EA 1 —
RESET 2 —
AVREF, AVSS — Connect to V SS.
VDD — Connect to VDD.

µ

PD78P328

12

Figure 1-1. Pin Input/Output Circuits

TYPE 1 TYPE 6

V

DD

IN

P-ch

N-ch

data input enable

control signal

control input
enable

data

output
disable

data

µ

PD78P328

V

DD

P-ch

IN/OUT

N-ch

TYPE 2

TYPE 8

data

IN

output
disable

Schmitt-triggerred input with hysteresis characteristics

TYPE 4 TYPE 9

V

DD

IN

data

output
disable

Push-pull output that can be placed in high impedance
(both P-ch and N-ch off).

P-ch

N-ch

OUT

TYPE 5

V

P-ch
N-ch

(Threshold voltage)

DD

V

P-ch

N-ch

REF

IN/OUT

Comparator

+
–

input
enable

data

output
disable

input
disable

V

DD

P-ch

IN/OUT

N-ch

13

µ

PD78P328

2. DIFFERENCES BETWEEN µPD78P328 and µPD78328

The µPD78P328 is a product provided by replacing the µPD78328's on-chip mask ROM with one-time PROM
or EPROM. Thus, the µPD78P328 and µPD78328 are the same in function except for the ROM specifications such
as write or verify. Table 2-1 lists the differences between these two products.

µ

This Data Sheet describes the PROM specification function. Refer to the
other functions.

PD78328 documents for details of

Table 2-1. Differences between µPD78P328 and µPD78328

Item
Internal program memory One-time PROM EPROM Mask ROM
(electrical program) (programmable only once) (reprogrammable) (nonprogrammable)
PROM programming pin Contained Not contained
Package • 64-pin plastic shrink DIP • 64-pin ceramic shrink DIP • 64-pin plastic shrink DIP

*

Electrical specifications Current dissipations are different.
Others Noise immunity and noise radiation differ because circuit complexity and mask layout are

*

Caution The noise immunity and noise radiation differ between the PROM and mask ROM versions. To

*

replace the PROM version with the mask ROM version when shifting from experimental production
to mass production, evaluate your system by using the CS version (not ES version) of the mask
ROM version.

µ

PD78P328

• 64-pin plastic QFP (with window) • 64-pin plastic QFP

different.

µ

PD78328

14

µ

PD78P328

3. PROM PROGRAMMING

The PROM incorporated in the µPD78P328 is a 16,384 x 8-bit electrically writable PROM. For programming,

set the PROM programming mode by using the RESET and AVDD pins.

The programming characteristics are compatible with the µPD27C256A programming characteristics.

Table 3-1. Pin Function in Programming Mode

Function Normal Operating Mode Programming Mode
Address input P00-P07, P80, P20, P81-P85 A0-A14
Data input P40-P47 D0-D7
Chip enable/program pulse P33 CE
Output enable P32 OE
Program voltage EA VPP
Mode control RESET, AVDD

3.1 Operation Mode

To set the program write/verify mode, set RESET = H and AV

selected by setting the CE and OE pins, as listed in Table 3-2.

To read the PROM contents, set the read mode.
Connect the unused pins exactly as indicated on Pin Configuration.

DD = L. For the mode, the operation mode can be

Table 3-2. PROM Programming Operation Mode

Mode RESET AVDD CE OE VPP VDD D0-D7
Program write H L L H +12.5 V +6 V Data input
Program verify H L Data output
Program inhibit H H High impedance
Read L L +5 V +5 V Data output
Output disable L H High impedance
Standby H L/H High impedance

Caution When VPP is set to +12.5 V and VDD is set to +6V, setting both CE and OE to L is inhibited.

15

µ

PD78P328

3.2 PROM Write Procedure

The write procedure into PROM is as follows: (See also Figure 3-2).

(1) Fix RESET = H and AV

DD = L. Connect other unused pins exactly as indicated in section "Pin Configuration."

(2) Supply +6 V to the VDD and +12.5 V to the VPP pin.
(3) Supply an initial address.
(4) Supply write data.
(5) Supply 1 ms program pulse (active low) to the CE pin.
(6) Execute the verify mode. Check whether or not the write data is written normally.

• When it is written normally: Proceed to step (8).

• When it is not written normally: Repeat steps (4) to (6).

If the data is not written normally after 25 repetitions of the steps, proceed to step (7).
(7) Assume the device to be defective. Stop write operation.
(8) Supply write data and X (number of steps (4) to (6) repetitions) x 3 ms program pulses (additional write).
(9) Increment the address.
(10) Repeat steps (4) to (9) to the last address.

Figure 3-1 shows the PROM Write/Verify Timing Steps (2) to (8) above.

A0-A14

D0-D7

+12.5 V

V

PP

+6 V

V

DD

CE (input)

OE (input)

Figure 3-1. PROM Write/Verify Timing

X-time repetition

Write

Data input

V

DD

V

DD

Hi-Z Hi-Z Hi-Z

Verify

Address input

Data

output

Additional
data write

Data input

3 X ms

16

Figure 3-2. Write Procedure Flowchart

µ

PD78P328

(1)

(2)

(3)

(4)

(5)

Write NG

(after 24

repetition or less)

(8)

(9)

WRITE START

Supply power

Supply initial address

Supply write data

Supply program pulse

(6)

Verify mode

Write OK

Make additional write

(3X ms pulses)

Increment address

Write NG
(at the 25th repetition)

X: Number of write

repetitions

< end address

(10)

End address

> end address

WRITE END Defective device

(7)

17

3.3 PROM Read Procedure

The read procedure of the PROM contents into the external data bus (D0-D7) is as follows.
(1) Fix RESET = H and AV
(2) Supply +5 V to the VDD and VPP pins.
(3) Input the address of the data to be read to the A0-A14 pins.
(4) Execute the read mode.
(5) The data is output to the D0-D7 pins.

Figure 3-3 shows the PROM read timing steps (2) to (5) above.

DD = L. Connect other unused pins exactly as indicated on Pin Configuration.

Figure 3-3. PROM Read Timing

µ

PD78P328

A0-A14

CE (input)

OE (input)

D0-D7

Address input

Hi-Z Hi-Z

Data output

18

µ

PD78P328

4. ERASURE CHARACTERISTICS (EPROM VERSION ONLY)

The data written into the µPD78P328DW program memory can be erased (FFH) and new data can be rewritten

into the memory.

To erase data, apply light with a wave length shorter than 400 nm to the window. Normally, apply ultraviolet rays

having the 254-nm wave length. The radiation amount required to completely erase data is as follows:

2

• Ultraviolet strength x erasure time: 15 W•s/cm

• Erasure time: 15 to 20 minutes when a 12,000
prolonged due to ultraviolet lamp performance deterioration, dirty window, etc.

For erasure, place an ultraviolet lamp at a position within 2.5 cm from the window. If a filter is attached to the

ultraviolet lamp, remove the filter before applying ultraviolet rays.

or more

µ

W/cm2 ultraviolet lamp is used. However, the time may be

5. WINDOW SEAL (EPROM VERSION ONLY)

If the µPD78P328DW window is exposed to sunlight or fluorescent lamp light for hours, EPROM data may be
erased and the internal circuit may operate erroneously. To prevent such accidents from occurring, put a protective
seal on the window.

A protective seal whose quality is guaranteed by NEC is attached to every EPROM version with window at
shipment.

6. ONE-TIME PROM VERSION SCREENING

The one-time PROM versions (µPD78P328CW, 78P328GF-3BE) cannot be completely tested by NEC for
shipment because of their structure. For screening, it is recommended to verify PROM after storing the necessary
data under the following conditions:

NEC provides chargeable services ranging from one-time PROM writing to marking, screening, and verification
for QTOP microcontroller products. For details, contact an NEC sales representative.

Storage temperature Storage time
125˚C 24 hours

19

µ

7. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25 °C)

Parameter Symbol Test Conditions Ratings Unit
Power supply voltage VDD –0.5 to +7.0 V

VDD –0.5 to VDD +0.5 V
VPP –0.5 to +13.5 V
AVSS –0.5 to +0.5 V

Input voltage VI1 Note 1 –0.5 to VDD +0.5 V

VI2 P20/NIM (A9) PIN –0.5 to +13.5 V
Output voltage VO –0.5 to VDD +0.5 V
Output current, low IOL All output pins 4.0 mA

Total for all pins 90 mA

Output current, high IOH All output pins –1.0 mA

Total for all pins –20 mA

Analog input voltage VIAN Note 2 AVDD > VDD -0.5 to VDD +0.5 V

VDD ≥ AVDD -0.5 to AVDD +0.5 V
A/D converter reference AVREF AVDD > VDD -0.5 to VDD +0.3 V
input voltage VDD ≥ AVDD -0.5 to AVDD +0.3 V
Operating ambient temperature TA –10 to +70 °C
Storage temperature Tstg –65 to +150 °C

PD78P328

Notes 1. Pins except for P20/NMI (A9), P70/ANI0-P77/ANI7

2. P70/ANI0-P77/ANI7

Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter,

*

even momentarily. In other words, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be used under
conditions which ensure that the absolute maximum ratings are not exceeded.

Recommended Operation Conditions

Oscillation frequency TA VDD
8 MHz ≤ fXX ≤ 16 MHz –10 to +70 ˚C +5.0 V ±5%

Capacitance (TA = 25 °C, VSS = VDD = 0 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Input capacitance CI f = 1 MHz 10 pF
Output capacitance CO Unmeasured pins returned to 0 V 20 pF
I/O capacitance CIO 20 pF

20

µ

PD78P328

Oscillator Characteristics (TA = –10 to +70 °C, VDD = +5 V±5%, VSS = 0 V)

Resonator Recommended Circuit Parameter MIN. MAX. Unit
Ceramic or crystal Oscillation frequency (fXX) 8 16 MHz
resonator

V

X1X2

SS

C1C2

External clock X1 input frequency (fX) 8 16 MHz

X1 X2

HCMOS
Inverter

or

X1 X2

Open

HCMOS
Inverter

X1 input rise, fall time (fXR, tXF) 0 20 ns

X1 input high, low level width 25 80 ns
(tWXH, tWXL)

Caution When using the system clock oscillator, wire the portion enclosed in dotted line in the figure as

follows to avoid adverse influences on the wiring capacitance:

• Keep the wiring length as short as possible.

• Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of
lines through which a high fluctuating current flows.

• Always keep the ground point of the capacitor of the oscillator circuit at the same potential as

SS. Do not connect the power source pattern through which a high current flows.

V

• Do not extract signals from the oscillation circuit.

Recommended Oscillator Constants

Ceramic resonator

Manufacturer Name Part Number Frequency Recommended

MURATA CSA8.00MT 8.0 30 30

CSA12.0MT 12.0
CSA16.00MX040 16.0 15 15
CST8.00MTW 8.0 Internal Internal
CST12.00MTW 12.0
CST16.00MXW0C3 16.0

[MHz] Constants

C1 [pF] C2 [pF]

21

µ

PD78P328

DC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Input voltage, low VIL 0 0.8 V
Input voltage, high VIH1 Note 1 2.2 V

VIH2 Note 2 0.8VDD
Output voltage, low VOL IOL = 2.0 mA 0.45 V
Output voltage, high VOH IOH = –400 µAVDD–1.0 V
Input leakage current ILI 0 V ≤ VI ≤ VDD ±10
Output leakage current ILO 0 V ≤ VO ≤ VDD ±10
VDD power supply current IDD1 Operation mode 45 75 mA

IDD2 HALT mode 25 45 mA
Data retention voltage VDDDR STOP mode 2.5 V
Data retention current IDDDR STOP mode VDDDR = 2.5 V 3 15

VDDDR = 5.0 V ±5% 10 50

µ

A

µ

A

µ

A

µ

A

Notes 1. Pins except for RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1/TI, P86/INTP2/TO0, P32/SO/SB0,

P33/SI/SB1, or P34/SCK.

2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1/TI, P86/INTP2/TO0, P32/SO/SB0, P33/SI/SB1, or
P34/SCK pins.

22

µ

PD78P328

AC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V)

Discontinuous read/write operation (when general-purpose memory is connected)

Parameter Symbol Test Conditions MIN. MAX. Unit
System clock cycle time tCYK 125 250 ns
Address setup time (to ASTB ↓)tSAST 22 ns
Address hold time (from ASTB ↓)tHSTA 32 ns
Address → RD ↓ delay time tDAR 85 ns
RD ↓ → address float time tFRA 8ns
Address → data input time tDAID 222 ns
RD ↓ → data input time tDRID 112 ns
ASTB ↓ → RD ↓ delay time tDSTR 42 ns
Data hold time (from RD ↑)tHRID 0ns
RD ↑ → address active time tDRA 37 ns
RD low-level width tWRL 147 ns
ASTB high-level width tWSTH 37 ns
Address → WR ↓ delay time tDAW 85 ns
ASTB ↓ → data output time tDSTOD 102 ns
WR ↓ → data output time tDWOD 40 ns
ASTB ↓ → WR ↓ delay time tDSTW 42 ns
Data setup time (to WR ↑)tSODW 137 ns
Data hold time (from WR ↑)tHWOD 32 ns
WR ↑ → ASTB ↓ delay time tDWST 42 ns
WR low-level width tWWL 147 ns

23

tCYK-Dependent Bus Timings

Parameter Calculation expression MIN./MAX. Unit
tSAST 0.5T – 40 MIN. ns
tHSTA 0.5T – 30 MIN. ns
tDAR T – 40 MIN. ns
tDAID (2.5 + n) T – 90 MAX. ns
tDRID (1.5 + n) T – 75 MAX. ns
tDSTR 0.5T – 20 MIN. ns
tDRA 0.5T – 25 MIN. ns
tWRL (1.5 + n) T – 40 MIN. ns
tWSTH 0.5T – 25 MIN. ns
tDAW T – 40 MIN. ns
tDSTOD 0.5T + 40 MAX. ns
tDSTW 0.5T – 20 MIN. ns
tSODW 1.5T – 50 MIN. ns
tHWOD 0.5T – 30 MIN. ns
tDWST 0.5T – 20 MIN. ns
tWWL (1.5 + n) T – 40 MIN. ns

µ

PD78P328

Remarks 1. T = tCYK = 1/fCLK (fCLK is the internal system clock frequency and is provided by dividing fXX or fX by two).

2. n is the number of wait cycles defined by user software.

3. Only parameters listed in the table are dependent on t

CYK.

24

µ

PD78P328

Serial Operation (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V)

Parameter Symbol Test Conditions MIN. MAX. Unit
Serial clock cycle time tCYSK Input External clock 1

Output Internal divide by 8 8T tCYK

Internal divide by 32 32T tCYK

Serial clock high-level width tWSKL Input External clock 420 ns

Output Internal divide by 8 4T–80 ns

Internal divide by 32 16T–100 ns

Serial clock high-level width tWSKH Input External clock 420 ns

Output Internal divide by 8 4T–80 ns

Internal divide by 32 16T–100 ns
SI setup time (to SCK ↑)tSRXSK 80 ns
SI hold time (from SCK ↑)tHSKRX 80 ns
SO/SB0, SI/SB1 tDSBSK1 CMOS push-pull output 0 210 ns
output delay time (from SCK ↓) (3-wire serial I/O mode)

tDSBSK2 Open drain output 0 600 ns

(SBI mode), RL = 1 kΩ
SB0, SB1 high hold time (from SCK ↑)tHSBSK SBI mode 4T tCYK
SB0, SB1 low setup time (from SCK ↓)tSSBSK 4T tCYK
SB0, SB1 low-level width tWSBL 4T–20 ns
SB0, SB1 high-level width tWBSH 4T–20 ns

µ

s

Remark T = tCYK = 1/fCLK (fCLK is the internal system clock frequency and is provided by dividing fXX or fX by two.)

25

µ

PD78P328

Other operations (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = 0 V)

Parameter Symbol Test Conditions MIN. MAX. Unit
NMI high-, low-level widths tWNIH,5

tWNIL

INTP0 high-, low-level widths tWIOH,8TtCYK

tWIOL

INTP1 high-, low-level widths tWI1H ,8TtCYK

tWI1L

INTP2 high-, low-level widths tWI2H ,8TtCYK

tWI2L

RESET high-, low-level widths tWRSH,5

tWRSL

TI high-, low-level widths tWTIH, TM1 8T tCYK

tWTIL In the event counter mode

µ

s

µ

s

Remark T = tCYK = 1/fCLK (fCLK is the internal system clock frequency and is provided by dividing fXX or fX by two.)

External clock timing (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = 0 V)

Parameter Symbol Test Conditions MIN. MAX. Unit
X1 input high-, low-level widths tWXH,2580ns

tWXL

X1 input rise, fall times tXR, 0 20 ns

tXF

TI input cycle time tCYK 62 125 ns

26

µ

PD78P328

A/D Converter (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = AVSS = 0 V, VDD –0.5 V ≤ AVDD ≤ VDD)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Resolution 10 bit
Total error

Quantification error ±1/2 LSB
Conversion time tCONV 144 tCYK
Sampling time tSAMP 24 tCYK
Zero scale error

Fullscale error

Nonlinear error

Analog input voltage
Basic voltage AVREF 3.4 AVDD V
AVREF current AIREF 1.0 3.0 mA
AVDD supply current AIDD 2.0 6.0 mA
A/D converter data AIDDDR STOP mode AVDDDR = 2.5 V 2.0 10
retention current AVDDDR = 5 V±5% 10 50

Note1

Note1

Note1

Note1

Note2

4.5 V ≤ AVREF ≤ AVDD ±0.4 %FSR

3.4 V ≤ AVREF ≤ AVDD ±0.7 %FSR

4.5 V ≤ AVREF ≤ AVDD +1.5 ±2.5 LSB

3.4 V ≤ AVREF ≤ AVDD +1.5 ±4.5 LSB

4.5 V ≤ AVREF ≤ AVDD +1.5 ±2.5 LSB

3.4 V ≤ AVREF ≤ AVDD +1.5 ±4.5 LSB

4.5 V ≤ AVREF ≤ AVDD +1.5 ±2.5 LSB

3.4 V ≤ AVREF ≤ AVDD +1.5 ±4.5 LSB

VIAN –0.3 AVDD V

µ

A

µ

A

*

Notes 1. Quantization error is excluded.

2. When –0.3 V ≤ V

IAN ≤ 0 V, conversion result is 000H.

When 0 V < VIAN < AVREF, conversion is executed by 10-bit resolution.
When AV

REF ≤ VIAN ≤ AVDD, conversion result is 3 FFH.

Standby flag retention characteristics (TA = –10˚C to 70˚C)

Parameter Symbol Test Conditions MIN. MAX. Unit
Standby flag retention power supply voltage VDDDR 2.5 5.5 V
VDD rising, falling time tRVD, 200 ns

tFVD

AC Timing Test Points

– 1 V

V

DD

0.45 V

0.8 VDD or 2.2 V

0.8 V

Test

Points

0.8 V

or 2.2 V

DD

0.8 V

27

Timing Wave Forms

Discontinuous Read Operation

(CLK)

t

CYK

µ

PD78P328

P50-P57
(output)

P40-P47
(input/output)

t

P50-P57
(output)

RD (output)

Discontinuous Write Operation

(CLK)

P50-P57
(output)

t

(output)

t

DAR

t

DAID

t

HSTA

DSTR

t

SAST

Low-order address

WSTH

High-order address High-order address

Hi-Z Hi-Z Hi-Z

t

FRA

Data (input)

t

t

DRID

t

WRA

HRID

t

DRA

Low-order address

(output)

High-order address High-order address

P40-P47
(input/output)

ASTB
(output)

WR (output)

t

SAST

Low-order address

(output)

t

WSTH

t

HSTA

t

DSTW

t

DAW

t

DSTOD

t

DWOD

t

WWL

Data (output)

t

SODW

t

HWOD

t

DSTA

Low-order address

(output)

28

Serial Operation

Three-Wire Serial I/O Mode:

SCK

t

WSKL

t

CYSK

t

WSKH

t

SRXSKtHSKRX

µ

PD78P328

SI

SO

SBI Mode

Bus Release Signal Transfer

SCK

SB0

t

HSBSK

Command Signal Transfer

SCK

t

HSBSK

SB0 I/O data

t

WSBL

t

SSBSK

t

WSBH

t

DSBSKI

Output data

t

SSBSK

t

WSKL

t

CYSK

t

WSKH

Input data

t

DSBSK2tSSSK

t

HSSK

29

Interrupt Input Timing

µ

PD78P328

NMI

INTP0

INTP1

t

WNIH

t

WIOH

t

t

WI2H

WI1H

0.8 V

0.8 V

t

WNIL

DD

t

WIOL

t

WI1L

t

WI2L

Reset Input Timing

INTP2

RESET

t

WRSH

0.8 V

DD

0.8 V

t

WRSL

30

External Clock Timing

X1

t

WXH

µ

PD78P328

Standby Flag Retention Timing

V

DD

TI Pin Input Timing

TI

t

XR

t

t

FVD

t

WTIH

CYX

V

DDDR

t

XF

t

WXL

t

RVD

t

WTIL

31

µ

PD78P328

DC Programming Characteristics (TA = 25 ± 5 °C, VSS = 0 V)

Parameter Symbol Symbol Test conditions MIN. TYP. MAX. Unit

Note1

Input voltage, high VIH VIH 2.2 VDDP V

+0.3
Input voltage, low VIL VIL –0.3 0.8 V
Input leakage current ILIP ILI 0 ≤ VI ≤ VDDP
Output voltage, high VOH VOH IOH = –400 µA 2.4 V
Output voltage, low VOL VOL IOL = 2.0 mA 0.45 V
Input current IA9 — A9 (P20/NMI) pin ±10
Output leakage current ILO —0 ≤ VO ≤ VDDP, OE = VIN 10
PROG pin high voltage input IIP — ±10
current
VDDP power supply voltage VDDP VDD Program memory write mode 5.75 6.0 6.25 V

Program memory read mode 4.5 5.0 5.5 V

VPP power supply voltage VPP VPP Program memory write mode 12.2 12.5 12.8 V

Program memory read mode VPP = VDDP V

VDDP power supply current IDD IDD Program memory write mode 10 30 mA

Program memory read mode 10 30 mA
CE = VIL, OE = VIN

VPP power supply current IPP IPP Program memory write mode 10 30 mA

CE = VIL, OE = VIN
Program memory read mode 1 100

Note 2

±10

µ

A

µ

A

µ

A

µ

A

µ

A

Notes 1. Corresponding µPD27C256A symbols.

2. VDDP is VDD pin during the programming mode.

32

µ

PD78P328

AC Programming Characteristics (TA = 25 ± 5 °C, VSS = 0 V)

Parameter Symbol Symbol Test conditions MIN. TYP. MAX. Unit

Note

Address setup time (to CE ↓)tSAC tAS 2
Data → OE ↓ delay time tDDOO tOES 2
Input data setup time (to CE ↓)tSIDC tDS 2
Address hold time (from CE ↑)tHCA tAH 2

Input data hold time (from CE ↑) tHCID tDH 2
Output data hold time (from OE ↑) tHOOD tDF 0 130 ns

VPP setup time (to CE ↓)tSVPC tVPS 2
VDDP setup time (to CE ↓)tSVDC tVDS 2
Initial program pulse width tWL1 tPW 0.95 1.0 1.05 ms
Additional program pulse width tWL2 tOPW 2.85 78.75 ms
Address → data output time tDAOD tACC OE = VIL 2
OE ↓ → data output time tDOOD tOE 1
Data hold time (from OE ↑)tHCOD tDF 0 130 ns
Data hold time (from address) tHAOD tOH OE = VIL 0ns

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

Note Corresponding µPD27C256A symbols.

33

PROM Write Mode Timing

µ

PD78P328

V

V

DDP

CE

OE

PP

A12-A0

D7-D0

V

V

DDP

V

DDP

+1

V

DDP

V

V

V

V

t

SAC

Data input

t

SIDC

PP

t

SVPC

t

SVDC

IH

IL

IH

IL

t

WL1

Effective address

Data output Data onput

t

HCID

t

DDOO

t

DOOD

Cautions 1. Apply VDDP before VPP and remove it after VPP.

2. VPP must not exceed +13 V, including the overshoot.

t

HOOD

t

SIDC

t

HCA

t

HCID

t

WL2

PROM Read Mode Timing

A12-A0

OE

D7-D0

t

DAOD

Effective address

t

DOOD

t

HAOD

Data output

t

HCOD

Hi-ZHi-Z

34

8. PACKAGE DRAWINGS

64 PIN PLASTIC SHRINK DIP (750 mil)

64 33

A

µ

PD78P328

321

K

I

J

H

G

NOTE

Each lead centerline is located within 0.17 mm (0.007 inch) of

1)
its true position (T.P.) at maximum material condition.

Item "K" to center of leads when formed parallel.2)

F

M

D

N

L

B

C

ITEM MILLIMETERS INCHES

A
B
C

D

F
G
H

I

J
K

L
M
N

R

M

58.68 MAX.

1.78 MAX.

1.778 (T.P.)

0.50±0.10

0.9 MIN.

3.2±0.3

0.51 MIN.

4.31 MAX.

5.08 MAX.

19.05 (T.P.)

17.0
+0.10

0.25

–0.05

0.17

0~15°

2.311 MAX.

0.070 MAX.

0.070 (T.P.)

0.020

0.035 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.750 (T.P.)

0.669

0.010

0.007
0~15°

P64C-70-750A,C-1

+0.004
–0.005

+0.004
–0.003

R

35

µ

PD78P328

36

64 PIN PLASTIC QFP (14×20)

A
B

µ

PD78P328

52

64

51

1

33

19

32

20

F

G

H

M

I

P

N

NOTE

Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.

detail of lead end

C D

S

Q

R

J

K

M

L

ITEM MILLIMETERS INCHES

A

23.6±0.4

B

20.0±0.2

C

14.0±0.2

D 17.6±0.4 0.693±0.016
F 1.0 0.039
G 1.0 0.039

H 0.40±0.10 0.016

I 0.20 0.008

J 1.0 (T.P.) 0.039 (T.P)

K 1.8±0.2 0.071

L 0.8±0.2 0.031

M 0.15 0.006
N 0.10 0.004

P 2.7 0.106
Q 0.1±0.1 0.004±0.004
R 5°±5° 5°±5°
S 3.0 MAX. 0.119 MAX.

+0.10
–0.05

P64GF-100-3B8,3BE,3BR-2

0.929±0.016
+0.008

0.795

–0.009
+0.009

0.551

–0.008

+0.004

–0.005

+0.008

–0.009

+0.009

–0.008

+0.004

–0.003

37

µ

PD78P328

9. RECOMMENDED SOLDERING CONDITIONS

It is recommended that this device be soldered under the following conditions.
For details on the recommended soldering conditions, refer to information document "Semiconductor Devices
Mounting Technology Manual" (IEI-1207).

For soldering methods and conditions other than those recommended, please contact your NEC sales
representative.

Table 9-1. Soldering Conditions for Surface Mount Devices

µ

PD78P328GF-3BE: 64-pin plastic QFP (14 x 20 mm)

Soldering Method Soldering Conditions Recommended Soldering

Code

Infrared reflow Package peak temperature: 235˚C, IR35-207-2

Time: 30 seconds max. (210˚C min.),
Number of times: 2 max, Maximum number of days: 7 days
(thereafter, 20 hours of prebaking is required at 125˚C)
< Cautions >
(1) Wait for the device temperature to return to normal after the first

reflow before starting the second reflow.

(2) Do not perform flux cleaning with water after the first reflow.

VPS Package peak temperature: 215˚C, VP15-207-2

Time: 40 seconds max. (200˚C min.),
Number of times: 2 max, Maximum number of days: 7 days
(thereafter, 20 hours of prebaking is required at 125˚C)
< Cautions >
(1) Wait for the device temperature to return to normal after the first

reflow before starting the second reflow.

(2) Do not perform flux cleaning with water after the first reflow.

Wave soldering Soldering bath temperature: 260˚C max., Time: 10 seconds max., WS60-207-1

Number of times: 1,
Preheating temperature: 120°C max. (package surface temperature),
Maximum number of days: 7 days
prebaking is required at 125˚C).

Partial heating Pin temperature: 300˚C max., —

Time: 3 seconds max. (per pin row)

Note

(thereafter, 20 hours of

Note

Note

*

Note Number of days after unpacking the dry pack. Storage conditions are 25°C and 65% RH max.

Caution Do not use different soldering methods together (except the partial heating method).

Table 9-2. Soldering Conditions for Through-hole Devices

µ

PD78P328CW: 64-pin Plastic Shrink DIP (750 mils)

µ

PD78P328DW: 64-pin Ceramic Shrink DIP (750 mils) (with window)

Soldering Method Soldering Conditions
Wave soldering (pin only) Soldering bath temperature: 260˚C max., Time: 10 seconds max.
Partial heating Pin temperature: 300˚C max., Time: 3 seconds max. (per pin)

Caution Apply wave soldering only to the pins and be careful so as not to bring solder into direct contact

with the package.

38

µ

PD78P328

APPENDIX A. DRAWINGS OF CONVERSION SOCKET AND RECOMMENDED FOOTPRINT

*

combination with the conversion socket (EV-9200G-64).

The drawings of the socket and recommended footprint are shown below.

Figure A-1. Drawing of Conversion Socket (EV-9200G-64)

The emulation probe (EP-78327GF-R) for the µPD78P328GF-3BE is connected with the target system in

F

E

C

D

No.1 pin index

1

A

B

EV-9200G-64

(for reference only)

G

N

O P

S

K

Q

R

T

U

L

M

H

I

J

EV-9200G-64-G0

ITEM MILLIMETERS INCHES

A

B

C

D

E

F

G

H

I

J

K

L

M

O

N

P

Q

R

S

T

U

25.0

20.30

4.0

14.45

19.0

4-C 2.8

0.8

11.0

22.0

24.7

5.0

16.2

18.9

8.0

7.8

2.5

2.0

1.35

0.35±0.1

φ

2.3

φ

1.5

0.984

0.799

0.157

0.569

0.748

4-C 0.11

0.031

0.433

0.866

0.972

0.197

0.638

0.744

0.315

0.307

0.098

0.079

0.053

+0.004

0.014

–0.005

φ

0.091

φ

0.059

39

Figure A-2. Recommended Footprint for EV-9200G-64

(for reference only)

G

H

µ

PD78P328

L

F

E

D

M

C

B

A

EV-9200G-64-P0

ITEM MILLIMETERS INCHES

+0.002

–0.001

+0.002

–0.001

1.012

0.827

0.598

0.783

0.433

0.217

0.197

0.098

0.024

φ

0.093

φ

0.062

+0.004

–0.003

+0.001

–0.002

+0.003

–0.004

+0.002

–0.001

+0.001

–0.002

+0.001

–0.002

+0.001

–0.002

M

A

B

C

D

E

F

G

H

I

J

K

L

25.7

21.0

±

1.0

0.02 × 18=18.0

±

1.0

0.02 × 12=12.0

15.2

19.9

11.00±0.08

5.50±0.03

5.00±0.08

2.50±0.03

0.6±0.02

φ

2.36±0.03

φ

1.57±0.03

±

0.039 × 0.709=0.709

0.05

±

0.039 × 0.472=0.472

0.05

J

I

K

+0.002

–0.003

+0.003

–0.002

40

Caution

Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (IEI-1207).

APPENDIX B. TOOLS

*

B.1 Development Tools

The following development tools are readily available to support development of systems using the µPD78P328:

Language Processor

78K/III Series Relocatable assembler common to the 78K/III series. Since it contains the macro function, the
relocatable assembler development efficiency can be improved. A structured assembler which enables you to explicity
(RA78K/III) describe program control structure is also attached and program productivity and maintenance

78K/III Series C compiler common to the 78K/III series. This is a program to convert a program written in C
C compiler language into an object code executable with a microcontroller. When using the compiler,
(CC78K/III) 78K/III series relocatable assembler(RA78K/III) is necessary.

µ

PD78P328

can be improved.
Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS

IBM PC/AT

TM

PC DOS
and compatible machine 5-inch 2HC
HP9000 series 700
SPARCstation

TM

NEWS

TM

TM

HP-UX

SunOS

NEWS-OS

TM

TM

TM

TM

TM

3.5-inch 2HD
5-inch 2HD

3.5-inch 2HC

DAT
Cartridge tape
(QIC-24)

µ

S5A13RA78K3

µ

S5A10RA78K3

µ

S7B13RA78K3

µ

S7B10RA78K3

µ

S3P16RA78K3

µ

S3K15RA78K3

µ

S3R15RA78K3

Host machine Ordering code

OS Supply medium (product name)
PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD

IBM PC/AT

TM

PC DOS 3.5-inch 2HC
and compatible machine 5-inch 2HC
HP9000 series 700 HP-UX DAT
SPARCstation SunOS Cartridge tape
NEWS NEWS-OS (QIC-24)

µ

S5A13CC78K3

µ

S5A10CC78K3

µ

S7B13CC78K3

µ

S7B10CC78K3

µ

S3P16CC78K3

µ

S3K15CC78K3

µ

S3R15CC78K3

Remark The operation of the relocatable assembler and C compiler is guaranteed only on the host machine under

the operating systems listed above.

41

µ

PD78P328

PROM Write Tools

Hard- PG-1500 PG-1500 is a PROM programmer which enables you to program single chip micro­ware controllers containing PROM by stand-alone or host machine operation by connecting an

attached board and optional programmer adapter to PG-1500. It also enables you to

program typical PROM devices of 256K bits to 4M bits.
UNISITE PROM programmer manufactured by Data I. O. Japan.
2900
PA-78P328CW PROM programmer adapters to write programs onto the µPD78P328 on a general
PA-78P328GF purpose PROM programmer such as PG-1500.

PA-78P328CW ... µPD78P328CW and 78P328DW

PA-78P328GF ... µPD78P328GF

Soft- PG-1500 controller Connects PG-1500 and a host machine by a serial or parallel interface and controlls
ware PG-1500 on the host machine.

Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HD
and compatible machine 5-inch 2HC

µ

S5A13PG1500

µ

S5A10PG1500

µ

S7B13PG1500

µ

S7B10PG1500

Remark The operation of the PG-1500 controller is guaranteed only on the host machine under the operating

systems listed above.

Debugging Tools

Hard- IE-78327-R IE-78327-R is an in-circuit emulator that can be used for application system development
ware and debugging.

EP-78327CW-R Emulation probe for 64-pin plastic shrink DIP to connect IE-78327-R to the target system.
EP-78327GF-R Emulation probe for 94-pin plastic QFP to connect IE-78327-R to the target system.
EV-9200G-64 One conversion socket EV-9200G-64 used for connection to the target system

is attached.

Soft- IE-78327-R Program to control IE-78327-R on a host machine. Automatic execution of commands,
ware control program etc., is enabled for more efficient debugging.

(IE controller) Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HD
and compatible machine 5-inch 2HC

µ

S5A13IE78327

µ

S5A10IE78327

µ

S7B13IE78327

µ

S7B10IE78327

Remark The operation of the IE controller is guaranteed only on the host machine under the operating systems

listed above.

42

Development Tool Configuration

µ

PD78P328

Host machine
PC-9800 series or
IBM PC/AT

Software

Relocatable
assembler (with
structure assembler)

On-chip PROM version

µ

PD78P328GF

Programmer adapter

PA-78P328GF

PG-1500
controller

PD78P328CWµPD78P328DW

IE controller

µ

PA-78P328CW

RS-232C

+++

IE-78327-R
In-circuit
emulator

RS-232C

PROM
programmer

PG-1500

Emulation probe

EP-78327GF-R EP-78327GF-R

Socket to connect emulation probe and target system

+

EV-9200G-64

Target system

+

SDIP socket

Note

Note The socket is attached to the emulation probe.

Remarks 1. The host machine and PG-1500 can be connected directly by RS-232-C.

2. Supply media of software are represented as 3.5-inch floppy disks in the figure above.

43

µ

PD78P328

B.2 Evaluation Tools

The following evaluation tools are provided to evaluate the µPD78P328 function:

Ordering Code Host Machine Function
(product name)
EB-78327-98 PC-9800 series The µPD78P328 function can be easily evaluated by connecting the evaluation tool to

a host machine. The EB-78327-98/PC command system basically is compliant with the

EB-78327-PC IBM PC/AT IE-78327-R command system. Thus, easy transition to application system development

and compatible process by IE-78327-R can be made. The evaluation tools enable turbo access manager
machine (µPD71P301)

Note

to be mounted on the printed circuit board.

Note Turbo access manager (µPD71P301) is available for maintenance purpose only.

µ

Cautions 1. EB-78327-98/PC is not the

PD78P328 application system development tool.

2. EB-78327-98/PC does not contain the emulation function at internal PROM execution of the

µ

PD78P328.

B.3 Embedded Software

The following embedded software products are readily available to support more efficient program development

and maintenance:

Real-time OS

Real-time OS The purpose of RX78K/III is to realize a multi-task environment in a control area which requires
(RX78K/III) real-time processing. RX78K/III allocates idle times of CPU to other processing to improve

overall performance of the system.
RX78K/III provides a system call based on the µITRON specification.
RX78K/III assembler package provides the RX78K/III nucleus and a tool (configurator) to
prepare multiple information tables.
Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HC
and compatible machine 5-inch 2HC

µ

S5A13RX78320

µ

S5A10RX78320

µ

S7B13RX78320

µ

S7B10RX78320

Caution When purchasing the RX78K/III, fill in the purchase application form in advance, and sign the

User's Agreement.

Remark When using the RX78K/III Real-time OS, the RA78K/III assembler package (option) is necessary.

44

µ

PD78P328

Fuzzy Inference Development Support System

Fuzzy knowledge Data Program supporting input of fuzzy knowledge data (fuzzy rule and membership function),
Preparation Tool input/editing (edit), and evaluation (simulation).
(FE9000, FE9200)

Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS WindowsTM3.5-inch 2HC
and compatible machine 5-inch 2HC

Translator Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation
(FT78K3)

Fuzzy Inference Module Program executing fuzzy inference. Fuzzy inference is executed by linking fuzzy knowledge
(FI78K/III)

Fuzzy Inference Debugger Support software evaluating and adjusting fuzzy knowledge data at hardware level by using
(FD78K/III) in-circuit emulator.

Note

Note

tool to the assembler source program for the RA78K/III.
Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HC
and compatible machine 5-inch 2HC

data converted by translator.
Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HC
and compatible machine 5-inch 2HC

Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HC
and compatible machine 5-inch 2HC

µ

S5A13FE9000

µ

S5A10FE9000

µ

S7B13FE9200

µ

S7B10FE9200

µ

S5A13FT78K3

µ

S5A10FT78K3

µ

S7B13FT78K3

µ

S7B10FT78K3

µ

S5A13FI78K3

µ

S5A10FI78K3

µ

S7B13FI78K3

µ

S7B10FI78K3

µ

S5A13FD78K3

µ

S5A10FD78K3

µ

S7B13FD78K3

µ

S7B10FD78K3

Note Under development

45

[MEMO]

CHAPTER 2 PIN FUNCTIONS

46

µ

NOTES FOR CMOS DEVICES

(1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate

oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it once,
when it has occurred. Environmental control must be adequate. When it is dry,
humidifier should be used. It is recommended to avoid using insulators that easily
build static electricity. Semiconductor devices must be stored and transported in an
anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.

(2) HANDLING OF UNUSED INPUT PINS FOR CMOS

PD78P328

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection

is provided to the input pins, it is possible that an internal input level may be generated
due to noise, etc., hence causing malfunction. CMOS devices behave differently than
Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by
using a pull-up or pull-down circuitry. Each unused pin should be connected to V
or GND with a resistor, if it is considered to have a possibility of being an output pin.
All handling related to the unused pins must be judged device by device and related
specifications governing the devices.

(3) STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device. Immediately
after the power source is turned ON, the devices with reset function have not yet been
initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or
contents of registers. Device is not initialized until the reset signal is received. Reset
operation must be executed immediately after power-on for devices having reset
function.

DD

QTOP is a trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.

TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.

47

µ

PD78P328

The export of these products from Japan is regulated by the Japanese government. The export of some
or all of these products may be prohibited without governmental license. To export or re-export some or
all of these products from a country other than Japan may also be prohibited without a license from that
country. Please call an NEC sales representative.

µ

License not needed:
The customer must judge the need for license: µPD78P328CW, 78P328GF-3BE

PD78P328DW

No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use of
such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property
arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in
its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computer, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for
life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support

systems or medical equipment for life support, etc.
The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they
should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.

M4 94.11