Datasheet UPD78F9177YGB-8ES, UPD78F9177YGA-9EU, UPD78F9177GB-8ES Datasheet (NEC)

DATA SHEET

µµµµ

Y

MOS INTEGRATED CIRCUIT

PD78F9177, 78F9177

8-BIT SINGLE-CHIP MICROCONTROLLER

The µPD78F9177 and µPD78F9177Y are µPD789177, 789177Y Subseries (small, general-purpose) in the 78K/0S

Series.

The µPD78F9177 replaces the internal ROM of the µPD789176 and µPD789177 with flash memory, while the

PD78F9177Y replaces the ROM of the µPD789176Y and µPD789177Y with flash memory.

µ

Because flash memory allows the program to be written and erased electrically with the device mounted on the
board, this product is ideal for the evolution stages of system development, small-scale production and rapid
development of new products.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.

µ

PD789167, 789177, 789167Y, 789177Y Subseries User’s Manual: U14186E

78K/0S Series User's Manual Instruction: U11047E

FEATURES

• Pin compatible with mask ROM version (except V

• Flash memory: 24 Kbytes

• High-speed RAM: 512 bytes

• Minimum instruction execution time can be changed from high-speed (0.4 µs: @5.0-MHz operation with main

system clock) to ultra-low-speed (122 µs: @ 32.768-kHz operation with subsystem clock)

• 10-bit resolution A/D converter: 8 channels

• I/O ports: 31

• Serial interface: 2 channels

3-wire serial I/O mode / UART mode: 1 channel

•

SMB (µPD78F9177Y only): 1 channel

•

• Timers: 6 channels

16-bit timer: 1 channel

•

8-bit timer/event counter: 2 channels

•

8-bit timer: 1 channel

•

Watch timer: 1 channel

•

Watchdog timer: 1 channel

•

• On-chip 16-bit multiplier

• Power supply voltage: VDD = 1.8 to 5.5 V

PP

pin)

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. U14022EJ1V0DS00 (1st edition)
Date Published August 2000 NS CP(K)
Printed in Japan

The mark shows major revised

©

2000

APPLICATIONS

Power windows, battery management unit, side air bags, etc

ORDERING INFORMATION

(1)

PD78F9177

µµµµ

Part Number Package

PD78F9177GB-8ES 44-pin plastic QFP (10 × 10)

µ

(2)

PD78F9177Y

µµµµ

Part Number Package

PD78F9177YGB-8ES 44-pin plastic LQFP (10 X 10)

µ

PD78F9177YGA-9EU 48-pin plastic TQFP (fine pitch) (7 X 7)

µ

µµµµ

PD78F9177, 78F9177Y

2

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

78K/0S SERIES DEVELOPMENT

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

Products under mass production

Products under development

Y subseries supports SMB.

Small, general-purpose

PD789046 PD789026 with subsystem clock added

44 pins
42/44 pins
28 pins

Small, general-purpose + A/D

44 pins
44 pins
30 pins
30 pins
30 pins
30 pins
30 pins
30 pins

µ

PD789026

µ

PD789014

µ

PD789177

µ

PD789167

µ

PD789156

µ

PD789146

µ

PD789134A

µ

PD789124A

µ

PD789114A

µ

PD789104A

µ

PD789177Y

µ

PD789167Y

µ

µ
µ

PD789014 with timer reinforced and ROM and RAM expanded

UART. Low-voltage (1.8-V) operation

PD789167 with improved A/D

µ
µ

PD789104A with improved timer
PD789146 with improved A/D

µ
µ

PD789104A with EEPROM added
PD789124A with improved A/D

µ

RC oscillation model of PD789104A

µ

PD789104A with improved A/D
PD789026 with A/D and multiplier added

µ

µ

78K/0S
series

For inverter control

44 pins

For driving LCD

80 pins
80 pins
64 pins
64 pins
64 pins
64 pins
64 pins
64 pins

For driving Dot LCD

144 pins
88 pins

For ASSP

52 pins
52 pins
44 pins
44 pins
20 pins
20 pins

PD789842

µ

PD789417A

µ

PD789407A

µ

PD789456

µ

PD789446

µ

PD789436

µ

PD789426

µ

PD789316

µ

PD789306

µ

PD789835

µ

PD789830

µ

PD789467

µ

PD789327

µ

PD789800

µ

PD789840

µ

PD789861

µ

PD789860

µ

Internal inverter control circuit and UART

PD789407A with improved A/D

µ
µ

PD789456 with improved I/O

µ

PD789446 with improved A/D
PD789426 with improved display output

µ
µ

PD789426 with improved A/D
PD789306 with A/D added

µ

RC oscillation model of PD789306
Basic subseries for driving LCD

Segment/common output: 96 pins
Segment: 40 pins, common: 16 pins

PD789327 with A/D added

µ

For remote controller. Internal LCD controller/driver
For PC keyboard. Internal USB function
For key pad. Internal POC
RC oscillation model of PD789860
For keyless entry. Internal POC and key return circuit

µ

µ

Data Sheet U14022EJ1V0DS00

3

The major differences between subseries are shown below.

Function

Subseries Name
Small,

general­purpose

PD789046 16 K 1 ch

µ

PD789026 4 K-16 K

µ

PD789014 2 K-4 K 2 ch

µ

ROM

Capacity

8-bit 16-bit Watch WDT

1 ch 1 ch 34 pins

Timer

1 ch

−

−

8-bit

10-bit

A/D

A/D

−−

µµµµ

PD78F9177, 78F9177Y

Serial Interface I/O

1 ch (UART:1 ch)

22 pins

DD

V

MIN

Value

1.8 V

Remark

−

Small,
general­purpose
+ A/D

For
inverter
control

For LCD
driving

PD789177

µ

PD789167

µ

PD789156

µ

PD789146

µ

PD789134A

µ

PD789124A

µ

PD789114A

µ

PD789104A

µ

PD789842 8 K-16 K 3 ch

µ

µ

PD789417A

µ

PD789407A
PD789456

µ

PD789446 6 ch

µ

PD789436

µ

PD789426

µ

PD789316

µ

PD789306

µ

16 K-24 K 3 ch 1 ch

8 K-16 K

2 K-8 K

12 K-24 K 3 ch

12 K-16 K

8 K to
16K

1 ch

1 ch

Note

1 ch 1 ch 1 ch

2 ch

−

1 ch 1 ch 8 ch

1 ch

−

8 ch

−

4 ch

4 ch

−

4 ch

7 ch

−

−

6 ch

−

8 ch

1 ch (UART: 1 ch)

−

4 ch

−

4 ch

−

4 ch

−

1 ch (UART: 1 ch) 30 pins 4.0 V

−

1 ch (UART: 1 ch)

7 ch

−

6 ch

−

6 ch

−

2 ch (UART: 1 ch) 23 pins

31 pins

20 pins

43 pins

30 pins

40 pins

1.8 V

1.8 V

−

Internal
EEPROM

RC oscillation
version

−

−

−

RC oscillation
version

−

LCD
driving

ASSP

Note

4

PD789835 24 K-60 K 6 ch

µ

PD789830 24 K 1 ch 1 ch

µ

PD789467 1 ch

µ

PD789327

µ

PD789800

µ

PD789840

µ

PD789861

µ

PD789860

µ

4 K-24 K 2 ch

8 K 1 ch

4 K

2 ch

−

−

−

1 ch 1 ch

1 ch 1 ch

1 ch

−

10-bit timer: 1 channel

Data Sheet U14022EJ1V0DS00

3 ch 28 pins 1.8 VFor Dot

−

−

−

4 ch 1 ch 29 pins 2.8 V

−

1 ch

−

30 pins 2.7 V

−

1 ch 21 pins
2 ch (USB: 1 ch) 31 pins 4.0 V

−

−

18 pins

14 pins 1.8 V

1.8 V Internal

−

LCD

−

RC oscillation
version,
Internal
EEPROM

Internal
EEPROM

OVERVIEW OF FUNCTIONS

µµµµ

PD78F9177, 78F9177Y

Item

Flash memory 24 KbytesInternal memory
High-speed RAM 512 bytes

Minimum instructi on execution time • 0.4/1.6 µs (@5.0-MHz operation with main system clock)

• 122
General-purpose registers 8 bits × 8 registers
Instruction set • 16-bit operations

• Bit manipulations (set, reset, test)
Multiplier 8 bits × 8 bits = 16 bits
I/O ports Total: 31

• CMOS input: 8

• CMOS I/O: 17

• N-ch open drain: 6
A/D converters 10-bit resolution × 8 channels
Serial interfaces 3-wire serial I/O/UART : 1 c hannel

Timers • 16-bit timer:1 channel

• 8-bit timer/event counter:2 channels

• 8-bit timer:1 channel

• Watch timer:1 channel

• Watchdog timer:1 channel
Timer output 4 output
Buzzer output 1
Vectored interrupt
sources

Non-maskable Internal: 1
Power supply voltage VDD = 1.8 to 5.5 V
Operating ambient temperature TA = −40°C to +85°C
Package 44-pin plastic LQFP (10 × 10)

Internal: 10, External: 4
Internal: 12, External: 4

PD78F9177

µ

s (@ 32.768-kHz operation with s ubsystem clock)

µ

•

3-wire serial I/O / UART: 1 channel

• SMB: 1 channel

PD78F9177)Maskable

(µ

PD78F9177Y)

(µ

•

44-pin plastic LQFP (10 X10)

•

48-pin plastic TQFP (fine pitch) (7 x 7)

PD78F9177Y

µ

Data Sheet U14022EJ1V0DS00

5

µµµµ

PD78F9177, 78F9177Y

CONTENTS

1. PIN CONFIGURATION (TOP VIEW)................................................................................................. 7

2. BLOCK DIAGRAM............................................................................................................................. 10

3. PIN FUNCTIONS................................................................................................................................ 11

3.1 Port Pins.................................................................................................................................................. 11

3.2 Non-Port Pins.......................................................................................................................................... 12

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins...................................................... 13

4. CPU ARCHITECTURE....................................................................................................................... 15

5. FLASH MEMORY PROGRAMMING ................................................................................................ 16

5.1 Selecting Communication Mode .......................................................................................................... 16

5.2 Function of Flash Memory Programming ............................................................................................ 17

5.3 Flashpro III Connection Example ......................................................................................................... 17

5.4 Example of Settings for Flashpro III (PG-FP3) .................................................................................... 19

6. INSTRUCTION SET OVERVIEW ...................................................................................................... 20

6.1 Conventions ........................................................................................................................................... 20

6.2 Operations .............................................................................................................................................. 22

7. ELECTRICAL SPECIFICATIONS...................................................................................................... 27

8. CHARACTERISTICS CURVES ........................................................................................................ 45

9. PACKAGE DRAWING ...................................................................................................................... 46

10. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 48

APPENDIX A. DIFFERENCES BETWEEN

PD78F9177, 78F9177Y, AND MASK ROM VERSIONS...... 49

µµµµ

APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 50

APPENDIX C. RELATED DOCUMENTS............................................................................................... 52

6

Data Sheet U14022EJ1V0DS00

1. PIN CONFIGURATION (TOP VIEW)

µµµµ

PD78F9177, 78F9177Y

• 44-pin plastic LQFP (10

PD78F9177GB-8ES

µ

PD78F9177YGB-8ES

µ

P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
P66/ANI6
P67/ANI7

AV

SS

P10
P11

××××

10)

REFAVDD

AV

P53

P52

P51

P50

44 43 42 41 40 39 38 37 36 35 34

1
2
3
4
5
6
7
8

9
10
11

12 13 14 15 16 17 18 19 20 21 22

P05

SS1

V

P04

P03

P02

33
32
31
30
29
28
27
26
25
24
23

P01
P00
P26/TO80
P25/TI80/SS20

DD0

V
VSS0
X1
X2
RESET
XT1
XT2

Note

The SCL0 and SDA0 pins are available in

Cautions 1. Connect the V

2. Connect the AVDD pin to V

3. Connect the AVSS pin to V

P31/INTP1/TO81

P32/INTP2/TO90

P30/INTP0/TI81/CPT90

PP

pin directly to V

P33/INTP3/TO82/BZO90

DD0

SS0

DD1

V

Note

D20

X

Note

D20

X

P23/SCL0

P22/SI20/R

P21/SO20/T

P24/SDA0

P20/SCK20/ASCK20

PD78F9177Y product only.

µ

SS0

or V

SS1

.

.

.

PP

V

Data Sheet U14022EJ1V0DS00

7

µµµµ

PD78F9177, 78F9177Y

• 44-pin plastic QFP (fine pitch) (7

PD78F9177YGA-9EU

µ

P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
P66/ANI6
P67/ANI7

AV

SS

P10
P11

IC2

10
11
12

7)

××××

REFAVDD

AV

P53

P52

IC0

P51

4847 46 45444342 41 403938 37

1
2
3
4
5
6
7
8
9

1314 15 16171819 20 212223 24

DD1

V

P50

IC2

P05

SS1

V

P04

P03

P02

36
35
34
33
32
31
30
29
28
27
26
25

PP

V

P01
P00
P26/TO80
P25/Tl80/SS20
V

DD0

IC2
V

SS0

X1
X2
RESET
XT1
XT2

Cautions 1. Connect the V

2. Connect the IC0 (Internally Connected) pin directly to V

3. Leave the IC2 pin open.

4. Connect the AV

5. Connect the AV

P31/INTP1/TO81

P32/INTP2/TO90

P30/INTP0/Tl81/CPT90

PP

pin directly to the V

DD

pin to V

SS

pin to V

P33/INTP3/TO82/BZO90

DD0

.

SS0

.

P23/SCL0

P24/SDA0

P22/Sl20/RxD20

P21/SO20/TxD20

P20/SCK20/ASCK20

SS0

or V

SS1

pin in normal operation mode.

SS0

SS1

or V

.

8

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

ANI0 to ANI7: Analog Input RESET: Reset
ASCK20: Asynchronous Serial Input RxD20: Receive Data

DD

AV

: Analog Power Supply SCK20: Serial Clock (for SIO20)

REF

AV

: Analog Reference Voltage SCL0

SS

AV

: Analog Ground SDA0

Note2

: Serial Clock (for SMB0)

Note2

: Serial Data
BZO90: Buzzer Output SI20: Serial Input
CPT90: Capture Trigger Input SO20: Serial Output
IC0

Note1

,IC2

Note2

: Internally Connected SS20: Chip Select Input
INTP0 to INTP3: Interrupt from Peripherals TI80, TI81: Timer Input
P00 to P05: Port 0 TO80 to TO82, TO90: Timer Output
P10, P11: Port 1 TxD20: Transmit Data

DD0

P20 to P26: Port 2 V
P30 to P33: Port 3 V
P50 to P53: Port 5 V

DD1

, V

: Power Supply

PP

: Programming Power Supply

SS0

SS1

, V

: Ground

P60 to P67: Port 6 X1, X2: Crystal (Main System Clock)

XT1, XT2: Crystal (Subsystem Clock)

Notes 1.

2.

The IC0 pin is available in 48-pin plastic TQFP (fine pitch) only.
The IC2, SCL0, and SDA0 pins are available in

PD78F9177Y product only.

µ

Data Sheet U14022EJ1V0DS00

9

2. BLOCK DIAGRAM

µµµµ

PD78F9177, 78F9177Y

TI80/SS20/P25

TO80/P26

TI81/INTP0/CPT90/P30

TO81/INTP1/P31

TO82/INTP3/BZO90/P33

CPT90/INTP0/TI81/P30

TO90/INTP2/P32

BZO90/INTP3/TO82/P33

SCK20/ASCK20/P20

SO20/T

X

D20/P21

SI20/RXD20/P22

SS20/TI80/P25

SCL0/P23
SDA0/P24

ANI0/P60-

ANI7/P67

AV
AV

AV

REF

8-BIT TIMER/
EVENT COUNTER80

8-BIT TIMER/
EVENT COUNTER81

8-BIT TIMER82

16-BIT TIMER90

WATCH TIMER

WATCHDOG TIMER

DD
SS

SIO20

Note1

SMB

A/D

CONVERTER

78K/0S

CPU CORE

RAM

ROM

PORT0

PORT1

PORT2

PORT3

PORT5

PORT6

SYSTEM

CONTROL

INTERRUPT

CONTROL

P00-P05

P10, P11

P20-P26

P30-P33

P50-P53

P60-P67

RESET
X1
X2
XT1
XT2

INTP0/TI81/CPT90/P30
INTP1/TO81/P31
INTP2/TO90/P32
INTP3/TO82/BZO90/P33

Notes 1.

MULTIPLIER

SMB is available in

The IC0 pin is available in 48-pin plastic TQFP (fine pitch) only.

2.

The IC2 pin is available in

3.

PD78F9177Y product only.

µ

PD78F9177Y product only.

µ

V

DD0

V

SS0

V

PP

IC0
IC2

Note2
Note3

V

SS1

V

DD1

10

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

3. PIN FUNCTIONS

3.1 Port Pins

Pin Name I/O Function After Reset Alternate Function

P00 to P05 I/O Port 0

6-bit input/output port
Input/output mode can be specified in 1-bit units
When used as an input port, an on-chip pull -up resistor can be
specified by soft ware.

P10, P11 I/O Port 1

2-bit input/output port
Input/output mode can be specified in 1-bit units
When used as an input port, an on-chip pull -up resistor can be

specified by soft ware.
P20 SCK20/ASCK20
P21 SO20/TxD20
P22 SI20/RxD20
P23
P24
P25 TI80/SS20
P26
P30 INTP0/TI81/CPT90
P31 INTP1/TO81
P32 INTP2/TO90
P33

I/O Port 2

7-bit input/output port

Input/output mode can be specified in 1-bit units

For P20 to P22, P25, and P26, an on-c hi p pul l -up resistor can be

specified by soft ware.

Only P23 and P24 can be used as N-ch open-drai n

input/output port pins.

I/O Port 3

4-bit input/output port

Input/output mode can be specified in 1-bit units

On-chip pull-up resistor can be s pecified by software.

Input

Input

Input

Input

−

−

Note

SCL0

Note

SDA0

TO80

INTP3/TO82/BZO90

P50 to P53 I/O Port 5

4-bit N-ch open-drain input/output port

Input/output mode can be specified in 1-bit units
P60 to P67 Input Port 6

8-bit input-only port

PD78F9177Y only

µ

Note

Input

Input ANI0 to ANI7

−

Data Sheet U14022EJ1V0DS00

11

µµµµ

PD78F9177, 78F9177Y

3.2 Non-Port Pins

Pin Name I/O Function After Reset Alternate Function
INTP0 P30/TI81/CPT90
INTP1 P31/TO81

Input External interrupt input for which t he valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified

INTP2 P32/TO90
INTP3
SI20 Input Serial data input to serial interface Input P22/RxD20
SO20 Output Serial data output from serial interface Input P21/TxD20
SCK20 I/O Serial clock i nput /output for serial interface Input P20/ASCK20
SS20 Input Chip select input to serial int erface Input P25/TI80
ASCK20 Input Serial clock input for asynchronous serial i nterface Input P20/SCK20
RxD20 Input Serial data input for asynchronous serial interface Input P22/SI20
TxD20 Output S eri al data output for asynchronous s eri al i nt erface Input P21/SO20
SCL0
SDA0

Note1

Note1

I/O SMB0 clock input/output Input P23

I/O SMB0 data input/output Input P24
TI80 Input External count clock input to 8-bit ti mer/event counter (TM80) Input P25/SS20
TI81 Input External count clock input to 8-bit ti mer/event counter (TM81) Input P30/INTP0/CPT90
TO80 Output 8-bit timer/event count er (TM 80) output Input P26
TO81 Output 8-bit timer/event count er (TM 81) output Input P31/INTP1
TO82 Output 8-bit timer (TM82) output Input P33/INTP3/BZO90
TO90 Output 16-bit timer (TM90) output Input P32/INTP2
BZO90 Output 16-bit tim er (TM 90) Buzzer output Input P33/INTP3/TO82
CPT90 Input Capture edge input Input P30/INTP0/TI81
ANI0 to

Input A/D c onverter analog input Input P60 to P67

ANI7

REF

AV

SS

AV

DD

AV
X1 Input
X2
XT1 Input
XT2

DD0

V

DD1

V

SS0

V

SS1

V

A/D converter reference v ol t age

−

A/D converter ground potential

−

A/D converter analog power supply

−

Connecting crystal res onator for main system clock
oscillation

−

Connecting crystal res onator for subsystem clock oscillation

−

Positive power supply

−

Positive power supply (other than ports)

−

Ground potential

−

Ground potential (other than ports)

−

RESET Input System reset input Input
V

IC0

IC2

PP

Note2

Note1

Sets flash memory programming mode. Applies high vol t age

−

when a program is written or verifi ed. Connect directly to V

SS1

or V

in normal operation mode.

Internally connected. Connect this pin directly to the V

−

SS1

V

pin.

Internally connected. Leave this pin open.

−

SS0

SS0

or

Input

P33/TO82/BZO90

−−

−−

−−

−−

−−

−−

−−

−−

−−

−−

−−

−

−−

−−

−−

Notes 1.

12

PD78F9177Y only.

µ

2.

48-pin plastic TQFP (fine pitch) only.

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins is shown in Table 3-1.
For the input/output circuit configuration of each type, refer to Figure 3-1.

Table 3-1. Type of I/O Circuit for Each Pin and Connection of Unused Pins

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pi ns

DD0

, V

DD0

DD0

SS0

DD0

, V

or V

, V

or V

or V

SS1

DD1

or V

DD1

DD1

or V

SS1

DD1

.

Input: Independently connects to V

P00 to P05
P10, P11
P20/SCK20/ASCK20

5-H

8-C

I/O

via a resistor.

Output: Leave open.

P21/SO20/TxD20
P22/SI20/RxD20
P23/SCL0
P24/SDA0

Note1

Note1

13-X Input: Independentl y connects to V

resistor.

Output: Leave open.
P25/TI80/SS20
P26/TO80

P30/INTP0/TI81/CPT90
P31/INTP1/TO81
P32/INTP2/TO90

8-C

Input: Independently connects to V

via a resistor.

Output: Leave open.

Input: Independently connects to V

resistor.

Output: Leave open.

P33/INTP3/TO82/BZO90
P50 to P53 13-T

Input: Independently connects to V

resistor.

Output: Leave open.
P60/ANI0 to P67/ANI7 9-C Input Connect directly to V
XT1 Input Connect to V
XT2

−

Leave open.

−

SS0

or V

RESET 2 Input

PP

V
IC0
IC2

Note2

Note1

−−

Connect directly to V

Leave open.

SS1

DD0

SS0

, V

.

or V

DD1

or V

−

SS1

SS0

.

SS0

via a

SS0

via a

via a

, V

, V

SS1

SS1

Notes 1.

The IC2, SCL0, and SDA0 pins are available in

2.

48-pin plastic TQFP (fine pitch) only.

Data Sheet U14022EJ1V0DS00

PD78F9177Y product only.

µ

13

Figure 3-1. Pin Input/Output Circuits

µµµµ

PD78F9177, 78F9177Y

Type 2

IN

Schmitt-triggered input with hysteresis characteristics

Type 5-H

Pull-up
enable

Data

V

DD0

P-ch

V

DD0

P-ch

IN/OUT

Output
disable

N-ch

V

SS0

Input
enable

Type 9-C

IN

P-ch

N-ch

AV

SS

Comparator

V

REF

+

−

(Threshold voltage)

Type 13-T

Output data

Output disable

V

N-ch

SS0

Input enable

Input buffer with intermediate withstand voltage

Input
enable

IN/OUT

Type 8-C

Pull-up
enable

Data

Output
disable

DD0

V

Type 13-X

P-ch

IN/OUT

V

DD0

P-ch

Output data

Output disable

N-ch

V

SS0

IN/OUT

N-ch

V

SS0

Input buffer with 5-V
withstand voltage

Comparator

14

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

4. CPU ARCHITECTURE

Products in the µPD78F9177 and µPD78F9177Y can access up to 64 Kbytes of memory space.
Figure 4-1 shows the memory map.

Figure 4-1. Memory Map

FFFFH

Special function registers

256 × 8 bits

FF00H
FEFFH

Internal high-speed RAM

512 × 8 bits

FD00H

Data memory space

FCFFH

6000H
5FFFH

Reserved

5FFFH

Program memory
space

0000H

Internal flash memory

24576 x 8 bits

0080H
007FH

0040H
003FH

0024H
0023H

0000H

Program area

CALLT table area

Program area

Vector table area

Data Sheet U14022EJ1V0DS00

15

µµµµ

PD78F9177, 78F9177Y

5. FLASH MEMORY PROGRAMMING

The on-chip program memory in the µPD78F9177 and µPD78F9177Y is flash memory.

The flash memory can be written with the µPD78F9177 and µPD78F9177Y mounted on the target system (on­board). Connect the dedicated flash programmer (Flashpro III (part number: FL-PR3, PG-FP3)) to the host machine
and target system to write the flash memory.

Remark

FL-PR3 is made by Naito Densei Machida Mfg. Co., Ltd.

5.1 Selecting Communication Mode

The flash memory is written by using Flashpro III and by means of serial communication. Select a communication
mode from those listed in Table 5-1. To select a communication mode, the format shown in Figure 5-1 is used. Each
communication mode is selected by the number of V

PP

pulses shown in Table 5-1.

Table 5-1. Communication Mode

Communication Mode P i ns Used Number of V
3-wire serial I/O SCK20/ASCK20/P20

SO20/TxD20/P21
SI20/RxD20/P22

Note1

SMB

UART TxD20/SO20/P21

Pseudo 3-wire mode

Note2

SCL0/P23
SDA0/P24

RxD20/SI20/P22
P00 (Serial clock input)
P01 (Serial data output)
P02 (Serial data input)

0

4

8

12

PP

Pulses

Notes 1.

PD78F9177Y only

µ

Serial transfer is performed by controlling a port by software.

2.

Caution Be sure to select a communication mode based on the V

Figure 5-1. Communication Mode Selection Format

10 V

V

DD

V

PP

V

SS

V

RESET

16

DD

V

SS

Data Sheet U14022EJ1V0DS00

PP

pulse number shown in Table 5-1.

12 n

µµµµ

PD78F9177, 78F9177Y

5.2 Function of Flash Memory Programming

By transmitting/receiving commands and data in the selected communication mode, operations such as writing to

the flash memory are performed. Table 5-2 shows the major functions of flash memory programming.

Table 5-2. Functions of Flash Memory Programming

Function Description
Batch erase Erases all contents of memory
Batch blank check Checks erased state of entire memory
Data write Write to flash memory based on write start address and number of data written

(number of bytes)

Batch verify Compares all contents of memory with input data

5.3 Flashpro III Connection Example

How the Flashpro III is connected to the

PD78F9177 and µPD78F9177Y differs depending on the communication

µ

mode (3-wired serial I/O, SMB, UART, or pseudo 3-wire mode). Figures 5-2 to 5-5 show the connection in the
respective mode.

Figure 5-2. Flashpro III Connection in 3-wired Serial I/O Mode

µ

PD78F9177, 78F9177Y

V

PP

V

DD0

, V

DD1

, AV

RESET

SCK20
SI20
SO20
V

SS0

, V

SS1

, A

Note

Flashpro III

n = 1, 2

Note

VPPn

V

DD

RESET

CLK X1

SCK

SO

SI

GND

DD

VSS

Data Sheet U14022EJ1V0DS00

17

Figure 5-3. Flashpro III Connection in SMB Mode

Flashpro III

Note

VPPn

V

DD

V

PP

V

DD0

µµµµ

µ

PD78F9177Y

, V

DD1

, AV

PD78F9177, 78F9177Y

DD

Note

RESET

RESET

CLK X1

SO

SI

GND

SCL0
SDA0

SS0

V

n = 1, 2

Figure 5-4. Flashpro III Connection in UART Mode

Flashpro III

Note

VPPn

V

RESET

CLK

SO

DD

SI

µ

PD78F9177, 78F9177Y

V

PP

V

DD0

RESET
X1
RxD20

TxD20

, V

, V

SS1

DD1

, AV

, AV

SS

DD

Note

GND

n = 1, 2

SS0

, V

SS1

, AV

V

SS

Figure 5-5. Flashpro III Connection in Pseudo Serial I/O Mode (When Port 0 is Used)

µ

PD78F9177, 78F9177Y

V

PP

V

DD0

, V

DD1

, AV

DD

RESET
X1
P00 (Serial clock)
P02 (Serial input)
P01 (Serial output)

V

SS0

, V

SS1

, AV

SS

Note

Flashpro III

n = 1, 2

Note

VPPn

V

RESET

CLK

SCK

SO

GND

DD

SI

18

Data Sheet U14022EJ1V0DS00

5.4 Example of Settings for Flashpro III (PG-FP3)

Set as follows when writing to flash memory using the Flashpro III (PG-FP3).

Download the parameter file.

<1>

Select the serial mode and the serial clock using the type command.

<2>

The following is a setting example using the PG-FP3.

<3>

µµµµ

PD78F9177, 78F9177Y

Table 5-3. Example Using PG-FP3

Communication mode Setting example using PG-FP3 Number of V

3-wired serial I/O mode

COMM PORT SIO ch-0

0
On target boardCPU CLK
In Flashpro

On target board 4.1943 MHz
SIO CLK 1.0 MHz
In Flashpro 4.0 MHz
SIO CLK 1.0 MHz

SMB

Note2

COMM PORT IIC-ch0

4

SLAVE ADDRESS 10H
IIC CLOCK 100 kHz
CPU CLOCK In Flashpro
Flashpro Clock 4.0 MHz

Note3

Multiple Rate 01.00

UART

COMM PORT UART-ch0

8

CPU CLK On target board
On target board 4.1943 MHz

Note4

12

Pseudo 3-wire mode

UART BPS 9600 bps
COMM PORT Port A

On target boardCPU CLK
In Flashpro

On target board 4.1943 MHz
SIO CLK 1.0 MHz
In Flashpro 4.0 MHz
SIO CLK 1.0 MHz

pulses

PP

Note1

Notes 1.

Remark

PP

The number of V

pulses supplied from the Flashpro III during serial communication initialization.

The pins to be used in communication are determined by this number of pulses.

PD78F9177Y only.

2.

µ

Select one of 4.0 MHz or 3.125 MHz.

3.

Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps.

4.

COMM PORT : Selection of serial port
SIO CLK : Selection of serial clock frequency
CPU CLK : Selection of CPU clock source to be input

Data Sheet U14022EJ1V0DS00

19

µµµµ

PD78F9177, 78F9177Y

6. INSTRUCTION SET OVERVIEW

This section lists the µPD78F9177 and µPD78F9177Y instruction set.

6.1 Conventions

6.1.1 Operand identifiers and description methods

Operands are described in the “Operand” column of each instruction in accordance with the description method of
the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more
description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords
and must be described as they are. Each symbol has the following meaning.

#: Immediate data specification

•

!: Absolute address specification

•

$: Relative address specification

•

[ ]: Indirect address specification

•

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #,!, $, or [ ] symbols.

For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.

Table 6-1. Operand Identifiers and Description Methods

Identifier Description Method

r
rp
sfr

saddr
saddrp

addr16

addr5
word

byte
bit

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),
AX (RP0), BC (RP1), DE (RP 2), HL (RP3)
Special function regis ter symbol

FE20H to FF1FH immediate data or label
FE20H to FF1FH immediate data or label (ev en address only)

0000H to FFFFH immediate data or label
(Only even addresses for 16-bit data transfer instructi ons)
0040H to 007FH immediate data or label (even address only)

16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label

20

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

6.1.2 Descriptions of the operation field

A: A register; 8-bit accumulator
X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair; 16-bit accumulator
BC: BC register pair
DE: DE register pair
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carry flag
Z: Zero flag
IE: Interrupt request enable flag
NMIS: Non-maskable interrupt servicing flag
( ): Memory contents indicated by address or register contents in parentheses

H

, XL: Higher 8 bits and lower 8 bits of 16-bit register

X

: Logical product (AND)

∧

: Logical sum (OR)

∨

: Exclusive OR

∨

: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)

6.1.3 Description of the flag operation field

(Blank): Not affected
0: Cleared to 0
1: Set to 1

: Set/cleared according to the result

×

R: Previously saved value is restored

Data Sheet U14022EJ1V0DS00

21

6.2 Operations

µµµµ

PD78F9177, 78F9177Y

Mnemonic Operand Bytes Clock Operation

MOV r. #byte 3 6 r ← byte

saddr, #byte 3 6 (saddr) ← byte
sfr, #byte 3 6 sfr ← byte

Note 1

A, r

Note 1

r, A
A, saddr 2 4 A ← (saddr)
saddr, A 2 4 (saddr) ← A
A, sfr 2 4 A ← sfr
sfr, A 2 4 sfr ← A
A, !addr16 3 8 A ← (addr16)
!addr16, A 3 8 (addr16) ← A
PSW, #byte 3 6 PSW ← byte
A, PSW 2 4 A ← PSW
PSW, A 2 4 PSW ← A
A, [DE] 1 6 A ← (DE)
[DE], A 1 6 (DE) ← A
A, [HL] 1 6 A ← (HL)
[HL], A 1 6 (HL) ← A
A, [HL + byte] 2 6 A ← (HL + byte)
[HL + byte], A 2 6 (HL + byte) ← A

XCH A, X 1 4 A ←→ X

Note 2

A, r
A, saddr 2 6 A ←→ (saddr)
A, sfr 2 6 A ←→ (sfr)
A, [DE] 1 8 A ←→ (DE)
A, [HL] 1 8 A ←→ (HL)
A, [HL + byte] 2 8 A ←→ (HL+byte)

MOVW rp, #word 3 6 rp ← word

AX, saddrp 2 6 AX ← (saddrp)
saddrp, AX 2 8 (saddrp) ← AX

Note 3

AX, rp

Note 3

rp, AX

24A
24r

26A ←→ r

1 4 AX ← rp
14rp

r

←

A

←

AX

←

Flags

ZACCY

×××

×××

Notes 1.

Remark

22

Except r = A
Except r = A, X

2.

Only when rp = BC, DE, HL

3.

One clock of an instruction is one clock of the CPU clock (f
control register (PCC).

Data Sheet U14022EJ1V0DS00

CPU

) selected using the processor clock

µµµµ

PD78F9177, 78F9177Y

Mnemonic Operand Bytes Clock Operation

Note

XCHW
ADD A, #byte 2 4 A, CY ← A + byte

ADDC A, #byte 2 4 A, CY ← A + byte + CY

SUB A, #byte 2 4 A, CY ← A – byte

SUBC A, #byte 2 4 A, CY ← A – byte – CY

AX, rp

saddr, #byte 3 6 (saddr), CY ← (saddr) + byte
A, r 2 4 A, CY ← A + r
A, saddr 2 4 A, CY ← A + (saddr)
A, !addr16 3 8 A, CY ← A + (addr16)
A, [HL] 1 6 A, CY ← A + (HL)
A, [HL + byte] 2 6 A, CY ← A + (HL + byte)

saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY
A, r 2 4 A, CY ← A + r + CY
A, saddr 2 4 A, CY ← A+ (saddr) + CY
A, !addr16 3 8 A, CY ← A+ (addr16) +CY
A, [HL] 1 6 A, CY ← A + (HL) + CY
A, [HL + byte] 2 6 A, CY ← A+ (HL + byte) + CY

saddr, #byte 3 6 (saddr), CY ← (saddr) – byte
A, r 2 4 A, CY ← A – r
A, saddr 2 4 A, CY ← A – (saddr)
A, !addr16 3 8 A, CY ← A – (addr16)
A, [HL] 1 6 A, CY ← A – (HL)
A, [HL + byte] 2 6 A, CY ← A – (HL + byte)

saddr, #byte 3 6 (saddr), CY ← (saddr) – byte – CY
A, r 2 4 A, CY ← A – r – CY
A, saddr 2 4 A, CY ← A – (saddr) – CY
A, !addr16 3 8 A, CY ← A – (addr16) – CY
A, [HL] 1 6 A, CY ← A – (HL) – CY
A, [HL + byte] 2 6 A, CY ← A – (HL + byte) – CY

1 8 AX ←→ rp

Flags

ZACCY

×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××

Only when rp = BC, DE, HL

Note

Remark

One clock of an instruction is one clock of the CPU clock (f
control register (PCC).

Data Sheet U14022EJ1V0DS00

CPU

) selected using the processor clock

23

µµµµ

PD78F9177, 78F9177Y

Mnemonic Operand Bytes Clock Operation

AND A, #byte 2 4 A ← A ∧ byte

saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte
A, r 2 4 A ← A ∧ r
A, saddr 2 4 A ← A ∧ (saddr)
A, !addr16 3 8 A ← A ∧ (addr16)
A, [HL] 1 6 A ← A ∧ (HL)
A, [HL + byte] 2 6 A ← A ∧ (HL + byte)

OR A, #byte 2 4 A ← A ∨ byte

saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte
A, r 2 4 A ← A ∨ r
A, saddr 2 4 A ← A ∨ (saddr)
A, !addr16 3 8 A ← A ∨ (addr16)
A, [HL] 1 6 A ← A ∨ (HL)
A, [HL + byte] 2 6 A ← A ∨ (HL + byte)

XOR A, #byte 2 4 A ← A ∨ byte

saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte
A, r 2 4 A ← A ∨ r
A, saddr 2 4 A ← A ∨ (saddr)
A, !addr16 3 8 A ← A ∨ (addr16)
A, [HL] 1 6 A ← A ∨ (HL)
A, [HL + byte] 2 6 A ← A ∨ (HL + byte)

CMP A, #byte 2 4 A – byte

saddr, #byte 3 6 (saddr) – byte
A, r 2 4 A – r
A, saddr 2 4 A – (saddr)
A, !addr16 3 8 A – (addr16)
A, [HL] 1 6 A – (HL)

A, [HL + byte] 2 6 A – (HL + byte)
ADDW AX, #word 3 6 AX, CY ← AX + word
SUBW AX, #word 3 6 AX, CY ← AX – word
CMPW AX, #word 3 6 AX – word
INC r 2 4 r ← r + 1

saddr 2 4 (saddr) ← (saddr) + 1
DEC r 2 4 r ← r– 1

saddr 2 4 (saddr) ← (saddr) – 1

Flags

ZACCY

×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
××
××
××
××

Remark

24

One clock of an instruction is one clock of the CPU clock (f
control register (PCC).

Data Sheet U14022EJ1V0DS00

CPU

) selected using the processor clock

µµµµ

PD78F9177, 78F9177Y

Mnemonic Operand Bytes Clock Operation

Flags

ZACCY
INCW rp 1 4 rp ← rp + 1
DECW rp 1 4 rp ← rp – 1

7

0

m-1

ROR A, 1 1 2 (CY, A
ROL A, 1 1 2 (CY, A0 ← A7, A
RORC A, 1 1 2 (CY ← A0, A7 ← CY, A
ROLC A, 1 1 2 (CY ← A7, A0 ← CY, A

A

, A

←

← Am) × 1

m+1

← Am) × 1

m-1

← Am) × 1

m+1

← Am) × 1

×
×
×
×

SET1 saddr.bit 3 6 (saddr.bit) ← 1

sfr.bit 3 6 sfr.bit ← 1
A.bit 2 4 A.bit ← 1
PSW.bit 3 6 PSW.bit ← 1

×××

[HL].bit 2 10 (HL).bit ← 1

CLR1 saddr.bit 3 6 (saddr.bit) ← 0

sfr.bit 3 6 sfr.bit ← 0
A.bit 2 4 A.bit ← 0
PSW.bit 3 6 PSW.bit ← 0

×××

[HL].bit 2 10 (HL).bit ← 0
SET1 CY 1 2 CY ← 11
CLR1 CY 1 2 CY
NOT1 CY 1 2 CY

00

←

CY

←

×

CALL !addr16 3 6 (SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,

PC ← addr16, SP ←SP – 2

CALLT [addr5] 1 8 (SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,

H

PC

← (00000000, addr5 + 1)

L

PC

← (00000000, addr5)

SP ← SP – 2

RET 1 6 PCH ← (SP + 1), PCL ← (SP),

SP ← SP + 2

RETI 1 8 PCH ← (SP + 1), PCL ← (SP),

RRR
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0

PUSH PSW 1 2 (SP – 1) ← PSW, SP ← SP – 1

rp 1 4 (S P – 1) ← rpH, (SP – 2) ← rpL,

SP ← SP -– 2

POP PSW 1 4 PSW ← (SP), SP ← SP + 1 R R R

rp 1 6 rpH ← (SP + 1), rpL ← (SP),

SP ← SP + 2

MOVW SP, AX 2 8 SP ← AX

AX, SP 2 6 AX ← SP

Remark

One clock of an instruction is one clock of the CPU clock (f
control register (PCC).

Data Sheet U14022EJ1V0DS00

CPU

) selected using the processor clock

25

µµµµ

PD78F9177, 78F9177Y

Mnemonic Operand Bytes Clock Operation

BR !addr16 3 6 PC ← addr16

$addr16 2 6 PC ← PC + 2 + jdisp8

AX 1 6 PCH ← A, PCL ← X
BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1
BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0
BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1
BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0
BT saddr.bit, $saddr16 4 10 PC ← PC + 4 + jdisp8

if (saddr. bit) = 1
sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 1
A.bit, $saddr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 1
PSW.bit $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 1

BF saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8

if (saddr. bit) = 0
sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 0
A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 0
PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 0

DBNZ B, $addr16 2 6 B ← B – 1, then

PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16 2 6 C ← C – 1, then

PC ← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16 3 8 (saddr) ← (saddr) – 1, then

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

NOP 1 2 No Operat i on
EI 3 6 IE ← 1 (Enable Interrupt)
DI 3 6 IE ← 0 (Disable Interrupt)
HALT 1 2 Set HALT Mode
STOP 1 2 Set Stop Mode

Flags

ZACCY

Remark

26

One clock of an instruction is one clock of the CPU clock (f
control register (PCC).

Data Sheet U14022EJ1V0DS00

CPU

) selected using the processor clock

7. ELECTRICAL SPECIFICATIONS

µµµµ

PD78F9177, 78F9177Y

Absolute Maximum Ratings (TA = 25

Parameter Symbol Conditions Ratings Unit

Supply voltage

AV

AV

Input voltage

Output voltage V

Operating ambient temperature T

Storage temperature T

C)

°°°°

DD

V

V

V
V
V

OH

AVDD − 0.3 V ≤ VDD ≤ AVDD + 0.3 V

REF

DD

≤ AV

AV

DD

REF

AV

REF

PP

I1

Pins other than P50 to P53, P 23, P24

I2

P23, P24

I3

P50 to P53

O

+ 0.3 V

≤ VDD + 0.3 V

Per pin
Total for all pins

OL

Per pin 30 mAOutput current, low I

0.3 to +6.5

−

0.3 to +10.5 V

−

0.3 to VDD + 0.3 V

−

0.3 to +5.5 V

−

0.3 to +13 V

−

DD

0.3 to V

−

+ 0.3 V

10 mAOutput current, high I

−

30 mA

−

V
V
V

Total for all pins 160 mA

A

In normal operation mode
During flash memory programming +10 to +40

stg

40 to +85

−

40 to +125

−

C

°

C

°

C

°

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.

Remark

Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.

Data Sheet U14022EJ1V0DS00

27

µµµµ

PD78F9177, 78F9177Y

Main System Clock Oscillator Characteristics (TA =

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Oscillation frequency (fX)

Oscillation stabilization time

Oscillation frequency (fX)

Oscillation stabilization time

X1 input frequency (fX)

X1 input high-/low-level widt h

XH

, tXL)

(t

X1 input frequency (fX)

resonator

Crystal
resonator

External
clock

X1

X1

PP

C1

PP

C1

X2X1V

C2

X2X1V

C2

X2

X2

40 to +85

−−−−

Note 1

Note 2

Note 1

Note 2

Note 1

Note 1

C, VDD = 1.8 to 5.5 V)

°°°°

VDD = oscillation
voltage range

After VDD reaches
oscillation voltage
range MIN.

VDD = 4.5 to 5.5 V 10

VDD = 2.7 to 5.5 V

1.0 5.0 MHzCeramic

1.0 5.0 MHz

1.0 5.0 MHz

85 500 ns

1.0 5.0 MHz

4ms

30

ms

DD

V

Notes 1.

OPEN

Indicates only oscillator characteristics. Refer to
Time required to stabilize oscillation after reset or STOP mode release. Use a resonator that stabilizes

2.

X1 input high-/low-level widt h

XH

, tXL)

(t

AC Characteristics

= 2.7 to 5.5 V

for instruction execution time.

85 500 ns

oscillation within the oscillation wait time.

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.

••••

Do not cross the wiring with the other signal lines.

•

Do not route the wiring near a signal line through which a high fluctuating current flows.

•

Always make the ground point of the oscillator capacitor the same potential as V

•

Do not ground the capacitor to a ground pattern through which a high current flows.

•

Do not fetch signals from the oscillator.

•

SS0

.

2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.

Remark

For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.

28

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

Subsystem Clock Oscillator Characteristics (TA =

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX . Unit

Crystal
resonator

clock

Notes 1.

V

PP

C3

XT1

XT2XT1

R

C4

XT2

Indicates only oscillator characteristics. Refer
Time required to stabilize oscillation after reset or STOP mode release.

2.

Oscillation frequency (fXT)

Oscillation stabilization time

XT1 input frequency (fXT)

XT1 input high-/low-level width

XTH

XTL

, t

(t

)

40 to +85

−−−−

Note 1

Note 2

Note 1

C, VDD = 1.8 to 5.5 V)

°°°°

32 32.768 35 kHz

VDD = 4.5 to 5.5 V 1.2 2 s

32 35 kHzExternal

14.3 15.6

AC Characteristics

for instruction execution time.

10 s

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.

••••

Do not cross the wiring with the other signal lines.

•

Do not route the wiring near a signal line through which a high fluctuating current flows.

•

Always make the ground point of the oscillator capacitor the same potential as V

•

Do not ground the capacitor to a ground pattern through which a high current flows.

•

Do not fetch signals from the oscillator.

•

SS0

.

s

µ

Remark

2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.

For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U14022EJ1V0DS00

29

µµµµ

PD78F9177, 78F9177Y

DC Characteristics (TA =

40 to +85

−−−−

C, VDD = 1.8 to 5.5 V)

°°°°

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Output current

,

high

Output current, low I

OH

I

OL

Per pin

Total for all pins

Per pin

1mA

−

15 mA

−

10 mA

Total for all pins 80 mA

Input voltage, high

IH1

P00 to P05, P10,
P11,P60 to P67

IH2

P50 to P53

IH3

RESET,
P20 to P26, P30

VDD = 2.7 to 5.5 V 0.7 V

0.9 V

VDD = 2.7 to 5.5 V 0.7 V

DD

= 1.8 to 5.5 V,

V

A

T

= 25 to +85°C

0.9 V

VDD = 2.7 to 5.5 V 0.8 V

0.9 V

DD
DD
DD
DD

DD
DD

DD

V

DD

V

12 VV
12 V

DD

V

DD

V

to P33

DD
DD

Input voltage, low

IH4

V

IL1

IL2

X1, X2, XT1, XT2

P00 to P05, P10,
P11, P60 to P67

P50 to P53

VDD = 4.5 to 5.5 V VDD − 0.5 V

DD

− 0.1 V

V

VDD = 2.7 to 5.5 V 0 0.3 V

0 0.1 V

VDD = 2.7 to 5.5 V 0 0.3 V

0 0.1 V

IL3

IL4

V

RESET,P20 to
P26, P30 to P33

X1, X2, XT1, XT2

VDD = 2.7 to 5.5 V 0 0.2 V

0 0.1 V

VDD = 4.5 to 5.5 V 0 0.4 V

00.1V

high

OH

V

Pins other than
P23, P24, P50 to
P53

VDD = 4.5 to 5.5 V, IOH = −1 mA VDD − 1.0 VOutput voltage,

DD

V

= 1.8 to 5.5 V, IOH = −100 µAVDD − 0.5 V

VV
V

VV
V

V
V

DD
DD
DD
DD
DD
DD

VV
V
VV
V
VV
V

Output voltage,
low

Input leakage
current, high

Input leakage
current, low

Output leakage
current, high

Output leakage
current, low

Software pull-up
resistor

A low-level input leakage current of -60

Note

is executed to P50 to P53 and P50 to P53 are set to input mode. At times other than this, -3 µA (MAX.)
current flows.

OL1

Pins other than
P50 to P53

OL2

V

I

LIH1

P50 to P53

DD

VI = V

VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 VV

DD

= 1.8 to 5.5 V, IOL = 400 µA0.5V

V
VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V

DD

= 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V

V
Pins other than P50 to P53 (N-c h

3

A

µ

open-drain) X1, X2, XT1, and
XT2

LIH2

I

LIH3

I

VI = 12 V P50 to P53 (N-ch open drain) 20

LIL1

I

VI = 0 V

X1, X2, XT1, XT2 20

Pins other than P50 to P53 (N-c h

−

A

µ

A

µ

3

A

µ

open-drain) X1, X2, XT1, and
XT2

LIL2

I

LIL3

I

LOH

I

LOL

I

1

R

DD

VO = V

VO = 0 V

VI = 0 V, for pins other than P23, P 24, and P50 to

X1, X2, XT1, XT2
P50 t o P53 (N-ch open drain)

20

−

Note

3

−

3

3

−

50 100 200 k

A

µ

A

µ

A

µ

A

µ

Ω

P53

A(MAX.) flows only during the 1-cycle time after a read instruction

µ

Remark

30

Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

DC Characteristics (TA =

40 to +85

−−−−

C, VDD = 1.8 to 5.5 V)

°°°°

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Power supply
current

Note 1

DD1

I

5.0-MHz crystal oscillation

VDD = 5.0 V ± 10%

operating mode
(C1 = C2 = 22pF)

Note 1

DD2

I

5.0-MHz crystal oscillation

VDD = 3.0 V ± 10%

VDD = 2.0 V ± 10%

VDD = 5.0 V ± 10%

HALT mode
(C1 = C2 = 22pF)

Note 1

DD3

I

32.768-kHz crystal
oscillation operating

Note 3

mode
(C3 = C4 = 22pF,

VDD = 3.0 V ± 10%

VDD = 2.0 V ± 10%
VDD = 5.0 V ± 10%

VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%

Note 4

Note 5

Note 5

Note 4

Note 5

Note 5

5.0 15.0 mA

2.0 5.0 mA

1.5 3.0 mA

2.0 6.0 mA

1.0 2.5 mA

0.75 1.5 mA
250 750

200 600
150 450

R = 220kΩ)

Note 1

DD4

I

32.768-kHz crystal
oscillation HALT mode

(C3 = C4 = 22pF,
R = 220kΩ)

Note 1

DD5

I

32.768-kHz crystal stop
STOP mode

Note 2

DD6

I

5.0-MHz crystal oscillation
A/D operating mode
(C1 = C2 = 22pF)

Note 3

VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%

VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%

VDD = 5.0 V ± 10%

VDD = 3.0 V ± 10%

VDD = 2.0 V ± 10%

Note 4

Note 5

Note 5

50 150
30 90
20 60

0.1 30

0.05 10

0.05 10

6.0 17.0 mA

3.0 7.0 mA

2.5 5.0 mA

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

Notes 1.

2.

3.

4.

5.

Remark

REF

The AV

ON (ADCS0 (bit 7 of ADM0; A/D converter mode register 0) = 1), AVDD, and the port current
(including the current flowing through the internal pull-up resistors) are not included.
The AV

REF

On (ADCS0 =1) and port current (including the current flowing through the internal pull-up
resistors) are not included. Refer to the A/D converter characteristics for the current flowing through

REF

AV

.
When the main system clock is stopped.
During high-speed mode operation (when the processor clock control register (PCC) is set to 00H.)
During low-speed mode operation (when PCC is set to 02H)

Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.

Data Sheet U14022EJ1V0DS00

31

AC Characteristics

µµµµ

PD78F9177, 78F9177Y

(1) Basic operation (TA =

40 to +85

−−−−

C, VDD = 1.8 to 5.5 V)

°°°°

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Cycle time
(minimum instruction
execution time)

T

main system clock

VDD = 2.7 to 5.5 V 0.4 8

1.6 8

CY

Operation based on the subsystem clock 114 122 125

TI

TI80 and TI81 input
frequency

high-/low-level width

Interrupt input high-

t

TIH

t

INTH

VDD = 2.7 to 5.5 V 0 4

f

0 275

TIL

VDD = 2.7 to 5.5 V 0.1

, t

1.8

INTL

, t

INTP0 to INTP3 10

/low-level width
RESET input low-

RSL

t

10

level width
CPT90 input high-

/low-level width

CPH

t

,

CPL

t

10

TCY vs VDD (main system clock)

µ
µ
µ

MHz

kHz

µ
µ
µ

µ

µ

sOperation based on the
s
s

sTI80 and TI81 input
s
s

s

s

µ

Cycle time TCY [ s]

60

10

2.0

1.0

0.5

0.4

0.1

Guaranteed
operation range

123456

Supply voltage VDD [V]

32

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

(2) Serial interface (TA =

40 to +85

−−−−

C, VDD = 1.8 to 5.5 V)

°°°°

(a) 3-wire serial I/O mode (SCK20...Internal clock)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

KCY1

VDD = 2.7 to 5.5 V 800 nsSCK20 cycle time t

3200 ns

KCY1

/2−50 nsSCK20 high-/low-

KCY1

t

/2−150 ns

500

600 ns

0 1000 ns

level width

SI20 setup time
(to SCK20 ↑)

(from SCK20 ↑)

time from SCK20

R and C are the load resistance and load capacitance of the SO20 output line.

Note

KH1

KL1

t

t

t

t

↓

VDD = 2.7 to 5.5 V t

, t

SIK1

VDD = 2.7 to 5.5 V 150

KSI1

VDD = 2.7 to 5.5 V 400 nsSI 20 hol d t i me

KSO1

R = 1 kΩ,
C = 100 pF

Note

VDD = 2.7 to 5.5 V 0 250 nsSO20 output delay

(b) 3-wire serial I/O mode (SCK20...External clock)

ns
ns

Parameter Symbol Conditions MIN. TYP. MAX. Unit

KCY2

VDD = 2.7 to 5.5 V 900 nsSCK20 cycle time t

3500 ns

KH2

KL2

VDD = 2.7 to 5.5 V 400 nsSCK20 high-/low-

, t

SIK2

VDD = 2.7 to 5.5 V 100

KSI2

VDD = 2.7 to 5.5 V 400 nsSI20 hold time

KSO2

KAS2

KDS2

R = 1 kΩ,
C = 100 pF

VDD = 2.7 to 5.5 V 120 nsS O20 setup time

VDD = 2.7 to 5.5 V 240 nsS O20 di sable time

Note

VDD = 2.7 to 5.5 V 0 300 nsSO20 output delay

1600 ns

150

600 ns

0 1000 ns

400 ns

800 ns

level width

SI20 setup time
(to SCK20 ↑)

(from SCK20 ↑)

time

from SCK20

(when using SS20,
to SS20 ↓)

(when using SS20,
from SS20 ↑)

R and C are the load resistance and load capacitance of the SO20 output line.

Note

t

t

t

t

↓

t

t

ns
ns

(c) UART mode (dedicated baud rate generator output)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 78125 bpsTransfer rate

19531 bps

Data Sheet U14022EJ1V0DS00

33

µµµµ

PD78F9177, 78F9177Y

(d) UART mode (external clock input)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

KCY3

VDD = 2.7 to 5.5 V 900 nsASCK20 cycle

3500 ns

KL3

VDD = 2.7 to 5.5 V 400 nsASCK20 high-/low-

, t

1600 ns

VDD = 2.7 to 5.5 V 39063

F

9766

1

time

level width

Transfer rate

ASCK20 rise time,
fall time

t

KH3

t

tR, t

bps
bps

µ

s

34

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

(3) Serial interface SMB0 (TA =

40 to +85

−−−−

C, VDD = 1.8 to 5.5 V) (

°°°°

PD78F9177Y only)

µµµµ

(a) DC Characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, high V
Input voltage, low V
Output voltage,

high

Input leakage

IH

SCL0, SDA0 (at hysteres i s) 0.8 V

IL

SCL0, SDA0 (at hysteres i s) 0 0.2 V

OL

V

SCL0, SDA0

LIH

I

SCL0, SDA0 VI = V

VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0

DD

V

= 1.8 to 5.5 V, IOL = 400 µ A0.5

DD

DD

DD

V

3

current, high
Input leakage

LIL

I

SCL0, SDA0 VI = 0 V

3

−

current, low

(b) DC Characteristics (When using comparator)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input range V

Transfer level V

Input level
threshold value

SDA

,

VDD = 1.8 to 5.5 V 0 5.5 V

SCL

V

ISDA

4.5 ≤ VDD ≤ 5.5 V 0.72 V

,

ISCL

V

3.3 ≤ VDD < 4.5 V 0.78 V

2.7 ≤ VDD < 3.3 V 0.75 V

1.8 ≤ VDD < 2.7 V 0.90 V

ISMB

V

LVL01, LVL00 = 0, 1 0.25 × V

ISMB

ISMB

ISMB

ISMB

LVL01, LVL00 = 1, 0 0.375 × V
LVL01, LVL00 = 1, 1 0.5 × V

ISMB

V

ISMB

V

ISMB

V

ISMB

V

1.28 V

1.22 V

1.25 V

1.45 V

DD

DD

DD

DD

ISMB

ISMB

ISMB

ISMB

V
V
V
V

A

µ

A

µ

V
V
V
V
V
V
V

ISMB

is an input level threshold value selected by bits LVL00 and LVL01 (bits 0 and 1 of SMB input level

V

Note

setting register 0 (SMBVI0)).
According to the SMB standard (V1.1), the maximum value of low-level input voltage is 0.8 V, and the
minimum value of high-level input voltage, 2.1 V. To satisfy these conditions, set LVL01 and LVL00 as
follows;

When VDD = 1.8 to 3.3 V: LVL01, LVL00 = 1, 1 (0.5 × VDD)

•

When VDD = 3.3 to 4.5 V: LVL01, LVL00 = 1, 0 (0.375 × VDD)

•

When VDD = 4.5 to 5.5 V: LVL01, LVL00 = 0, 1 (0.25 × VDD)

•

"LVL01, LVL00 = 0, 0" is not available since this setting does not satisfy the SMB standard (V1.1).

Data Sheet U14022EJ1V0DS00

35

µµµµ

PD78F9177, 78F9177Y

(c) AC Characteristics

Parameter Symbol

SCL0 clock frequency f
Bus free time
(between stop and start condition)

Hold time

Note1

Start/restart condi tion setup time t
Stop condition setup t i m e t

When using CBUS-

time

compatible master
When using SMB/IIC

bus

Data setup time t
SCL0 clock low-level width t

SCL0 clock high-level width t
SCL0 and SDA0 signal fall ti m e t
SCL0 and SDA0 signal rise tim e t
Spike pulse width control l ed by

input filter
Timeout t
Total extended time of SCL0 c l ock

low-level period (slave)
Total extended time of cum ul ative

clock low-level peri od (m aster)
Capacitive load per each bus li ne Cb

t

t

t

t

t

t

CLK

BUF

HD:STA

SU:STA

SU:STO

HD:DAT

SU:DAT

LOW

HIGH

F

R

SP

TIMEOUT

LOW:SEXT

LOW:MEXT

2

C

SMB Mode

Standard Mode I

Bus

High-speed Mode I2C

Bus

MIN. MAX. MIN. MAX. MIN. MAX.

10 100 0 100 0 400 kHz

4.7

4.0

4.7

4.0

−

−

−

−

−−

300

250

4.7

−−−

−

−

4.0 50 4.0

−

−

300

1000

−−−−

25 35

−

−

25

10

−−−

4.7

4.0

4.7

4.0
5

250

4.7

−

−

−

−

−

−

−−−

−

−

−

300

1000

100

1.3

0.6

0.6

0.6

Note2

0

1.3

0.6

Note4

−

−

−

−

−

−

Note3

900

−

−

−

300 ns
300 ns

050ns

−−−−

−−−−

−−−−

400

−

400 pF

Unit

µ

µ
µ

µ
µ

ns

ns

µ
µ

ms
ms

ms

s

s
s

s
sData hold

s
s

36

Notes 1.

2.

3.

4.

In the start condition, the first clock pulse is generated after this hold time.
To fill in the underfined area of the SCL0 falling edge, it is necessary for the device to internally

IHmin

provide at least 300 ns of hold time for the SDA0 signal (which is V
If the device does not extend the SCL0 signal low hold time (t

HD:DAT

t

needs to be fulfilled.

. of the SCL0 signal).

LOW

), only maximum data hold time

The high-speed mode I2C bus is available in the SMB mode and the standard mode I2C bus system.
At this time, the conditions described below must be satisfied.
If the device extends the SCL0 signal low state hold time
t

SU:DAT

250 ns

≥

If the device extends the SCL0 signal low state hold time

Rmax.

Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (t

SU:DAT

t

= 1000 + 250 = 1250 ns by the SMB mode or the standard mode I2C bus specification).

Data Sheet U14022EJ1V0DS00

+

AC Timing Measurement Points (excluding the X1 and XT1 inputs)

0.8 V

0.2 V

DD

DD

Point of
measurement

Clock Timing

1/f

X

t

XL

X1 input

µµµµ

PD78F9177, 78F9177Y

0.8 V

DD

0.2 V

DD

t

XH

V

IH4

(MIN.)

IL4

(MAX.)

V

TI Timing

XT1 input

TI80, TI81

1/f

XT

t

XTL

1/f

t

TIL

t

XTH

V

IH4

(MIN.)

IL4

(MAX.)

V

TI

t

TIH

Data Sheet U14022EJ1V0DS00

37

Interrupt Input Timing

INTP0-INTP3

RESET Input Timing

CPT90 Input Timing

CPT90

RESET

µµµµ

PD78F9177, 78F9177Y

t

INTL

t

RSL

t

CPL

t

INTH

t

CPH

38

Data Sheet U14022EJ1V0DS00

Serial Transfer Timing

3-wire serial I/O mode:

t

KCYm

µµµµ

PD78F9177, 78F9177Y

SCK20

SI20

SO20

Remark

m = 1, 2

3-wire serial I/O mode (when using SS20):

t

KSOm

t

KLm

t

SIKm

Input data

t

KSIm

Output data

t

KHm

SS20

SO20

UART mode (external clock input):

ASCK20

t

KAS2

KDS2

t

Output data

t

KCY3

t

KL3

t

R

t

KH3

t

F

Data Sheet U14022EJ1V0DS00

39

SMB mode:

µµµµ

PD78F9177, 78F9177Y

SCL0

SDA0

tBUF

Stop condition Start condition

tLOW

tHD:STA

tHD:DAT

tR

tSU:DAT

tF

tSU:STA tHD:STA tSP

Restart condition

t

SU:STO

Stop condition

tHIGH

40

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

10-Bit A/D Converter Characteristics (TA =

40 to +85

−−−−

C, 1.8

°°°°

≤≤≤≤

AV

REF

AVDD = VDD

≤≤≤≤

5.5 V, AVSS = VSS = 0 V)

≤≤≤≤

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution 10 10 10 bit
Overall error

Note

Conversion time t

Zero-scale error

Full-scale error

Integral linearity

Note

error

Differential linearit y

Note

error

Note

Note

Analog input voltage V
Reference voltage A V
Resistance between

AV

REF

and AV

SS

R

CONV

INL

DNL

IAN

AIREF

4.5 V ≤ AV

2.7 V ≤ AV

1.8 V ≤ AV

4.5 V ≤ AV

2.7 V ≤ AV

1.8 V ≤ AV

4.5 V ≤ AV

2.7 V ≤ AV

1.8 V ≤ AV

4.5 V ≤ AV

2.7 V ≤ AV

1.8 V ≤ AV

4.5 V ≤ AV

2.7 V ≤ AV

1.8 V ≤ AV

4.5 V ≤ AV

2.7 V ≤ AV

1.8 V ≤ AV

REF

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V 14 100

REF

≤ AVDD ≤ 5.5 V 14 100

REF

≤ AVDD ≤ 5.5 V 28 100

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

REF

≤ AVDD ≤ 5.5 V

0.2

±

0.4

±

0.8

±

0AV

1.8 AV
20 40 k

0.4 %FSR

±

0.6 %FSR

±

1.2 %FSR

±

0.4 %FSR

±

0.6 %FSR

±

1.2 %FSR

±

0.4 %FSR

±

0.6 %FSR

±

1.2 %FSR

±

2.5

±

4.5

±

8.5

±

1.5

±

2.0

±

3.5

±

REF

DD

µ
µ
µ

LSB
LSB
LSB
LSB
LSB
LSB

V
V

s
s
s

Ω

Excludes quantization error (±0.05%FSR).

Note

Remark

FSR: Full scale range

Data Sheet U14022EJ1V0DS00

41

µµµµ

PD78F9177, 78F9177Y

FLASH MEMORY WRITE/DELETE CHARACTERISTICS (TA = 10 to 40

C, VDD = 1.8 to 5.5 V)

°°°°

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Write current

Note

DD

pin)

(V
Write current

Note

PP

pin)

(V
Delete current

Note

DD

pin)

(V
Delete current

Note

PP

pin)

(V
Unit delete time t
Total delete time t

I

I

I

I

DDW

PPW

DDE

PPE

er

era

When VPP supply voltage = V
(5.0-MHz crystal oscillat i on operat ion mode)

When VPP supply voltage = V

When VPP supply voltage = V
(5.0-MHz crystal oscillat i on operat ion mode)

When VPP supply voltage = V

PP1

PP1

PP1

PP1

18 mA

7.5 mA

18 mA

100 mA

0.5 1 1 s
20 s

Write count Delete/write are regarded as 1 cycle 20 Times

PP0

V

PP1

V

The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and AV

Note

In normal operation 0 0.2V
During flash memory programming 9.7 10.0 10.3 V

DD

current are not included.

=

Data Memory Stop Mode Low Power Supply Voltage Data Retention Characteristics (T

A

−−−−

40 to +85

C)

°°°°

VVPP supply voltage

DD

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data retention power

V

DDDR

1.8 5.5 V

supply voltage
Release signal set tim e t

wait time

Note 1

Notes 1.

The oscillation stabilization time is the time the CPU operation is stopped to prevent unstable

SREL

WAIT

t

0
Release by RESET 215/f
Release by interrupt request

Note 2

X

operation when oscillation starts.
By using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time selection register (OSTS),

2.

12

/fX, 215/fX, or 217/fX can be selected.

2

Remark

fX: Main system clock oscillation frequency

s

µ

sOscillation stabilization
s

42

Data Sheet U14022EJ1V0DS00

Data Retention Timing (STOP Mode Release by RESET)

STOP mode

Data retention mode

µµµµ

PD78F9177, 78F9177Y

Internal reset operation

HALT mode

Operating mode

VDD

RESET

STOP instruction execution

V

DDDR

tSREL

tWAIT

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

HALT mode

STOP mode

Data retention mode

V

DD

STOP instruction execution

V

DDDR

t

SREL

Operating mode

Standby release signal
(interrupt request)

t

WAIT

Data Sheet U14022EJ1V0DS00

43

8. CHARACTERISTICS CURVES

µµµµ

PD78F9177, 78F9177Y

(mA)

DD

10.0

1.0

0.5

0.1

(TA = 25 ˚C)

Main system clock operating
mode (PCC1 = 0, CSS0 = 0)

Main system clock operating
mode (PCC1 = 1, CSS0 = 0)

Main system clock operation
HALT mode (PCC1 = 1,
CSS0 = 0)

Main system clock operation
HALT mode (PCC1 = 1, CSS0 = 0)

Subsystem clock operating
mode (CSS0 = 1, MCC = 1)

Supply current I

0.05

0.01

0.005

0.001
01234

22 pF

Supply voltage V

Subsystem clock operation
HALT mode (CSS0 = 1,
MCC = 1)

X1 X2

Crystal

resonator

5.0 MHz

22 pF

5678

DD

(V)

XT1

V

SS

XT2

Crystal

resonator

32.768 kHz

33 pF

V

SS

220 kΩ

33 pF

44

Data Sheet U14022EJ1V0DS00

9. PACKAGE DRAWING

44 PIN PLASTIC QFP (10x10)

µµµµ

PD78F9177, 78F9177Y

A
B

34

44

33

1

23

11

22

12

F

J

G

H

M

I

K

S

N

NOTE

Each lead centerline is located within 0.16 mm of
its true position (T.P.) at maximum material condition.

CD

M

detail of lead end

S

P

T

R

L
U

Q

S

ITEM MILLIMETERS

A 12.0±0.2
B 10.0±0.2
C 10.0±0.2
D 12.0±0.2

F

1.0

G

1.0

H

I

J

K

L 0.5

M 0.17
N

P 1.4±0.05
Q 0.1±0.05

R3°

S 1.6 MAX.

U 0.6±0.15

+0.08

0.37

−0.07

0.2

0.8 (T.P.)

1.0±0.2

+0.03

−0.06

0.10

+4°

−3°

S44GB-80-8ES-1

Data Sheet U14022EJ1V0DS00

45

48-PIN PLASTIC TQFP (FINE PITCH) (7x7)

A
B

µµµµ

PD78F9177, 78F9177Y

detail of lead end

37

36

25

24

S

P

T

L
U

48

CD

R

1

13

12

Q

F

G

H

M

I

J

K

S

SN

M

NOTE

Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

9.0±0.2

A
B 7.0±0.2
C 7.0±0.2
D 9.0±0.2
F 0.75
G

0.75
+0.05

0.22

H

I 0.10

J 0.5 (T.P.)

K 1.0±0.2

L 0.5±0.2

M
N 0.08

P 1.0±0.1
Q 0.1±0.05

R
S 1.27 MAX.

−0.04

+0.03

0.17

−0.07

+4°

3°

−3°

P48GA-50-9EU

46

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

10. RECOMMENDED SOLDERING CONDITIONS

The µPD78F9177 and µPD789177Y should be soldered and mounted under the following recommended

conditions.

For the details of the recommended soldering conditions, refer to the document

Mounting Technology Manual (C10535E

).

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Table 10-1. Surface Mounting Type Soldering Conditions (1/2)

Semiconductor Device

PD78F9177GB-8ES: 44-pin plastic LQFP (10

µµµµ

PD78F9177YGB-8ES: 44-pin plastic LQFP (10

µµµµ

Soldering Method Soldering Conditions

Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds max.

(at 210 °C or higher), Count: Twice or less

VPS P ackage peak temperature: 215 °C, Time: 40 seconds max.

(at 200 °C or higher), Count: Twice or less

Wave soldering Solder bath temperature: 260 °C max., Time: 10 sec onds max., Count:

Once, Preheating temperature: 120 °C max. (package surface
temperature)

Partial heating Pin temperature: 300 °C max., Time: 3 sec onds max. (per pin row)

××××
××××

10)

10)

Caution Do not use different soldering methods together (except for partial heating).

Table 10-1. Surface Mounting Type Soldering Conditions (2/2)

PD78F9177YGA-9EU: 48-pin plastic TQFP (7

µµµµ

Soldering Method Soldering Conditions

7)

××××

Recommended Condition

Symbol

IR35-00-2

VP15-00-2

WS60-00-1

−

Recommended Condition

Symbol

Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds max.

(at 210 °C or higher), Count: Twice or less, Number of days:3
that, prebaking sis nec essary at 125 °C for 10 hours)

VPS P ackage peak temperature: 215 °C, Time: 40 seconds max.

(at 200 °C or higher), Count: Twice or less, Number of days:3
that, prebaking sis nec essary at 125 °C for 10 hours)

Partial heating Pin temperature: 300 °C max., Time: 3 sec onds max. (per pin row)

The number of days for storage at 25°C, 65% RH MAX after the dry pack has been opened.

Note

Note

Note

(After

(After

Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U14022EJ1V0DS00

IR35-103-2

VP15-103-2

−

47

µµµµ

PD78F9177, 78F9177Y

APPENDIX A. DIFFERENCES BETWEEN µPD78F9177, 78F9177Y, AND MASK ROM VERSIONS

The µPD78F9177 and µPD78F9177Y are flash memory version of the Mask ROM version. The differences

between the µPD78F9177, 78F9177Y and the Mask ROM versions are shown in Table A-1.

Table A-1. Differences between

Flash Memory Version Mask ROM VersionProduct Name

PD78F9177, 78F9177Y

µ

Item

ROM 24 KB 16 KB 24 KBInternal

memory
VPP pin Provided Not provided

Pull-up resistor 17 (Software control) 21 (Software control: 17, mask option specifi cation: 4)
A/D resolution 10 bits 8 bi ts (µPD789166, 789167, 789166Y, 789167Y)

Electrical speci fications See the relevant data sheet

High-speed RAM 512 bytes

PD78F9177, 78F9177Y and Mask ROM Versions

µµµµ

PD789166, 789166Y

µ

789176, 789176Y

10 bits (

PD789176, 789177, 789176Y, 789177Y)

µ

PD789167, 789167Y

µ

789177, 789177Y

Cautions 1. There are differences in the amount of noise immunity and noise radiation between the

flash memory and mask ROM versions. When pre-producing an application set with the
flash memory version and then mass producing it with the mask ROM versions, be sure
to conduct sufficient evaluations on the commercial samples (CS) (not engineering
sample, ES) of the mask ROM version.

2. When the

PD78F9177, a flash memory counterpart of the

µµµµ

PD789166 or

µµµµ

PD789167, is

µµµµ

used, however, ADCR0 can be manipulated with an 8-bit memory manipulation
instruction. In this case, use an object file assembled with the
The same is also true for the

PD789166Y or

µµµµ

PD789167Y. When the

µµµµ

PD78F9177Y, a flash memory counterpart of the

µµµµ

PD78F9177Y is used, ADCR0 can be

µµµµ

PD789166 or

µµµµ

PD789167.

µµµµ

manipulated with an 8-bit memory manipulation instruction. In this case, use an object
file assembled with the

PD789166Y or

µµµµ

PD789167Y.

µµµµ

48

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are available for developing systems using the µPD78F9177 and µPD78F9177Y.

Language Processing Software

RA78K0S
CC78K0S
DF789177
CC78K0S-L

Notes 1, 2, 3

Notes 1, 2, 3

Notes 1, 2, 3

Notes 1, 2, 3

Flash Memory Writing Tools

Assembler package com m on to 78K/0S Series
C compiler package common t o 78K/0S Series
Device file for µPD789167, 789177, 789167Y, and 789177Y Subseries
C compiler library sourc e f ile common to 78K/0S Series

Flashpro lIl
(Part No. FL-PR3

FA-44GB-8ES
FA-48GA Flash memory programming adapter f or 48-pi n pl astic TQFP (fine pitch) (GA-9EU

Note 4

Note 4

, PG-FP3)

Flash programmer dedicated for on-chi p flash memory microcont rol l ers

Flash memory programming adapter for 44-pi n pl astic LQFP (GB-8ES ty pe)

type)

Debugging Tools(1/2)

IE-78K0S-NS
In-circuit emulator

IE-70000-MC-PS-B
AC adapter

IE-70000-98-IF-C
Interface adapter

IE-70000-CD-IF-A
PC card/interface

IE-70000-PC-IF-C
Interface adapter

IE-70000-PCI-IF
Interface adapter

IE-789177-NS-EM1
Emulation board

NP-44GB
Emulation probe

NP-44GB-TQ
Emulation probe

Note 4

Note 4

EV-9200G-44
conversion socket

TGB-044SAP
conversion socket

Note 5

In-circuit emulator used to debug hardware or software when application systems
which use the 78K/0S Series are developed. The IE-78K0S-NS supports an integrated
debugger (ID78K0S-NS). The IE-78K0S-NS is used in combination with an interface
adapter for connection to an AC adapter, emulation probe, or host machine.

Adapter used to supply power from a 100- to 240-V AC outlet

Adapter required when using the PC-9800 series (excluding notebook PCs) as the host
machine for the IE-78K0S-NS (C bus supported)

PC card and interface cable required when using a notebook PC as the host machine
for the IE-78K0S-NS (PCMCIA socket supported)

Adapter required when using an IBM PC/AT
the IE-78K0S-NS (ISA bus supported)

Adapter required when using a PC equipped with a PCI bus as the host machine for
the IE-78K0S-NS

Emulation board used to emulate the peripheral hardware specific to the device. This
is used in combination with the in-circuit emulator.

Board to connect an in-circuit emulator to the target system. This is used in
combination with the EV-9200G-44

Conversion socket to connect the target system board on which a 44-pin plastic LQFP
can be mounted and the NP-44GB

Board to connect an in-circuit emulator to the target system. This is used in
combination with th e TG B- 0 4 4 SAP.

Conversion socket to connect the target system board on which a 44-pin plastic LQFP
can be mounted and the NP-44GB-TQ

TM

or compatible as the host machine for

Data Sheet U14022EJ1V0DS00

49

Debugging Tools(2/2)

NP-48GA
Emulation probe

SM78K0S
ID78K0S-NS
DF789177

Note 4

Notes 1, 2

Notes 1, 2

Notes 1, 2

Real-Time OS

MX78K0S

Notes 1, 2

Notes 1.

Based on the PC-9800 series (Japanese Windows
Based on IBM PC/AT and compatibles (Japanese Windows/English Windows)

2.

Based on the HP9000 series 700

3.

(NEWS-OSTM)
Product made by and available from Naito Densei Machida Mfg. Co., Ltd. ([phone]).

4.

Product made by TOKYO ELETECH CORPORATION.

5.

Refer to: Daimaru Kogyo, Ltd.

Board to connect an in-circuit emulator to the target system. This is used in
combination with the TGA-048SDP.

TGA-048SDP
conversion socket

Note 5

Conversion socket to connect the target system board on which a 48-pin plastic TQFP
(fine pitch) can be mounted and the NP-48GA

System simulator common to 78K/0S Series
Integrated debugger common to 78K/0S Series
Device file for µPD789167, 789177, 789167, and 789177Y Subseries

OS for 78K/0S Series

TM

(HP-UXTM), SPARCstationTM (SunOSTM, SorarisTM), and NEWS

Tokyo Electronic Division ([phone])
Osaka Electronic Division ([phone])

µµµµ

PD78F9177, 78F9177Y

TM

)

TM

Remark

The RA78K0S, CC78K0S, and SM78K0S can be used in combination with the DF789177.

50

Data Sheet U14022EJ1V0DS00

APPENDIX C. RELATED DOCUMENTS

Documents Related to Devices

µµµµ

PD78F9177, 78F9177Y

Document No.Document Name

Japanese English

PD789166, 167, 176, 177, 166Y, 167Y, 176Y , 177Y, 166(A), 167(A), 176(A), 177(A ),

µ

166Y(A), 167Y(A), 176Y(A), 177Y (A) Data Sheet

PD78F9177, 78F9177Y Data Sheet U14022J This manual

µ

PD789167, 789177, 789167Y, 789177Y Subseries User’s Manual U14186J U14186E

µ

78K/0S Series Inst ruction User’s Manual U11047J U11047E

U14017J U14017E

Document Related to Development Tools (User’s Manuals)

Document No.Document Name

Japanese English

RA78K0S Assembler Package

SM78K0S System Simulator Windows based Reference U11489J U11489E
SM78K Series System Simulator External Parts User

ID78K0S-NS Windows based Reference U12901J U12901E
IE-78K0S-NS In-circ ui t Emulator U13549J U13549E
IE-789177-NS-EM1 Emulation Board U14621J U14621E

Operation U11622J U11622E
Assembly Language U11599J U11599E
Structured Assembl y

Language
Operation U11816J U11816ECC78K0S C Compiler
Language U11817J U11817E

Open Interface
Specifications

U11623J U11623E

U10092J U10092E

Documents Related to Embedded Software (User’s Manuals)

Document No.Document Name

Japanese English

OS for 78K/0S Series MX78K0S Fundamental U12938J U12938E

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

Data Sheet U14022EJ1V0DS00

51

µµµµ

PD78F9177, 78F9177Y

Other Documents

Document No.Document Name

Japanese English
SEMICONDUCTOR SELECTION GUI DE Products & Packages (CD-ROM) X13769X
Semiconductor Device Mounting Technology Manual C10535J C10535E
Quality Grades on NEC Semic onductor Device C11531J C11531E
NEC Semiconductor Device Reliability /Quality Control System C10983J C10983E
Guide to Prevent Damage for Semi conductor Devices by El ectrostatic Disc harge (E SD) C11892J C11892E
Guide to Microcomputer-Relat ed P roducts by Third Party U11416J

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

The related document indicated in this publication may include preliminary versions. However, preliminary versions
are not marked as such.

−

52

Data Sheet U14022EJ1V0DS00

[MEMO]

µµµµ

PD78F9177, 78F9177Y

Data Sheet U14022EJ1V0DS00

53

µµµµ

PD78F9177, 78F9177Y

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

DD

pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

or GND with a resistor, if it is considered to have a possibility of

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

EEPROM is a trademark of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.

54

Data Sheet U14022EJ1V0DS00

µµµµ

PD78F9177, 78F9177Y

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Madrid Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore
Tel: [phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Electron Devices Division
Guarulhos-SP Brasil
Tel: [phone]
Fax: [phone]

Data Sheet U14022EJ1V0DS00

J00.7

55

µµµµ

PD78F9177, 78F9177Y

•

The information in this document is current as of August, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.

•

No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

•

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.

•

Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.

•

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.

•

NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4