Datasheet UPD784031YGK-BE9, UPD784031YGC-8BT, UPD784031YGC-3B9 Datasheet (NEC)

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Page 1

DATA SHEET

MOS INTEGRATED CIRCUIT

PD784031Y

16-/8-BIT SINGLE-CHIP MICROCONTROLLERS

The µPD784031Y is based on the µPD784031 with an I2C bus control function appended, and is ideal for

applications in audio-visual systems.

PD784031Y is a ROM-less version of µPD784035Y and 784036Y.

The

The functions are explained in detail in the following User’s Manual. Be sure to read this manual when

designing your system.

PD784038, 784038Y Subseries User’s Manual - Hardware : U11316E

78K/IV Series User’s Manual - Instruction : U10905E

FEATURES

78K/IV Series Pin-compatible with µPD78234 Subseries,

PD784026 Subseries, and µPD784038 Subseries Minimum instruction execution time: 125 ns (@ 32-MHz operation) I/O ports: 46 Serial interface: 3 channels UART/IOE (3-wire serial I/O): 2 channels

CSI (3-wire serial I/O, 2-wire serial I/O, I 1 channel PWM output: 2 outputs

C bus):

Timer/counter 16-bit Timer/counter x 3 units 16-bit Timer x 1 unit Standby function HALT/STOP/IDLE mode Clock division function Watchdog timer: 1 channel A/D converter: 8-bit resolution x 8 channels D/A converter: 8-bit resolution x 2 channels Supply voltage: VDD = 2.7 to 5.5 V

APPLICATION FIELDS

Cellular phones, cordless phones, audio-visual systems, etc.

ORDERING INFORMATION

Part Number Package

PD784031YGC-3B9

PD784031YGC-8BT

PD784031YGK-BE9 80-pin plastic TQFP (fine pitch) (12 x 12 mm) None 2048

80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm) 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm)

Internal ROM (Bytes) Internal RAM (Bytes)

None 2048 None 2048

Document No. U11504EJ1V0DS00 (1st edition) Date Published July 1997 N Printed in Japan

The information in this document is subject to change without notice.

The mark

shows major revised points.

1996

Page 2

78K/IV SERIES PRODUCT DEVELOPMENT

: Under mass production

: Under development

PD784031Y

Standard models

µPD784026

Enhanced A/D, 16-bit timer, and power management

ASSP models

µPD784908

Equipped with IEBus controller

µPD78F4943

For CD-ROM, 56-Kbyte flash memory

µPD784915

Equipped with analog circuit for software servo control VCR, enhanced timer

C bus supported

µPD784038Y

µPD784038

Enhanced internal memory capacity, pin compatible with the µPD784026

µPD784216Y

µPD784216

100 pins, enhanced I/O and internal memory capacity

µPD784054

µPD784046

Equipped with 10-bit A/D

Multimaster I

µPD784928

Enhanced function of the µPD784915

C bus supported

µPD784928Y

Multimaster I

µPD784225

80 pins, added ROM correction

Multimaster I

µPD784218

Enhanced internal memory capacity, added ROM correction

C bus supported

µPD784225Y

C bus supportedMultimaster I2C bus supported

µPD784218Y

Page 3

PD784031Y

FUNCTIONS

Item Function

Number of basic instructions 113 (mnemonics)

General-purpose register 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) Minimum instruction execution 125 ns/250 ns/500 ns/1000 ns (at 32 MHz)

time Internal memory ROM None

RAM 2048 bytes Memory space 1 Mbytes with program and data spaces combined I/O port Total 46

Input 8

I/O 34

Output 4

Pins with ancillary

Note

function

Real-time output port 4 bits x 2, or 8 bits x 1 Timer/counter Timer/counter 0: Timer register x 1 Pulse output

PWM output 12-bit resolution x 2 channels Serial interface UART/IOE (3-wire serial I/O) : 2 channels (on-chip baud rate generator)

A/D converter 8-bit resolution x 8 channels D/A converter 8-bit resolution x 2 channels Watchdog timer 1 channel Standby HALT/STOP/IDLE mode Interrupt

Supply voltage VDD = 2.7 to 5.5 V Package 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)

Pins with pull- 32

up resistor

LEDs direct 8

drive output

Transistor 8

direct drive

Capture register x 1 • Toggle output Compare register x 2 • PWM/PPG output

(16 bits) • One-shot pulse output Timer/counter 1: Timer register x 1 Pulse output

Capture register x 1 • Real-time output (4 bits x 2)

(8/16 bits) Capture/compare register x 1

Compare register x 1

Timer/counter 2: Timer register x 1 Pulse output

Capture register x 1 • Toggle output

(8/16 bits) Capture/compare register x 1 • PWM/PPG output

Compare register x 1

Timer 3: Timer register x 1 (8/16 bits) Compare register x 1

CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus) : 1 channel

Hardware source Software source Non-maskable Maskable Internal: 16, external: 6

24 (internal: 17, external: 7 (variable sampling clock input: 1)) BRK instruction, BRKCS instruction, operand error Internal: 1, external: 1

• 4 programmable priority levels

• 3 processing styles: vectored interrupt/macro service/context switching

80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm)

Note The pins with ancillary function are included in the I/O pins.

Page 4

PD784031Y

CONTENTS

1. DIFFERENCES AMONG MODELS IN µPD784038Y SUBSERIES.................................................. 6

2. MAJOR DIFFERENCES FROM µPD784026 SUBSERIES AND µPD78234 SUBSERIES.............. 7

3. PIN CONFIGURATION (Top View)................................................................................................... 8

4. BLOCK DIAGRAM ............................................................................................................................ 10

5. PIN FUNCTION ............................................................................................................................... 11

5.1 Port Pins ................................................................................................................................................ 11

5.2 Non-port Pins ........................................................................................................................................ 12

5.3 Types of Pin I/O Circuits and Connections for Unused Pins............................................................ 14

6. CPU ARCHITECTURE .................................................................................................................... 17

6.1 Memory Space....................................................................................................................................... 17

6.2 CPU Registers ....................................................................................................................................... 19

6.2.1 General-purpose registers .......................................................................................................... 19

6.2.2 Control registers.......................................................................................................................... 20

6.2.3 Special function registers (SFRs) ............................................................................................... 21

7. PERIPHERAL HARDWARE FUNCTIONS ..................................................................................... 26

7.1 Ports....................................................................................................................................................... 26

7.2 Clock Generation Circuit...................................................................................................................... 27

7.3 Real-time Output Port ........................................................................................................................... 29

7.4 Timer/Counter........................................................................................................................................ 30

7.5 PWM Output (PWM0, PWM1)................................................................................................................ 32

7.6 A/D Converter........................................................................................................................................ 33

7.7 D/A Converter........................................................................................................................................ 34

7.8 Serial Interface ...................................................................................................................................... 35

7.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ...................................................... 36

7.8.2 Clocked serial interface (CSI) ..................................................................................................... 38

7.9 Edge Detection Function...................................................................................................................... 39

7.10 Watchdog Timer .................................................................................................................................... 40

8. INTERRUPT FUNCTION ................................................................................................................. 41

8.1 Interrupt Sources .................................................................................................................................. 41

8.2 Vectored Interrupt................................................................................................................................. 43

8.3 Context Switching................................................................................................................................. 44

8.4 Macro Service........................................................................................................................................ 44

8.5 Application Example of Macro Service............................................................................................... 45

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PD784031Y

9. LOCAL BUS INTERFACE .............................................................................................................. 47

9.1 Memory Expansion ............................................................................................................................... 47

9.2 Memory Space....................................................................................................................................... 48

9.3 Programmable Wait .............................................................................................................................. 49

9.4 Pseudo Static RAM Refresh Function................................................................................................. 49

9.5 Bus Hold Function ................................................................................................................................ 49

10. STANDBY FUNCTION .................................................................................................................... 50

11. RESET FUNCTION ......................................................................................................................... 51

12. INSTRUCTION SET ........................................................................................................................ 52

13. ELECTRICAL SPECIFICATIONS ................................................................................................... 57

14. PACKAGE DRAWINGS .................................................................................................................. 77

15. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 80

APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 82

APPENDIX B. RELATED DOCUMENTS ............................................................................................... 84

Page 6

PD784031Y

1. DIFFERENCES AMONG MODELS IN µPD784038Y SUBSERIES

The only difference among the µPD784031Y, 784035Y, 784036Y, 784037Y, and 784038Y lies in the internal memory

capacity.

The µPD78P4038Y is provided with a 128-Kbyte one-time PROM or EPROM instead of the mask ROM of the

PD784035Y, 784036Y, 784037Y, and 784038Y. These differences are summarized in Table 1-1.

Table 1-1. Differences among Models in µPD784038Y Subseries

Part NumberµPD784031Y

Item Internal ROM None 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes 128 Kbytes

Internal RAM 2048 bytes 3584 bytes 4352 bytes Package 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)

80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm)

PD784035YµPD784036YµPD784037YµPD784038YµPD78P4038Y

(mask ROM) (mask ROM) (mask ROM) (mask ROM)

(one-time PROM or EPROM)

80-pin ceramic WQFN (14 x 14 mm)

Page 7

PD784031Y

2. MAJOR DIFFERENCES FROM µPD784026 SUBSERIES AND µPD78234 SUBSERIES

Series Name Item Number of basic instructions 113 65

(mnemonics) Minimum instruction execution time 125 ns 160 ns 333 ns

Memory space (program/data) 1 Mbytes combined 64 Kbytes/1 Mbytes Timer/counter 16-bit timer/counter x 1 16-bit timer/counter x 1

Clock output function Provided None Watchdog timer Provided None Serial interface

Interrupt Context Provided None

switching

PD784038Y Subseries

PD784038 Subseries

(@ 32-MHz operation) (@ 25-MHz operation) (@ 12-MHz operation)

8-/16-bit timer/counter x 2 8-bit timer/counter x 2 8-/16-bit timer x 1 8-bit timer x 1

UART/IOE (3-wire serial I/O) x 2 channels CSI (3-wire serial I/O, 2-wire serial I/O, I2C

Note

bus

) x 1 channel

PD784026 Subseries

UART/IOE (3-wire serial I/O) x 2 channels CSI (3-wire serial I/O, SBI) x 1 channel

PD78234 Subseries

UART x 1 channel CSI (3-wire serial I/O, SBI) x 1 channel

Priority 4 levels 2 levels Standby function HALT/STOP/IDLE mode HALT/STOP mode Operating clock Selectable from fXX/2, fXX/4, fXX/8, and fXX/16 Fixed to fXX/2 Pin function MODE pin None Specifies ROM-less mode

(always high level with

PD78233 and 78237)

TEST pin Device test pin None

Usually, low level

Package

80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)

80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm)

80-pin plastic TQFP (fine pitch) (12 x 12 mm)

80-pin ceramic WQFN (14 x 14 mm):

PD78P4038Y and

78P4038 only

80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)

80-pin plastic TQFP (fine pitch) (12 x 12 mm):

PD784021 only

80-pin ceramic WQFN (14 x 14 mm):

PD78P4026 only

80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)

94-pin plastic QFP (20 x 20 mm)

84-pin plastic QFJ (1150 x 1150 mil)

94-pin ceramic WQFN (20 x 20 mm):

PD78P238 only

NoteµPD784038Y Subseries only

Page 8

3. PIN CONFIGURATION (Top View)

• 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)

PD784031YGC-3B9

• 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm)

PD784031YGC-8BT

• 80-pin plastic TQFP (fine pitch) (12 x 12 mm)

PD784031YGK-BE9

PD784031Y

P32/SCK0/SCL

P33/SO0/SDA

P34/TO0 P35/TO1 P36/TO2 P37/TO3

RESET

DD1

X2 X1

SS1

P00 P01 P02 P03 P04 P05 P06 P07

P67/REFRQ/HLDAK

REF3AVREF2

P31/TxD/SO1

P30/RxD/SI1

P27/SI0

P26/INTP5

P25/INTP4/ASCK/SCK1

P24/INTP3

P23/INTP2/CI

P22/INTP1

P21/INTP0

P20/NMI

ANO1

80 6179 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21 4022 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

ANO0

AVSSAV

REF1AVDD

P77/ANI7

P76/ANI6

P75/ANI5

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 V

DD0

P17 P16 P15 P14/TxD2/SO2 P13/TxD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0

Note

TEST V

SS0

ASTB AD0 AD1 AD2

P66/WAIT/HLDRQ

Note Directly connect the TEST pin to V

P63/A19

P62/A18

SS0.

P61/A17

P60/A16

A15

A14

A13

A12

A11

A10

AD7

AD6

AD5

AD4

AD3

Page 9

PD784031Y

A8 to A19 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK, ASCK2 : Asynchronous Serial Clock ASTB : Address Strobe

DD : Analog Power Supply

AV AVREF1 to AVREF3 : Reference Voltage

SS : Analog Ground

AV CI : Clock Input HLDAK : Hold Acknowledge HLDRQ : Hold Request INTP0 to INTP5 : Interrupt from Peripherals NMI : Non-maskable Interrupt P00 to P07 : Port0 P10 to P17 : Port1 P20 to P27 : Port2 P30 to P37 : Port3 P60 to P63, P66, P67

: Port6

P70 to P77 : Port7 PWM0, PWM1 : Pulse Width Modulation Output RD : Read Strobe REFRQ : Refresh Request RESET : Reset RxD, RxD2 : Receive Data SCK0 to SCK2 : Serial Clock SCL : Serial Clock SDA : Serial Data SI0 to SI2 : Serial Input SO0 to SO2 : Serial Output TEST : Test TO0 to TO3 : Timer Output TxD, TxD2 : Transmit Data

DD0, VDD1 : Power Supply

V VSS0, VSS1 : Ground WAIT : Wait WR : Write Strobe X1, X2 : Crystal

Page 10

4. BLOCK DIAGRAM

PD784031Y

NMI

INTP0 to INTP5

INTP3

TO0 TO1

INTP0

INTP1

INTP2/CI

TO2 TO3

P00

P03

P04

P07

PWM0 PWM1

ANO0 ANO1

REF2

AV AV

REF3

ANI0 to ANI7

REF1

INTP5

PROGRAMMABLE INTERRUPT CONTROLLER

TIMER/COUNTER0

(16 BITS)

TIMER/COUNTER1

(16 BITS)

TIMER/COUNTER2

(16 BITS)

TIMER3

(16 BITS)

REAL-TIME OUTPUT PORT

PWM

D/A CONVERTER

A/D CONVERTER

78K/IV

CPU CORE

RAM

WATCHDOG

TIMER

UART/IOE2

BAUD-RATE

GENERATOR

UART/IOE1

BAUD-RATE

GENERATOR

CLOCKED SERIAL INTERFACE

BUS I/F

PORT0

PORT1

PORT2

PORT3

PORT6

PORT7

SYSTEM CONTROL

RxD/SI1 TxD/SO1

ASCK/SCK1

RxD2/SI2 TxD2/SO2

ASCK2/SCK2

SCK0/SCL SO0/SDA SI0

ASTB AD0

AD7

A15

A16

A19 RD WR WAIT/HLDRQ REFRQ/HLDAK

P00

P07

P10

P17

P27

P20

P37

P30

P63

P60

P67

P66

P70

P77 RESET

TEST X1 X2

DD0,VDD1

V V

SS0,VSS1

Page 11

5. PIN FUNCTION

5.1 Port Pins

Pin Name I/O Alternate Function Function

PD784031Y

P00 to P07 I/O –

P10 I/O PWM0 P11 PWM1 P12 ASCK2/SCK2 P13 RxD2/SI2 P14 TxD2/SO2 P15 to P17 – P20 Input NMI P21 INTP0 P22 INTP1 P23 INTP2/CI P24 INTP3 P25 INTP4/ASCK/SCK1 P26 INTP5 P27 SI0

Port 0 (P0):

• 8-bit I/O port

• Can be used as real-time output port (4 bits x 2).

• Can be set in input or output mode bitwise.

• Pins set in input mode can be connected to internal pull-up resistors by software.

• Can drive transistor.

Port 1 (P1):

• 8-bit I/O port

• Can be set in input or output mode bitwise.

• Pins set in input mode can be connected to internal pull-up resistors by software.

• Can drive LEDs.

Port 2 (P2):

• 8-bit input port

• P20 cannot be used as general-purpose port pin (non-maskable interrupt). However, its input level can be checked by interrupt routine.

• P22 through P27 can be connected to internal pull-up resistors by software in 6-bit units.

• P25/INTP4/ASCK/SCK1 pin can operate as SCK1 output pin if so specified by CSIM1.

P30 I/O RxD/S1 P31 TxD/SO1 P32 SCK0/SCL P33 SO0/SDA P34 to P37 TO0 to TO3 P60 to P63 I/O A16 to A19 P66 WAIT/HLDRQ P67 REFRQ/HLDAK

P70 to P77 I/O AN10 to AN17

Port 3 (P3):

• 8-bit I/O port

• Can be set in input or output mode bitwise.

• Pins set in input mode can be connected to internal pull-up resistors by software.

Port 6 (P6):

• P60 through P63 is dedicated ports for output.

• P66 and P67 can be set in input or output mode bitwise.

• Pins set in input mode can be connected to internal pull-up resistors by software.

Port 7 (P7):

• 8-bit I/O port

• Can be set in input or output mode bitwise.

Page 12

PD784031Y

5.2 Non-port Pins

Pin Name I/O Alternate Function Function TO0 to TO3 Output P34 to P37 Timer output CI Input P23/INTP2 Count clock input to timer/counter 2 RxD Input P30/SI1 Serial data input (UART0) RxD2 P13/SI2 Serial data input (UART2) TxD Output P31/SO1 Serial data output (UART0) TxD2 P14/SO2 Serial data output (UART2) ASCK Input P25/INTP4/SCK1 Baud rate clock input (UART0) ASCK2 P12/SCK2 Baud rate clock input (UART2) SDA I/O P33/SO0 Serial data input/output (2-wire serial I/O, I2C bus) SI0 Input P27 Serial data input (3-wire serial I/O0) SI1 P30/RxD Serial data input (3-wire serial I/O1) SI2 P13/RxD2 Serial data input (3-wire serial I/O2) SO0 Output P33/SDA Serial data output (3-wire serial I/O0) SO1 P31/TxD Serial data output (3-wire serial I/O1) SO2 P14/TxD2 Serial data output (3-wire serial I/O2) SCK0 I/O P32/SCL Serial clock input/output (3-wire serial I/O0) SCK1 P25/INTP4/ASCK Serial clock input/output (3-wire serial I/O1) SCK2 P12/ASCK2 Serial clock input/output (3-wire serial I/O2) SCL P32/SCK0 Serial clock input/output (2-wire serial I/O, I2C bus) NMI Input P20 External interrupt requests – INTP0 P21 • Count clock input to timer/counter 1

• Capture trigger signal of CR11 or CR12

INTP1 P22 • Count clock input to timer/counter 2

• Capture trigger signal of CR22

INTP2 P23/CI • Count clock input to timer/counter 2

• Capture trigger signal of CR21

INTP3 P24 • Count clock input to timer/counter 0

• Capture trigger signal of CR02 INTP4 P25/ASCK/SCK1 – INTP5 P26 Conversion start trigger input to A/D converter AD0 to AD7 I/O – Time-division address/data bus (for external memory connection) A8 to A15 Output – Higher address bus (for external memory connection) A16 to A19 Output P60 to P63 Higher address when address is extended (for external memory connection) RD Output – Read strobe to external memory WR Output – Write strobe to external memory WAIT Input P66/HLDRQ Wait insertion REFRQ Output P67/HLDAK Refresh pulse output to external pseudo static memory

HLDRQ Input P66/WAIT Bus hold request input HLDAK Output P67/REFRQ Bus hold acknowledge output ASTB Output – Latch timing output of time-division address (A0 through A7)

(when accessing external memory)

Page 13

Pin Name I/O Alternate Function Function RESET Input – Chip reset X1 Input – Crystal connection for system clock oscillation X2 – (Clock can also be input to X1.) ANI0 to ANI7 Input P70 to P77 Analog voltage input to A/D converter ANO0, ANO1 Output – Analog voltage output from D/A converter AVREF1 – – Reference voltage to A/D converter AVREF2, AVREF3 AVDD A/D converter power supply AVSS A/D converter GND

Note 1

VDD0

Note 1

VDD1

Note 2

VSS0

Note 2

VSS1

TEST Directly connect to VSS0 (IC test pin).

Reference voltage to D/A converter

Power supply of port Power supply except for port GND of port GND except for port

Notes 1. Provide the same potential to VDD0 and VDD1.

2. Provide the same potential to V

SS0 and VSS1.

PD784031Y

Page 14

5.3 Types of Pin I/O Circuits and Connections for Unused Pins

Table 5-1 shows types of pin I/O circuits and the connections for unused pins. For the input/output circuit of each type, refer to Figure 5-1.

Table 5-1. Types of Pin I/O Circuits and Connections for Unused Pins (1/2)

Pin Name I/O Circuit Type I/O Recommended Connection for Unused Pins P00 to P07 5-H I/O Input: Connect to VDD0. P10/PWM0 Output: Open

P11/PWM1 P12/ASCK2/SCK2 8-C P13/RxD2/SI2 5-H P14/TxD2/SO2 P15 to P17 P20/NMI 2 Input Connect to VDD0 or VSS0. P21/INTP0 P22/INTP1 2-C Connect to VDD0.

PD784031Y

P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-C I/O Input: Connect to VDD0.

Output: Open P26/INTP5 2-C Input Connect to VDD0. P27/SI0 P30/RxD/SI1 5-H I/O Input: Connect to VDD0. P31/TxD/SO1 Output: Open P32/SCK0/SCL 10-B P33/SO0/SDA P34/TO0 to P37/TO3 5-H AD0 to AD7 A8 to A15 Output P60/A16 to P63/A19 RD WR P66/WAIT/HLDRQ I/O Input: Connect to VDD0. P67/REFRQ/HLDAK Output: Open P70/ANI0 to P77/ANI7 20-A Input: Connect to VDD0 or VSS0.

ANO0, ANO1 12 Output Open

Note

Open

Output: Open

ASTB 4-B

Note I/O circuit type of these pins is 5-H. However these pins perform only as output by an internal circuit.

Page 15

Table 5-1. Types of Pin I/O Circuits and Connections for Unused Pins (2/2)

Pin Name I/O Circuit Type I/O Recommended Connection for Unused Pins RESET 2 Input – TEST 1-A Directly connect to VSS0. AVREF1 to AVREF3 – Connect to VSS0. AVSS AVDD Connect to VDD0.

PD784031Y

Caution Connect an I/O pin whose input/output mode is unstable to V

DD0 via a resistor of several 10 kΩ

(especially if the voltage on the reset input pin rises higher than the low-level input level on power application or when the mode is switched between input and output by software).

Remark Because the circuit type numbers shown in the above table are commonly used with all the models in the 78K

Series, these numbers of some models are not serial (because some circuits are not provided to some models).

Page 16

Figure 5-1. Types of Pin I/O Circuits

PD784031Y

Type 1-A

DD0

SS0

Type 2

Schmitt trigger input with hysteresis characteristics

Type 4-B

data

output

disable

DD0

SS0

OUT

Type 2-C

DD0

Schmitt trigger input with hysteresis characteristics

Type 5-H

pullup

enable

data

output

disable

DD0

SS0

pullup enable

DD0

IN/OUT

Push-pull output that can go into a high-impedance state (with both P-ch and N-ch off)

Type 8-C

pullup

enable

data

output

disable

DD0

SS0

Type 10-B

pullup

enable

DD0

data

open drain

output disable

SS0

input

enable

Type 12

DD0

Analog output voltage

IN/OUT

DD0

Type 20-A

data

OUT

DD0

IN/OUT

output

disable

Comparator

+ –

REF

(threshold voltage)

SS0

P N

input

enable

Page 17

PD784031Y

6. CPU ARCHITECTURE

6.1 Memory Space

A memory space of 1 Mbytes can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed after reset cancellation, and must not be used more than once.

(1) When LOCATION 0 instruction is executed

The internal data area is mapped in 0F700H to 0FFFFH.

(2) When LOCATION 0FH instruction is executed

The internal data area is mapped in FF700H to FFFFFH.

Page 18

Figure 6-1. Memory Map of

PD784031Y

On execution of

LOCATION 0 instruction

HFFFFF

External memory (960 Kbytes)

H00001 HFFFF0

Special function registers (SFR)

HFDFF0 H0DFF0

H00FF0 HFFEF0

H00DF0

HFFCF0

(256 bytes)

Internal RAM (2 Kbytes)

H007F0 HFF6F0

External memory (63232 bytes)

H00000

Note

HFFEF0

General-purpose registers (128 bytes)

H08EF0 HF7EF0

H13EF0

Macro service control word area (44 bytes)

H60EF0

Data area (512 bytes)

H00DF0 HFFCF0

Program/data area (1536 bytes)

H007F0

H00010 HFFF00

CALLF entry area (2 Kbytes)

H00800 HFF700

H08000 HF7000

CALLT table area (64 bytes)

H04000 HF3000

Vector table area (64 bytes)

H00000

On execution of

LOCATION 0FH instruction

HFFFFF

Special function registers (SFR)

HFDFFF H0DFFF

HFFEFF

H00FFF HFFEFF

(256 bytes)

Internal RAM (2 Kbytes)

H08EFF HF7EFF

HEFF

H60EFF

H00DFF HFFCFF

H007FF HFF6FF

External memory (1046272 bytes)

H007FF

HFFF00

H00800 HFF700

H08000 HF7000

H00001 HFFFF0

Note

H00000

PD784031Y

Note Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Page 19

(

PD784031Y

6.2 CPU Registers

6.2.1 General-purpose registers

Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers.

Eight banks of these registers are available which can be selected by using software or the context switching function.

The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal RAM.

Figure 6-2. General-purpose Register Format

VVP (RG4)

UUP (RG5)

TDE (RG6)

WHL (RG7)

Parentheses

A (R1)

AX (RP0)

B (R3)

BC (RP1)

VP (RP4)

R11

UP (RP5)

D (R13)

DE (RP6)

H (R15)

HL (RP7)

) indicate an absolute name.

X (R0)

C (R2)

RP2

RP3

R10

E (R12)

L (R14)

8 banks

Caution Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively,

by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of the 78K/III Series.

Page 20

6.2.2 Control registers

(1) Program counter (PC)

The program counter is a 20-bit register whose contents are automatically updated when the program is executed.

Figure 6-3. Program Counter (PC) Format

19 0

(2) Program status word (PSW)

This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed.

Figure 6-4. Program Status Word (PSW) Format

15 14 13 12 11 10 9 8

UF RBS2 RBS1 RBS0 – – – –PSWH

PD784031Y

PSW

76543210 S Z RSS

Note

AC IE P/V 0 CYPSWL

Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except when

the software for the 78K/III Series is used.

(3) Stack pointer (SP)

This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this pointer.

Figure 6-5. Stack Pointer (SP) Format

23 0

0000

Page 21

PD784031Y

6.2.3 Special function registers (SFRs)

The special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are allocated. These registers are mapped to a 256-byte space of addresses 0FF00H

Note

through 0FFFFH

Note On execution of the LOCATION 0 instruction. FFF00H through FFFFFH on execution of the LOCATION 0FH

instruction.

Caution Do not access an address in this area to which no SFR is allocated. If such an address is accessed by

mistake, the inputting the reset signal.

Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:

• Symbol................................ Symbol indicating an SFR. This symbol is reserved for NEC’s assembler (RA78K4).

PD784031Y may be in the deadlock status. This deadlock status can be cleared only by

It can be used as an sfr variable by the #pragma sfr command with the C compiler (CC78K4).

• R/W..................................... Indicates whether the SFR is read-only, write-only, or read/write.

R/W : Read/write R : Read-only W : Write-only

• Bit units for manipulation .... Bit units in which the value of the SFR can be manipulated.

SFRs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. To specify the address of this SFR, describe an even address. SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction.

• After reset........................... Indicates the status of the register when the RESET signal has been input.

Page 22

PD784031Y

Table 6-1. Special Function Registers (SFRs) (1/4)

Note

Address

0FF00H Port 0 P0 R/W √√– Undefined 0FF01H Port 1 P1 √√– 0FF02H Port 2 P2 R √√– 0FF03H Port 3 P3 R/W √√– 0FF06H Port 6 P6 √√– 00H 0FF07H Port 7 P7 √√– Undefined 0FF0EH Port 0 buffer register L P0L √√–

Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset

1 bit 8 bits 16 bits

0FF0FH 0FF10H Compare register (timer/counter 0) CR00 – – √ 0FF12H Capture/compare register (timer/counter 0) CR01 – – √ 0FF14H Compare register L (timer/counter 1) 0FF15H Compare register H (timer/counter 1) – – – 0FF16H Capture/compare register L (timer/counter 1) 0FF17H Capture/compare register H (timer/counter 1) – – – 0FF18H Compare register L (timer/counter 2) 0FF19H Compare register H (timer/counter 2) – – – 0FF1AH Capture/compare register L (timer/counter 2) 0FF1BH Capture/compare register H (timer/counter 2) – – – 0FF1CH Compare register L (timer 3) 0FF1DH Compare register H (timer 3) – – – 0FF20H Port 0 mode register PM0 √√– FFH 0FF21H Port 1 mode register PM1 √√– 0FF23H Port 3 mode register PM3 √√– 0FF26H Port 6 mode register PM6 √√– 0FF27H Port 7 mode register PM7 √√–

Port 0 buffer register H

P0H √√–

CR10

CR11

CR20

CR21

CR30

CR10W

CR11W

CR20W

CR21W

CR30W

– √√

0FF2EH Real-time output port control register RTPC √√– 00H 0FF30H Capture/compare control register 0 CRC0 – √ – 10H 0FF31H Timer output control register TOC √√– 00H 0FF32H Capture/compare control register 1 CRC1 – √ – 0FF33H Capture/compare control register 2 CRC2 – √ – 10H

Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is

added to this value.

Page 23

PD784031Y

Table 6-1. Special Function Registers (SFRs) (2/4)

Note 1

Address

0FF36H Capture register (timer/counter 0) CR02 R – – √ 0000H 0FF38H Capture register L (timer/counter 1) 0FF39H Capture register H (timer/counter 1) – – –

Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset

1 bit 8 bits 16 bits

CR12

CR12W

– √√

0FF3AH Capture register L (timer/counter 2) 0FF3BH Capture register H (timer/counter 2) – – – 0FF41H Port 1 mode control register PMC1 R/W √√– 00H 0FF43H Port 3 mode control register PMC3 √√– 0FF4EH Pull-up resistor option register PUO √√– 0FF50H Timer register 0 TM0 R – – √ 0000H 0FF51H –– 0FF52H Timer register 1 TM1 0FF53H – – – 0FF54H Timer register 2 TM2 0FF55H – – – 0FF56H Timer register 3 TM3 0FF57H – – – 0FF5CH Prescaler mode register 0 PRM0 R/W – √ – 11H 0FF5DH Timer control register 0 TMC0 √√ – 00H 0FF5EH Prescaler mode register 1 PRM1 – √ – 11H 0FF5FH Timer control register 1 TMC1 √√– 00H 0FF60H D/A conversion value setting register 0 DACS0 – √ –

CR22

CR22W

TM1W

TM2W

TM3W

– √√

0FF61H D/A conversion value setting register 1 DACS1 – √ – 0FF62H D/A converter mode register DAM √√– 03H 0FF68H A/D converter mode register ADM √√– 00H 0FF6AH A/D conversion result register ADCR R – √ – Undefined 0FF70H PWM control register PWMC R/W √√– 05H 0FF71H PWM prescaler register PWPR – √ – 00H 0FF72H PWM modulo register 0 PWM0 – – √ Undefined 0FF74H PWM modulo register 1 PWM1 – – √ 0FF7DH One-shot pulse output control register OSPC √√ – 00H 0FF80H I2C bus control register IICC √√– 0FF81H Prescaler mode register for serial clock SPRM – √ – 04H 0FF82H Clocked serial interface mode register CSIM √√– 00H 0FF83H Slave address register SVA

Note 2√Note 3

R/W

√ – 01H

Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H”

is added to this value.

2. Bit 0 is read-only.

3. Only bit 0 can be manipulated in bit units.

Page 24

Table 6-1. Special Function Registers (SFRs) (3/4)

Note 1

Address

0FF84H Clocked serial interface mode register 1 CSIM1 R/W √√– 00H 0FF85H Clocked serial interface mode register 2 CSIM2 √√– 0FF86H Serial shift register SIO – √ – 0FF88H Asynchronous serial interface mode register ASIM √√– 0FF89H Asynchronous serial interface mode register 2 ASIM2 √√– 0FF8AH Asynchronous serial interface status register ASIS R √√–

Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset

1 bit 8 bits 16 bits

PD784031Y

0FF8BH 0FF8CH Serial receive buffer: UART0 RXB – √ – Undefined

0FF8DH Serial receive buffer: UART2 RXB2 R – √ –

0FF90H Baud rate generator control register BRGC – √ – 00H 0FF91H Baud rate generator control register 2 BRGC2 – √ – 0FFA0H External interrupt mode register 0 INTM0 √√– 0FFA1H External interrupt mode register 1 INTM1 √√– 0FFA4H Sampling clock select register SCS0 – √ – 0FFA8H In-service priority register ISPR R √√– 0FFAAH Interrupt mode control register IMC R/W √√– 80H 0FFACH Interrupt mask register 0L MK0L MK0 √√√FFFFH 0FFADH Interrupt mask register 0H 0FFAEH Interrupt mask register 1L MK1L √√– FFH 0FFC0H Standby control register STBC – √ 0FFC2H Watchdog timer mode register WDM – √

Asynchronous serial interface status register 2

Serial transmit shift register: UART0 TXS W – √ – Serial shift register: IOE1 SIO1 R/W – √ –

Serial transmit shift register: UART2 TXS2 W – √ – Serial shift register: IOE2 SIO2 R/W – √ –

ASIS2 √√–

MK0H

√√

Note 2

– 30H

– 00H 0FFC4H Memory expansion mode register MM √√– 20H 0FFC5H Hold mode register HLDM √√– 00H 0FFC6H Clock output mode register CLOM √√– 0FFC7H Programmable wait control register 1 PWC1 – √ – AAH 0FFC8H Programmable wait control register 2 PWC2 – – √ AAAAH

Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H”

is added to this value.

2. Data can be written by using only dedicated instructions such as MOV STBC, #byte and MOV WDM, #byte, and cannot be written with any other instructions.

Page 25

PD784031Y

Table 6-1. Special Function Registers (SFRs) (4/4)

Note

Address

0FFCCH Refresh mode register RFM R/W √√– 00H 0FFCDH Refresh area specification register RFA √√– 0FFCFH Oscillation stabilization time specification OSTS – √ –

0FFD0H to External SFR area – √√–– 0FFDFH

0FFE0H Interrupt control register (INTP0) PIC0 √√– 43H 0FFE1H Interrupt control register (INTP1) PIC1 √√– 0FFE2H Interrupt control register (INTP2) PIC2 √√– 0FFE3H Interrupt control register (INTP3) PIC3 √√– 0FFE4H Interrupt control register (INTC00) CIC00 √√ – 0FFE5H Interrupt control register (INTC01) CIC01 √√ –

Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset

1 bit 8 bits 16 bits

0FFE6H Interrupt control register (INTC10) CIC10 √√ – 0FFE7H Interrupt control register (INTC11) CIC11 √√ – 0FFE8H Interrupt control register (INTC20) CIC20 √√ – 0FFE9H Interrupt control register (INTC21) CIC21 √√ – 0FFEAH Interrupt control register (INTC30) CIC30 √√ – 0FFEBH Interrupt control register (INTP4) PIC4 √√– 0FFECH Interrupt control register (INTP5) PIC5 √√– 0FFEDH Interrupt control register (INTAD) ADIC √√– 0FFEEH Interrupt control register (INTSER) SERIC √√–

0FFEFH Interrupt control register (INTSR) SRIC √√–

Interrupt control register (INTCSI1) CSIIC1 √√– 0FFF0H Interrupt control register (INTST) STIC √√– 0FFF1H Interrupt control register (INTCSI) CSIIC √√– 0FFF2H Interrupt control register (INTSER2) SERIC2 √√–

0FFF3H Interrupt control register (INTSR2) SRIC2 √√–

Interrupt control register (INTCSI2) CSIIC2 √√– 0FFF4H Interrupt control register (INTST2) STIC2 √√– 0FFF5H Interrupt control register (INTSPC) SPCIC √√–

Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is

added to this value.

Page 26

PD784031Y

7. PERIPHERAL HARDWARE FUNCTIONS

7.1 Ports

The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the function

of each port. Ports 0 through 6 can be connected to internal pull-up resistors by software when inputting.

Figure 7-1. Port Configuration

P00

Port 0

P07 P10

Port 1

P17

P20 to P27

P30

P37 P60

P63 P66

P67

P70

P77

Port 2

Port 3

Port 6

Port 7

Page 27

PD784031Y

Table 7-1. Port Functions

Port Name Pin Name Function Specification of Pull-up Resistor

Connection by Software

Port 0 P00 to P07 • Can be set in input or output mode in 1-bit units. All port pins in input mode

• Can operate as 4-bit real-time output port (P00 through P03 and P04 through P07).

• Can drive transistor.

Port 1 P10 to P17 • Can be set in input or output mode in 1-bit units. All port pins in input mode

• Can drive LEDs.

Port 2 P20 to P27 • Input port In 6-bit units (P22 through P27) Port 3 P30 to P37 • Can be set in input or output mode in 1-bit units. All port pins in input mode Port 6 P60 to P63 • Output only All port pins in input mode

P66, P67 • Can be set in input or output mode in 1-bit units.

Port 7 P70 to P77 • Can be set in input or output mode in 1-bit units. –

7.2 Clock Generation Circuit

An on-chip clock generation circuit necessary for operation is provided. This clock generation circuit has a divider circuit. If high-speed operation is not necessary, the internal operating frequency can be lowered by the divider circuit to reduce the current consumption.

Figure 7-2. Block Diagram of Clock Generation Circuit

Oscillation circuit

Remark fXX : oscillation frequency or external clock input

fCLK: internal operating frequency

1/2 1/2 1/2 1/2

UART/IOE INTP0 noise reduction circuit Oscillation stabilization timer

Selector

CLK

f CPU Peripheral circuit

Page 28

Figure 7-3. Example of Using Oscillation Circuit

(1) Crystal/ceramic oscillation

PD784031Y

SS1

(2) External clock

• EXTC bit of OSTS = 1 • EXTC bit of OSTS = 0

PD784031Y

PD74HC04, etc.

PD784031Y

X2Open

Caution When using the clock oscillation circuit, wire the dotted portion in the above figure as follows to avoid

adverse influences of wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines.

• Do not route the wiring in the vicinity of lines through which a high alternating current flows.

• Always keep the potential at the ground point of the capacitor in the oscillation circuit the same

SS1. Do not ground to a ground pattern through which a high current flows.

as V

• Do not extract signals from the oscillation circuit.

Page 29

PD784031Y

7.3 Real-time Output Port

The real-time output port outputs data stored in a buffer in synchronization with the coincidence interrupt generated by timer/counter 1 or with an external interrupt. As a result, pulses without jitter can be output.

The real-time output port is therefore ideal for applications where arbitrary patterns must be output at specific intervals (such as open loop control of a stepping motor).

The real-time output port mainly consists of port 0 and port 0 buffer registers (P0H and P0L) as shown in Figure 7-4.

Figure 7-4. Block Diagram of Real-time Output Port

Internal bus

844

INTP0 (from external source) INTC10 (from timer/counter 1) INTC11 (from timer/counter 1)

Real-time output port

control register (RTPC)

Output trigger

control circuit

Buffer register

P0H P0L

Output latch (P0)

P07 P00

Page 30

PD784031Y

7.4 Timer/Counter

Three units of timers/counters and one unit of timer are provided. Because a total of seven interrupt requests are supported, these timers/counters and timer can be used as seven units

of timers/counters.

Table 7-2. Operations of Timers/Counters

Name Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer 3

Item Count width 8 bits – √√√

16 bits √√√√

Operation mode

Function Timer output 2ch – 2ch –

Interval timer 2ch 2ch 2ch 1ch External event counter √√√– One-shot timer – – √ –

Toggle output √ – √ – PWM/PPG output √ – √ –

One-shot pulse output Real-time output – √ –– Pulse width measurement 1 input 1 input 2 inputs – Number of interrupt requests 2221

Note

√ –––

Note The one-shot pulse output function makes a pulse output level active by software and inactive by hardware (interrupt

request signal). This function is different in nature from the one-shot timer function of timer/counter 2.

Page 31

Timer/counter 0

Figure 7-5. Block Diagram of Timers/Counters

Clear control

Software trigger

PD784031Y

INTP3

Timer/counter 1

INTP0

XX/8

Edge detection

XX/8

Edge detection

Prescaler

Event input

INTP3

INTP0

Selector

Capture/Compare register

Timer register 0

(TM0)

Compare register

(CR00)

Compare register

(CR01)

Capture register

(CR02)

Clear control

Timer register 1

(TM1/TM1W)

Compare register

(CR10/CR10W)

(CR11/CR11W)

Capture register

(CR12/CR12W)

Match

OVF

TO0

TO1

Pulse output control

INTC00 INTC01

OVF

INTC10

To real-time output port

INTC11

Timer/counter 2

XX/8

INTP1

Edge detection

INTP2/CI

Timer 3

XX/8

Remark OVF: overflow flag

Prescaler

INTP2

Prescaler

INTP1

Selector

Capture/Compare register

Clear control

Timer register 2

(TM2/TM2W)

Compare register

(CR20/CR20W)

(CR21/CR21W)

Capture register

(CR22/CR22W)

Timer register 3

(TM3/TM3W)

Compare register

(CR30/CR30W)

Match

Clear

Match

OVF

TO2

TO3

Pulse output control

INTC20 INTC21

CSI

INTC30

Page 32

PD784031Y

7.5 PWM Output (PWM0, PWM1)

Two channels of PWM (pulse width modulation) output circuits with a resolution of 12 bits and a repeat frequency of

62.5 kHz (f These outputs are ideal for controlling the speed of a DC motor.

CLK = 16 MHz) are provided. Both these PWM output channels can select a high or low level as the active level.

Figure 7-6. Block Diagram of PWM Output Unit

Internal bus

CLK

Prescaler

Remark n = 0 or 1

PWM modulo register

PWMn

8-bit down counter

1/256

0347815

Pulse control circuit

4-bit counter

PWM control

Reload control

Output

control

PWMn (output pin)

Page 33

Internal bus

ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7

INTP5

Input selector

Edge

detection

circuit

Conversion trigger

Sample & hold circuit

Voltage comparator

Successive approximation

Control

Circuit

INTAD

Series resistor string

R/2

Tap selector

R/2

REF1

Trigger enable

A/D converter mode

A/D conversion result

PD784031Y

7.6 A/D Converter

An analog-to-digital (A/D) converter with eight multiplexed inputs (ANI0 through ANI7) is provided. This A/D converter is of successive approximation type. The result of conversion is retained by an 8-bit A/D conversion

result register (ADCR). Therefore, high-speed, high-accuracy conversion can be performed (conversion time: approx. 7.5

s at fCLK = 16 MHz).

A/D conversion can be started in either of the following two modes:

• Hardware start: Conversion is started by trigger input (INTP5).

• Software start: Conversion is started by setting a bit of the A/D converter mode register (ADM).

After started, the A/D converter operates in the following modes:

• Scan mode: Two or more analog inputs are sequentially selected, and data to be converted are obtained from all the input pins.

• Select mode: Only one analog input pin is used to continuously obtain converted values.

These operation modes and whether starting or stopping the A/D converter are specified by the ADM. When the result of conversion is transferred to the ADCR, interrupt request INTAD is generated. By using this request

and macro service, the converted values can be successively transferred to the memory.

Figure 7-7. Block Diagram of A/D Converter

Page 34

PD784031Y

7.7 D/A Converter

Two circuits of digital-to-analog (D/A) converters are provided. These D/A converters are of voltage output type and

have a resolution of 8 bits.

The conversion method is of R-2R resistor ladder type. By writing a value to be output to an 8-bit D/A conversion value setting register (DACSn: n = 0 or 1), an analog value is output to the ANOn (n = 0 or 1) pin. The output voltage range is determined by the voltage applied across the AV

Because the output impedance is high, no current can be extracted from the output. If the impedance of the load is low, insert a buffer amplifier between the load and output pin.

The ANOn pin goes into a high-impedance state while the RESET signal is low. After releasing reset, DACSn is cleared to 0.

Figure 7-8. Block Diagram of D/A Converter

REF2

REF2 and AVREF3 pins.

ANOn

REF3

Selector

DACSn DACEn

Remark n = 0 or 1

Internal bus

Page 35

PD784031Y

7.8 Serial Interface

Three independent serial interface channels are provided.

Asynchronous serial interface (UART)/3-wire serial I/O (IOE) x 2 Clocked serial interface (CSI) x 1

• 3-wire serial I/O (IOE)

• 2-wire serial I/O (IOE)

C bus interface (I2C)

• I

Therefore, communication with an external system and local communication within the system can be simultaneously

executed (refer to Figure 7-9).

Figure 7-9. Example of Serial Interface

PD6272 (EEPROM

SDA SCL

PD78062Y (slave)

)

PD4711A

RS-232-C

driver/receiver

PD784031Y (master)

[UART]

RxD TxD

Port

(a) UART + I

SDA

SCL

PD4711A

RS-232-C

driver/receiver

PD4711A

RS-232-C

driver/receiver

[UART]

RxD2 TxD2

Port

(b) UART + 3-wire serial I/O + 2-wire serial I/O

PD784031Y (master)

[3-wire serial I/O]

SI1

Note

Port

SCL

Note

Port

[2-wire serial I/O]

[UART]

RxD TxD

Port

SO1

SCK1

INTPm

SDA

INTPn

SDA SCL

PD75108 (slave)

SI SO SCK Port INT

PD78014 (slave)

SB0 SCK0 Port INT

LCD

Note Handshake line

Page 36

PD784031Y

7.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)

Two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial I/O mode are provided.

(1) Asynchronous serial interface mode

In this mode, data of 1 byte following the start bit is transferred or received. Because an on-chip baud rate generator is provided, a wide range of baud rates can be set. Moreover, the clock input to the ASCK pin can be divided to define a baud rate. When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can be also obtained.

Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode

Internal bus

Receive buffer RXB, RXB2

D, RXD2

D, TXD2

Baud rate generator

ASCK, ASCK2

Remark f

XX: oscillation frequency or external clock input

n = 0 through 11 m = 16 through 30

Selector

1/2

n + 1

Receive shift

Receive control

parity check

1/2m

INTSR, INTSR2

INTSER, INTSER2

Transmit shift

Transmit control

parity append

TXS, TXS2

INTST, INTST2

Page 37

PD784031Y

(2) 3-wire serial I/O mode

In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. This mode is used to communicate with a device having the conventional clocked serial interface. Basically, communication is established by using three lines: one serial clock (SCK) and two serial data (SI and SO) lines. Generally, to check the communication status, a handshake line is necessary.

Figure 7-11. Block Diagram in 3-wire Serial I/O Mode

Internal bus

Direction control circuit

SIO1, SIO2

SI1, SI2

Shift register Output latch

SO1, SO2

SCK1, SCK2

Remark f

Serial clock counter

Serial clock

control circuit

XX: oscillation frequency or external clock input

n = 0 through 11 m = 1 or 16 through 30

Interrupt signal

generation circuit

1/m 1/2

Selector

INTCSI1, INTCSI2

n + 1

fXX/2

Page 38

PD784031Y

7.8.2 Clocked serial interface (CSI)

In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in synchronization with this clock.

Figure 7-12. Block Diagram of Clocked Serial Interface

Internal bus

SI0

SO0/SDA

(in 2-wire or I

SCK0/SCL

N-ch open drain output

C bus mode)

Selector

Direction

control

Shift register

Start condition

detection circuit

Stop condition

detection circuit

Serial clock

Slave address

Acknowledge

counter

Match signal

Set Reset

Output latch

Interrupt signal

generation

circuit

Acknowledge

detection

control

Wake-up

control circuit

INTSPC

INTCSI

Remark f

Serial clock

control circuit

N-ch open drain output

(in 2-wire or I

XX: oscillation frequency or external clock input

C bus mode)

CLS0 CLS1

Selector

Timer 3 output

/16

Selector

Prescaler

Page 39

PD784031Y

(1) 3-wire serial I/O mode

This mode is to communicate with devices having the conventional clocked serial interface. Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial data (SI0 and SO0) lines. Generally, a handshake line is necessary to check the communication status.

(2) 2-wire serial I/O mode

This mode is to transfer 8-bit data by using two lines: serial clock (SCL) and serial data bus (SDA). Generally, a handshake line is necessary to check the communication status.

C (Inter IC) bus mode

(3) I

This mode is to communicate with devices conforming to the I This mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (SCL) and serial data bus (SDA). During transfer, a “start condition”, “data”, and “stop condition” can be output onto the serial data bus. During reception, these data can be automatically detected by hardware.

C bus format.

7.9 Edge Detection Function

The interrupt input pins (NMI and INTP0 through INTP5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input signal, they have a function to detect an edge. Moreover, a noise reduction circuit is also provided to prevent erroneous detection due to noise.

Pin Name Detectable Edge Noise Reduction NMI Either of rising or falling edge By analog delay INTP0 to INTP3 Either or both of rising and falling edges By clock sampling INTP4, INTP5 By analog delay

Note INTP0 can select a sampling clock.

Note

Page 40

PD784031Y

7.10 Watchdog Timer

A watchdog timer is provided to detect a hang up of the CPU. This watchdog timer generates a non-maskable interrupt unless it is cleared by software within a specified interval time. Once enabled to operate, the watchdog timer cannot be stopped by software. Whether the interrupt by the watchdog timer or the interrupt input from the NMI pin takes precedence can be specified.

Figure 7-13. Block Diagram of Watchdog Timer

CLK

Clear signal

Timer

CLK

Selector

INTWDT

Page 41

PD784031Y

8. INTERRUPT FUNCTION

As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by program.

Table 8-1. Servicing of Interrupt Request

Servicing Mode Entity of Servicing Servicing Contents of PC and PSW

Vector interrupt Software Branches and executes servicing routine Saves to and restores

(servicing is arbitrary). from stack.

Context switching Automatically switches register bank, Saves to or restores from

branches and executes servicing routine fixed area in register bank. (servicing is arbitrary).

Macro service Firmware Executes data transfer between memory Retained

and I/O (servicing is fixed).

8.1 Interrupt Sources

Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 24 types of sources, execution

of the BRK instruction or BRKCS instruction, or an operand error.

The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. When the macro service function is used, however, nesting always proceeds.

The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same request, simultaneously generate (refer to Table 8-2).

Page 42

Table 8-2. Interrupt Sources

PD784031Y

Type Default Source Internal/

Priority Name Trigger External

Software – BRK instruction Instruction execution – –

BRKCS instruction Operand error If result of exclusive OR between byte of operand and

byte is not FFH when MOV STBC, #byte, MOV WDM, #byte, or LOCATION instruction is executed

Non-maskable

Maskable 0 (highest) INTP0 Detection of pin input edge External √

– NMI Detection of pin input edge External –

WDT Overflow of watchdog timer Internal

(TM1/TM1W capture trigger, TM1/TM1W event counter input)

1 INTP1 Detection of pin input edge

(TM2/TM2W capture trigger, TM2/TM2W event counter input)

2 INTP2 Detection of pin input edge

(TM2/TM2W capture trigger, TM2/TM2W event counter input)

3 INTP3 Detection of pin input edge

(TM0 capture trigger, TM0 event counter input) 4 INTC00 Generation of TM0-CR00 match signal Internal √ 5 INTC01 Generation of TM0-CR01 match signal 6 INTC10 Generation of TM1-CR10 match signal

(in 8-bit operation mode)

Generation of TM1W-CR10W match signal

(in 16-bit operation mode) 7 INTC11 Generation of TM1-CR11 match signal

(in 8-bit operation mode)

Generation of TM1W-CR11W match signal

(in 16-bit operation mode) 8 INTC20 Generation of TM2-CR20 match signal

(in 8-bit operation mode)

Generation of TM2W-CR20W match signal

(in 16-bit operation mode) 9 INTC21 Generation of TM2-CR21 match signal

(in 8-bit operation mode)

Generation of TM2W-CR21W match signal

(in 16-bit operation mode) 10 INTC30 Generation of TM3-CR30 match signal

(in 8-bit operation mode)

Generation of TM3W-CR30W match signal

(in 16-bit operation mode) 11 INTP4 Detection of pin input edge External √ 12 INTP5 Detection of pin input edge 13 INTAD End of A/D conversion (transfer of ADCR) Internal √ 14 INTSER Occurrence of ASI0 reception error – 15 INTSR End of ASI0 reception or CSI1 transfer √

INTCSI1 16 INTST End of ASI0 transfer 17 INTCSI End of CSI1 transfer 18 INTSER2 Occurrence of ASI2 reception error – 19 INTSR2 End of ASI2 reception or CSI2 transfer √

INTCSI2 20 INTST2 End of ASI2 transfer

21 (lowest) INTSPC I2C bus stop condition interrupt

Macro Service

Remark ASI: asynchronous serial interface

CSI: clocked serial interface

Page 43

PD784031Y

8.2 Vectored Interrupt

Execution branches to a servicing routing by using the memory contents of a vector table address corresponding to

the interrupt source as the address of the branch destination.

So that the CPU performs interrupt servicing, the following operations are performed:

• On branching : Saves the status of the CPU (contents of PC and PSW) to stack

• On returning : Restores the status of the CPU (contents of PC and PSW) from stack

To return to the main routine from an interrupt service routine, the RETI instruction is used. The branch destination address is in a range of 0 to FFFFH.

Table 8-3. Vector Table Address

Interrupt Source Vector Table Address BRK instruction 003EH Operand error 003CH NMI 0002H WDT 0004H INTP0 0006H INTP1 0008H INTP2 000AH INTP3 000CH INTC00 000EH INTC01 0010H INTC10 0012H INTC11 0014H INTC20 0016H INTC21 0018H INTC30 001AH INTP4 001CH INTP5 001EH INTAD 0020H INTSER 0022H INTSR 0024H INTCSI1 INTST 0026H INTCSI 0028H INTSER2 002AH INTSR2 002CH INTCSI2 INTST2 002EH INTSPC 0030H

Page 44

PD784031Y

8.3 Context Switching

When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register bank is selected by hardware. Context switching is a function that branches execution to a vector address stored in advance in the register bank, and to stack the current contents of the program counter (PC) and program status word (PSW) to the register bank.

The branch address is in a range of 0 to FFFFH.

Figure 8-1. Context Switching Operation when Interrupt Request is Generated

0000B <7> Transfer

PC19 to 16

<2> Save (bits 8 through 11 of temporary register)

Temporary register

<1> Save

PSW

PC15 to 0

<6> Exchange

<5> Save

B R5 R7

V U

D H

C R4 R6

<3> Switching of register bank

(RBS0 to RBS2 ← n)

<4> RSS ← 0 IE ←0

(0 to 7)

8.4 Macro Service

This function is to transfer data between memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers data without loading it.

Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high speeds.

CPU

Internal bus

Figure 8-2. Macro Service

Read

Memory SFR

Write

Macro service

controller

Write

Read

Page 45

8.5 Application Example of Macro Service

(1) Transfer of serial interface

Transfer data storage buffer (memory)

Data n

Data n – 1

Data 2 Data 1

Internal bus

PD784031Y

TxD

Transfer shift register

Transfer control INTST

TXS (SFR)

Each time macro service request INTST is generated, the next transfer data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS (when the transfer data storage buffer has become empty), vectored interrupt request INTST is generated.

(2) Reception of serial interface

Receive data storage buffer (memory)

Data n

Data n – 1

Data 2 Data 1

Internal bus

RXB (SFR)

INTSR

RxD

Receive buffer

Receive shift register

Reception control

Each time macro service request INTSR is generated, the receive data is transferred from RXB to memory. When data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt request INTSR is generated.

Page 46

(3) Real-time output port

INTC10 and INTC11 serve as the output triggers of the real-time output port. The macro services for these can set the following output pattern and intervals simultaneously. Therefore, INTC10 and INTC11 can control two stepping motors independently of each other. They can also be used for PWM output or to control DC motors.

PD784031Y

Output timing profile (memory)

Internal bus

Match

CR10

INTC10

Tn– 1

T2 T1

TM1

(SFR)

P00 to P03

Output pattern profile (memory)

Pn– 1

P2 P1

Internal bus

(SFR)

P0L

Output latch

Each time macro service request INTC10 is generated, the pattern and timing are transferred to the buffer register (P0L) and compare register (CR10), respectively. When the contents of the timer register 1 (TM1) coincide with those of CR10, INTC10 is generated again, and the contents of P0L are transferred to the output latch. When Tn (last byte) has transferred to CR10, vectored interrupt request INTC10 is generated.

The same applies to INTC11.

Page 47

PD784031Y

9. LOCAL BUS INTERFACE

The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory space

of 1 Mbytes (refer to Figure 9-1).

Figure 9-1. Example of Local Bus Interface

PD784031Y

A16 to A19

Decoder

REFRQ

AD0 to AD7

ASTB

A8 to A15

Latch

Pseudo SRAM

PD27C1001A

Data bus

Address bus

Gate array I/O expansion Centronics I/F, etc.

PROM

Character

generator

PD24C1000

9.1 Memory Expansion

The memory capacity can be expanded in seven steps, from 256 bytes to 1 Mbytes, by connecting an external program

memory and data memory.

Page 48

PD784031Y

9.2 Memory Space

The 1-Mbyte memory space is divided into eight spaces of logical addresses. Each space can be controlled by using

the programmable wait function and pseudo static RAM refresh function.

Figure 9-2. Memory Space

HFFFFF

512 Kbytes

H00008 HFFFF7

256 Kbytes

H00004 HFFFF3

128 Kbytes

H00002 HFFFF1

64 Kbytes

H00001 HFFFF0

16 Kbytes

H000C0 HFFFB0

16 Kbytes

H00080 HFFF70

16 Kbytes

H00040 HFFF30

16 Kbytes

H00000

Page 49

PD784031Y

9.3 Programmable Wait

The memory space can be divided into eight spaces and wait states can be independently inserted in each of these spaces while the RD and WR signals are active. Even when a memory with a different access time is connected, therefore, the efficiency of the entire system does not drop.

In addition, an address wait function that extends the active period of the ASTB signal is also provided so as to have a sufficient address decode time (this function can be set to the entire space).

9.4 Pseudo Static RAM Refresh Function

The following refresh operations can be performed:

• Pulse refresh : A bus cycle that outputs a refresh pulse to the REFRQ pin at a fixed cycle is inserted. The memory spaces is divided into eight spaces, and a refresh pulse can be output from the REFRQ pin while a specified memory space is accessed. Therefore, the normal memory access is not kept to wait by the refresh cycle.

• Power-down self-refresh : The low level is output to the REFRQ pin in the standby mode to retain the contents of the pseudo static RAM.

9.5 Bus Hold Function

A bus hold function is provided to facilitate connection of a DMA controller. When a bus hold request signal (HLDRQ) is received from an external bus master, the address bus, address/data bus, and ASTB, RD, and WR pins go into a highimpedance state when the current bus cycle has been completed. This makes the bus hold acknowledge (HLDAK) signal active, and releases the bus to the external bus master.

Note that, while the bus hold function is used, the external wait function and pseudo static RAM refresh function cannot be used.

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PD784031Y

10. STANDBY FUNCTION

This function is to reduce the power dissipation of the chip, and can be used in the following modes:

• HALT mode : Stops supply of the operating clock to the CPU. This mode is used in combination with the normal operation mode for intermittent operation to reduce the average power dissipation.

• IDLE mode : Stops the entire system with the oscillation circuit continuing operation. The power dissipation in this mode is close to that in the STOP mode. However, the time required to restore the normal program operation from this mode is almost the same as that from the HALT mode.

• STOP mode: Stops the oscillator and thereby to stop all the internal operations of the chip. Consequently, the power dissipation is minimized with only leakage current flowing.

These modes are programmable. The macro service can be started from the HALT mode.

Figure 10-1. Transition of Standby Status

Macro service request

End of one processing

End of macro service

Interrupt request

RESET input

Sets HALT mode

Note 2

HALT

(standby)

Macro

service

Macro service request

End of one processing

NMI, INTP4, INTP5 input

STOP

(standby)

Waits for

oscillation

stabilization

Note 1

Sets STOP mode

RESET input

(standby)

Oscillation stabilization

time expires

Sets IDLE mode

RESET input

NMI, INTP4, INTP5 input

IDLE

Program

operation

Note 1

Interrupt request of masked interrupt

Notes 1. When INTP4 and INTP5 are not masked

2. Only interrupt requests that are not masked

Remark Only the externally input NMI is valid. The watchdog timer cannot be used to release the standby mode (STOP/

IDLE mode).

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PD784031Y

11. RESET FUNCTION

When the low level is input to the RESET pin, the internal hardware is initialized (reset status). When the RESET pin goes high, the following data are set to the program counter (PC).

• Lower 8 bits of PC : contents of address 0000H

• Middle 8 bits of PC : contents of address 0001H

• Higher 4 bits of PC : 0

Program execution is started from a branch destination address which is the contents of the PC. Therefore, the system

can be reset and started from any address.

Set the contents of each register by program as necessary. The RESET input circuit has a noise reduction circuit to prevent malfunctioning due to noise. This noise reduction circuit

is a sampling circuit by analog delay.

Figure 11-1. Accepting Reset Signal

Executes instruction at reset start address

RESET

(input)

Internal reset signal

Delay

Reset starts Reset ends

Delay Initialize PC

Assert the RESET signal active until the oscillation stabilization time (approx. 40 ms) elapses to execute a power-ON

reset operation.

Figure 11-2. Power-ON Reset Operation

Oscillation stabilization time Delay Initialize PC

Executes instruction at reset start address

RESET

(input)

Internal reset signal

Reset ends

Page 52

12. INSTRUCTION SET

(1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r)

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHIKL, CHKLA

Table 12-1. Instruction List by 8-bit Addressing

PD784031Y

Second Operand #byte A r saddr sfr !addr16 mem r3 [WHL+] n

None

Note 2

r' saddr' !!addr24 [saddrp] PSWL [WHL–]

First Operand A (MOV) (MOV) MOV

Note 1

ADD

(XCH) XCH

Note 1

(ADD)

Note 1

(MOV) (XCH) (ADD)

Note 6

MOV (MOV) MOV MOV (MOV)

Note 6

(XCH) (XCH) XCH (XCH)

Note 1,6

(ADD)

Note 1

ADD

r MOV (MOV) MOV MOV MOV MOV ROR

Note 1

ADD

(XCH) XCH XCH XCH XCH DIVUW

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

ADD

Note 1

[%saddrg]

Note 1

ADD

PSWH

(ADD)

Note 1

Note 3

MULU

INC

DEC

saddr MOV

Note 1

ADD

(MOV) (ADD)

Note 6

MOV MOV INC

Note 1

ADD

Note 1

XCH DEC

Note 1

ADD

DBNZ

sfr MOV MOV MOV PUSH

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

POP

CHKL

CHKLA

!addr16 MOV (MOV) MOV !!addr24 ADD

Note 1

mem MOV [saddrp] ADD

Note 1

[%saddrg] mem3 ROR4

ROL4

r3 MOV MOV PSWL PSWH

B, C DBNZ STBC, WDM MOV [TDE+] (MOV)

[TDE–]

(ADD) MOVM

Note 1

Note 4

MOVBK

Note 5

Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR.

4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of MOVM.

5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of MOVBK.

6. The code length of some instructions having saddr2 as saddr in this combination is short.

Page 53

PD784031Y

(2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as rp)

MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

Table 12-2. Instruction List by 16-bit Addressing

Second Operand #word AX rp saddrp sfrp !addr16 mem [WHL+] byte n None

Note 2

rp' saddrp' !!addr24 [saddrp]

First Operand

AX (MOVW) (MOVW) (MOVW)

Note 1

ADDW

(XCHW) (XCHW)

Note 1

(ADD)

(ADDW)

Note 1

(MOVW) (XCHW)

Note 1,3

(ADDW)

Note 3

MOVW (MOVW) MOVW (MOVW)

Note 3

(XCHW) XCHW XCHW (XCHW)

Note 1

(ADDW)

rp MOVW (MOVW) MOVW MOVW MOVW MOVW SHRW

Note 1

ADDW

saddrp MOVW

ADDW

(XCHW) XCHW XCHW XCHW SHLW INCW

Note 1

(ADDW)

(MOVW)

(ADDW)

Note 1

Note 3

Note 1

ADDW

Note 1

ADDW

Note 1

ADDW

Note 1

MOVW MOVW INCW

Note 1

ADDW

XCHW DECW

Note 1

ADDW

[%saddrg]

MULW

DECW

sfrp MOVW MOVW MOVW PUSH

Note 1

ADDW

!addr16 MOVW (MOVW) MOVW

(ADDW)

Note 1

ADDW

Note 1

POP

MOVTBLW

!!addr24

mem MOVW [saddrp] [%saddrg]

Note 4

PSW PUSH

SP ADDWG

SUBWG

post PUSH

PUSHU

POPU

[TDE+] (MOVW) SACW

byte MACW

MACSW

Notes 1. The operands of SUBW and CMPW are the same as that of ADDW.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The code length of some instructions having saddrp2 as saddrp in this combination is short.

4. The operands of MULUW and DIVUX are the same as that of MULW.

POP

Page 54

PD784031Y

(3) 24-bit instructions (The instructions in parentheses are combinations realized by describing WHL as rg)

MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP

Table 12-3. Instruction List by 24-bit Addressing

Second Operand #imm24 WHL rg saddrg !!addr24 mem1

rg'

First Operand

WHL (MOVG) (MOVG) (MOVG) (MOVG) (MOVG) MOVG MOVG MOVG

(ADDG) (ADDG) (ADDG) ADDG (SUBG) (SUBG) (SUBG) SUBG

rg MOVG (MOVG) MOVG MOVG MOVG INCG

ADDG (ADDG) ADDG DECG

SUBG (SUBG) SUBG PUSH

saddrg (MOVG) MOVG

!!addr24 (MOVG) MOVG

mem1 MOVG

[%saddrg] MOVG

SP MOVG MOVG INCG

[%saddrg]

SP None

POP

DECG

Note Either the second operand is not used, or the second operand is not an operand address.

Note

Page 55

(4) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET

Table 12-4. Bit Manipulation Instructions

PD784031Y

Second Operand CY saddr.bit sfr.bit /saddr.bit /sfr. bit None

A.bit X.bit /A.bit /X.bit PSWL.bit PSWH.bit /PSWL.bit /PSWH.bit mem2.bit /mem2.bit

First Operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit

CY MOV1 AND1 NOT1

AND1 OR1 SET1 OR1 CLR1 XOR1

saddr.bit MOV1 NOT1 sfr.bit SET1 A.bit CLR1 X.bit BF PSWL.bit BT PSWH.bit BTCLR mem2.bit BFSET !addr16.bit !!addr24.bit

Note

Note Either the second operand is not used, or the second operand is not an

operand address.

Page 56

(5) Call and return/branch instructions

CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ

Table 12-5. Call and Return/Branch Instructions

PD784031Y

Operand of Instruction $addr20 Address

Basic instruction BC

Compound instruction BF

$!addr20

Note

BR BR BR BR BR BR BR BR RET

BT BTCLR BFSET DBNZ

!addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None

CALL CALL CALL CALL CALL CALL CALL CALLF CALLF BRKCS BRK

RETCS RETI RETCSB

RETB

Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH,

and BH are the same as BC.

(6) Other instructions

ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS

Page 57

PD784031Y

13. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C)

Parameter Symbol Test Conditions Ratings Unit

Supply voltage VDD –0.5 to +7.0 V

AVDD AVSS to VDD + 0.5 V

AVSS –0.5 to +0.5 V Input voltage VI –0.5 to VDD + 0.5 V Output voltage VO –0.5 to VDD + 0.5 V Output current low-level IOL 1 pin 15 mA

Total of output pins 100 mA

Output current high-level IOH 1 pin –10 mA

Total of output pins –100 mA

Reference input voltage AVREF1 –0.5 to VDD + 0.3 V to A/D converter

Reference input voltage AVREF2 –0.5 to VDD + 0.3 V to D/A converter

Operating ambient TA –40 to +85 °C temperature

Storage temperature Tstg –65 to +150 °C

AVREF3 –0.5 to VDD + 0.3 V

Caution The product quality may be damaged even if a value of only one of the above parameters exceeds the

absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That is, the absolute maximum rating is a rating value which may cause a product to be damaged physically. The absolute maximum rating values must therefore be observed in using the product.

Page 58

Operating Condition

• Operating ambient temperature (TA) : –40 to +85°C

• Rise, fall time (t

r, tf) (unspecified pins) : 0 to 200

• Supply voltage and clock cycle time : refer to Figure 13-1

Figure 13-1. Supply Voltage and Clock Cycle Time

10000

4000

[ns]

1000

CYK

125 100

Clock Cycle Time t

62.5

Guaranteed Operation Range

PD784031Y

01234567

Supply Voltage [V]

Capacitance (TA = 25°C, VDD = VSS = 0 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacitance CI f = 1 MHz 10 pF Output capacitance CO I/O capacitance CIO

Unmeasured pins returned to 0 V.

10 pF 10 pF

Page 59

PD784031Y

Oscillator Characteristics (TA = –40 to +85°C, VDD = +4.5 to 5.5 V, VSS = 0 V)

Resonator Recommended Circuit Parameter MIN. MAX. Unit

Ceramic resonator or Oscillation frequency (fXX) 4 32 MHz crystal resonator

SS1

X1 X2

C2C1

External clock X1 input frequency (fX) 4 32 MHz

X1 X2

HCMOS inverter

X1 input rise, fall time (tXR, tXF) 0 10 ns

X1 input high-/low-level width 10 125 ns (tWXH, tWXL)

Caution When using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out

as follows to avoid an adverse effect from wiring capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.

• Wiring should not be placed close to a varying high current.

• The potential of the oscillator capacitor ground should be the same as V

SS1. Do not ground it to

the ground pattern in which a high current flows.

• Do not fetch a signal from the oscillator.

Page 60

PD784031Y

Oscillator Characteristics (TA = –40 to +85°C, VDD = +2.7 to 5.5 V, VSS = 0 V)

Resonator Recommended Circuit Parameter MIN. MAX. Unit

Ceramic resonator or Oscillation frequency (fXX) 4 16 MHz crystal resonator

SS1

X1 X2

C2C1

External clock X1 input frequency (fX) 4 16 MHz

X1 X2

HCMOS inverter

X1 input rise, fall time (tXR, tXF) 0 10 ns

X1 input high-/low-level width 10 125 ns (tWXH, tWXL)

Caution When using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out

as follows to avoid an adverse effect from wiring capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.

• Wiring should not be placed close to a varying high current.

• The potential of the oscillator capacitor ground should be the same as V

SS1. Do not ground it to

the ground pattern in which a high current flows.

• Do not fetch a signal from the oscillator.

Page 61

PD784031Y

DC Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Input voltage low-level VIL1 Except for pins shown in –0.3 0.3VDD V

Notes 1, 2, 3, 4, 6

VIL2 Pins shown in Notes 1, 2, 3, 4, 6 –0.3 0.2VDD V VIL3 VDD = +5.0 V ± 10 % –0.3 +0.8 V

Pins shown in Notes 2, 3, 4

Input voltage high-level V IH1 Except for pins shown in Notes 1, 6 0.7VDD VDD + 0.3 V

VIH2 Pins shown in Notes 1, 6 0.8VDD VDD + 0.3 V VIH3 VDD = +5.0 V ± 10 % 2.2 VDD + 0.3 V

Pins shown in Notes 2, 3, 4

Output voltage low-level VOL1 IOL = 2 mA 0.4 V

Except for pins shown in Note 6

VOL2 IOL = 3 mA 0.4 V

Pins shown in Note 6 IOL = 6 mA 0.6 V

Pins shown in Note 6

VOL3 VDD = +5.0 V ± 10 % 1.0 V

IOL = 8 mA Pins shown in Notes 2, 5

Output voltage high-level VOH1 IOH = –2 mA VDD – 1.0 V

VOH2 VDD = +5.0 V ± 10 % VDD – 1.4 V

IOH = –5 mA Pins shown in Note 4

X1 input current low-level IIL EXTC = 0 –30

0 V ≤ VI ≤ VIL2

X1 input current high-level IIH EXTC = 0 +30

VIH2 ≤ VI ≤ VDD

Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,

P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, TEST

2. AD0 to AD7, A8 to A15

3. P60/A16 to P63/A19, RD, WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK

4. P00 to P07

5. P10 to P17

6. P32/SCK0/SCL, P33/SO0/SDA

Page 62

PD784031Y

DC Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Input leakage current ILI 0 V ≤ VI ≤ VDD ±10

Except for X1 pin when EXTC = 0 Output leakage current ILO 0 V ≤ VO ≤ VDD ±10 VDD supply current IDD1 Operating fXX = 32 MHz 25 45 mA

mode VDD = +5.0 V ± 10 %

fXX = 16 MHz 12 25 mA VDD = +2.7 to 3.3 V

IDD2 HALT mode fXX = 32 MHz 13 26 mA

VDD = +5.0 V ± 10 % fXX = 16 MHz 8 12 mA

VDD = +2.7 to 3.3 V

IDD3 IDLE mode fXX = 32 MHz 12 mA

(EXTC = 0) VDD = +5.0 V ± 10 %

fXX = 16 MHz 8 mA VDD = +2.7 to 3.3 V

Pull-up resistor RL VI = 0 V 15 80 kΩ

Page 63

PD784031Y

AC Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)

(1) Read/write operation (1/2)

Parameter Symbol Test Conditions MIN. MAX. Unit

Address setup time tSAST VDD = +5.0 V ± 10 %

ASTB high-level width tWSTH VDD = +5.0 V ± 10 %

Address hold time (from ASTB↓)tHSTLA VDD = +5.0 V ± 10 % 0.5T – 24 ns

Address hold time (from RD↑)tHRA 0.5T – 14 ns Address → RD↓ delay time tDAR VDD = +5.0 V ± 10 % (1 + a) T – 9 ns

Address float time (from RD↓)tFRA 0ns Address → data input time tDAID VDD = +5.0 V ± 10 %

ASTB↓ → data input time tDSTID VDD = +5.0 V ± 10 % (2 + n) T – 40 ns

RD↓ → data input time tDRID VDD = +5.0 V ± 10 % (1.5 + n) T – 50 ns

ASTB↓ → RD↓ delay time tDSTR 0.5T – 9 ns Data hold time (from RD↑)tHRID 0ns RD↑ → address active time tDRA After program VDD = +5.0 V ± 10 % 0.5T – 8 ns

read After data VDD = +5.0 V ± 10 % 1.5T – 8 ns

read

RD↑ → ASTB↑ delay time tDRST 0.5T – 17 ns RD low-level width tWRL VDD = +5.0 V ± 10 %

Address hold time (from WR↑)tHWA 0.5T – 14 ns Address → WR↓ delay time tDAW VDD = +5.0 V ± 10 % (1 + a) T – 5 ns

ASTB↓ → data output delay time

WR↓ → data output delay time tDWOD 0.5T – 11 ns ASTB↓ → WR↓

output delay time

tDSTOD VDD = +5.0 V ± 10 % 0.5T + 19 ns

tDSTW 0.5T – 9 ns

(0.5 + a) T – 15 (0.5 + a) T – 31 (0.5 + a) T – 17 (0.5 + a) T – 40

0.5T – 34 ns

(1 + a) T – 15 ns

(2.5 + a + n) T – 37 (2.5 + a + n) T – 52

(2 + n) T – 60 ns

(1.5 + n) T – 70 ns

0.5T – 12 ns

1.5T – 12 ns

(1.5 + n) T – 30 (1.5 + n) T – 40

(1 + a) T – 15 ns

0.5T + 35 ns

ns ns ns ns

ns ns

Remark T: TCYK (system clock cycle time)

a : 1 in address wait, 0 in the other conditions n : the number of wait (n ≥ 0)

Page 64

PD784031Y

(1) Read/write operation (2/2)

Parameter Symbol Test Conditions MIN. MAX. Unit

Data setup time (to WR↑)tSODW VDD = +5.0 V ± 10 %

Data hold time (from WR↑)

WR↑ → ASTB↑ delay time tDWST 0.5T – 12 ns WR low-level width tWWL VDD = +5.0 V ± 10 %

Note

tHWOD VDD = +5.0 V ± 10 % 0.5T – 5 ns

(1.5 + n) T – 30 (1.5 + n) T – 40

0.5T – 25 ns

(1.5 + n) T – 30 (1.5 + n) T – 40

Note The data hold time includes the time to hold VOH1 and VOL1 in the load condition of CL = 50 pF, RL = 4.7 kΩ.

ns ns

Remark T: T

CYK (system clock cycle time)

n : the number of wait (n ≥ 0)

(2) Bus hold timing

Parameter Symbol Test Conditions MIN. MAX. Unit HLDRQ↑ → float delay time tFHQC HLDRQ↑ → HLDAK↑ tDHQHHAH VDD = +5.0 V ± 10 %

delay time Float → HLDAK↑ delay time tDCFHA 1T + 30 ns

HLDRQ↓ → HLDAK↓ tDHQLHAL VDD = +5.0 V ± 10 % 2T + 40 ns delay time

HLDAK↓ → active delay time tDHAC VDD = +5.0 V ± 10 % 1T – 20 ns

1T – 30 ns

(6 + a + n) T + 50 (7 + a + n) T + 30 (7 + a + n) T + 40

2T + 60 ns

Remark T: TCYK (system clock cycle time)

a : 1 in address wait, 0 in the other conditions n : the number of wait (n ≥ 0)

ns ns ns

Page 65

PD784031Y

(3) External wait timing

Parameter Symbol Test Conditions MIN. MAX. Unit

Address → WAIT↓ input time tDAWT VDD = +5.0 V ± 10 % (2 + a) T – 40 ns

(2 + a) T – 60 ns

ASTB↓ → WAIT↓ input time tDSTWT VDD = +5.0 V ± 10 % 1.5T – 40 ns

1.5T – 60 ns

ASTB↓ → WAIT hold time tHSTWTH VDD = +5.0 V ± 10 % (0.5 + n) T + 5 ns

(0.5 + n) T + 10 ns

ASTB↓ → WAIT↑ delay time tDSTWTH VDD = +5.0 V ± 10 % (1.5 + n) T – 40 ns

(1.5 + n) T – 60 ns

RD↓ → WAIT↓ input time tDRWTL VDD = +5.0 V ± 10 % T – 50 ns

T – 70 ns

RD↓ → WAIT↓ hold time tHRWT VDD = +5.0 V ± 10 % nT + 5 ns

nT + 10 ns

RD↓ → WAIT↑ delay time tDRWTH VDD = +5.0 V ± 10 % (1 + n) T – 40 ns

(1 + n) T – 60 ns

WAIT↑ → data input time tDWTID VDD = +5.0 V ± 10 % 0.5T – 5 ns

0.5T – 10 ns WAIT↑ → WR↑ delay time tDWTW 0.5T ns WAIT↑ → RD↑ delay time tDWTR 0.5T ns WR↓ → WAIT↓ input time tDWWTL VDD = +5.0 V ± 10 % T – 50 ns

T – 75 ns

WR↓ → WAIT hold time tHWWT VDD = +5.0 V ± 10 % nT + 5 ns

nT + 10 ns

WR↓ → WAIT↑ delay time tDWWTH VDD = +5.0 V ± 10 % (1 + n) T – 40 ns

(1 + n) T – 70 ns

Remark T: TCYK (system clock cycle time)

a : 1 in address wait, 0 in the other conditions n : the number of wait (n ≥ 0)

(4) Refresh timing

Parameter Symbol Test Conditions MIN. MAX. Unit Random read/write cycle time tRC 3T ns REFRQ low-level pulse width tWRFQL VDD = +5.0 V ± 10 % 1.5T – 25 ns

1.5T – 30 ns ASTB↓ → REFRQ delay time tDSTRFQ 0.5T – 9 ns RD↑ → REFRQ delay time tDRRFQ 1.5T – 9 ns WR↑ → REFRQ delay time tDWRFQ 1.5T – 9 ns REFRQ↑ → ASTB delay time tDRFQST 0.5T – 15 ns REFRQ high-level pulse width tWRFQH VDD = +5.0 V ± 10 % 1.5T – 25 ns

1.5T – 30 ns

Remark T: TCYK (system clock cycle time)

Page 66

PD784031Y

Serial Operation (TA = –40 to +85°C, VDD = +2.7 to 5.5 V, AVSS = VSS = 0 V)

(1) CSI

Parameter Symbol Test Conditions MIN. MAX. Unit

Serial clock cycle time (SCK0) tCYSK0 Input External clock 10/fXX + 380 ns

when SCK0, SO0 are CMOS input/output

Output T

Serial clock low-level width tWSKL0 Input External clock 5/fXX + 150 ns (SCK0) when SCK0, SO0 are CMOS

input/output

Output 0.5T – 40

Serial clock high-level width tWSKH0 Input External clock 5/fXX + 150 ns (SCK0) when SCK0, SO0 are CMOS

input/output

Output 0.5T – 40 SI0 setup time (to SCK0↑)tSSSK0 40 ns SI0 hold time (from SCK0↑)tHSSK0 5/fXX + 40 ns SO0 output delay time tDSBSK1 CMOS push-pull output 0 5/fXX + 150 ns

(from SCK0↓) (3-wire serial I/O mode)

tDSBSK2 Open drain output 0 5/fXX + 400 ns

(2-wire serial I/O mode), RL = 1 kΩ

Remarks 1. The values shown in the table above are those in the condition of CL = 100 pF.

2. T : serial clock cycle set by the software. The minimum value is 16/f

XX.

3. fXX : oscillation frequency

(2) I

Parameter Symbol Standard Mode I2C Bus High-speed Mode I2C Bus Unit

fXX = 4 to 32 MHz fXX = 8 to 32 MHz

MIN. MAX. MIN. MAX. SCL clock frequency fSCL 0 100 0 400 kHz Low status hold time of SCL tLOW 4.7 1.3

clock High status hold time of SCL tHIGH 4.0 0.6

clock Data hold time tHD ; DAT 300 300 900 ns Data setup time tSU ; DAT 250 100 ns SDA, SCL signal rise time tR 1000 20 + 0.1Cb 300 ns SDA, SCL signal fall time tF 300 20 + 0.1Cb 300 ns Load capacitance of each bus line

Cb 400 400 pF

Page 67

PD784031Y

(3) IOE1, IOE2

Parameter Symbol Test Conditions MIN. MAX. Unit Serial clock cycle time tCYSK1 Input VDD = +5.0 V ± 10 % 250 ns (SCK1, SCK2) 500 ns

Output Internal 16 frequency division T ns Serial clock low-level width tWSKL1 Input VDD = +5.0 V ± 10 % 85 ns (SCK1, SCK2) 210 ns

Output Internal 16 frequency division 0.5T – 40 ns Serial clock high-level width tWSKH1 Input VDD = +5.0 V ± 10 % 85 ns (SCK1, SCK2) 210 ns

Output Internal 16 frequency division 0.5T – 40 ns SI1, SI2 setup time tSSSK1 40 ns

(to SCK1, SCK2↑) SI1, SI2 hold time tHSSK1 40 ns

(from SCK1, SCK2↑) SO1, SO2 output delay time tDSOSK 050ns

(from SCK1, SCK2↓) SO1, SO2 output hold time tHSOSK When transferring data 0.5tCYSK1 – 40 ns

(from SCK1, SCK2↑)

Remarks 1. The values shown in the table above are those in the condition of CL = 100 pF.

2. T: serial clock cycle set by the software. The minimum value is 16/fXX.

(4) UART, UART2

Parameter Symbol Test Conditions MIN. MAX. Unit

ASCK clock input cycle time tCYASK VDD = +5.0 V ± 10 % 125 ns

250 ns

ASCK clock low-level width tWASKL VDD = +5.0 V ± 10 % 52.5 ns

85 ns

ASCK clock high-level width tWASKH VDD = +5.0 V ± 10 % 52.5 ns

85 ns

Page 68

PD784031Y

Other Operations

Parameter Symbol Test Conditions MIN. MAX. Unit NMI low-level width tWNIL 10 NMI high-level width tWNIH 10 INTP0 low-level width tWIT0L 3tCYSMP + 10 ns INTP0 high-level width tWIT0H 3tCYSMP + 10 ns INTP1 to INTP3, CI low-level width INTP1 to INTP3, CI high-level width INTP4, INTP5 low-level width tWIT2L 10 INTP4, INTP5 high-level width tWIT2H 10 RESET low-level width tWRSL 10 RESET high-level width tWRSH 10

Remark tCYSMP : sampling clock set by the software

tCYCPU : CPU operation clock set by the software

tWIT1L 3tCYCPU + 10 ns tWIT1H 3tCYCPU + 10 ns

A/D Converter Characteristics

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Resolution 8 bit Total error Linearity error Quantization error ±1/2 LSB Conversion time tCONV FR = 1 120 tCYK

Sampling time tSAMP FR = 1 24 tCYK

Analog input voltage VIAN –0.3 Analog input impedance RAN 1000 MΩ AVREF1 current AIREF1 0.5 1.5 mA AVDD supply current AIDD1 fXX = 32 MHz, CS = 1 2.0 5.0 mA

Note

(TA = –40 to +85°C, VDD = AVDD = AVREF1 = +2.7 to 5.5 V, VSS = AVSS = 0 V)

1.0 %

0.8 %

FR = 0 180 tCYK

FR = 0 36 tCYK

AVREF1 + 0.3

AIDD2 STOP mode, CS = 0 1.0 20

Note Quantization error is not included. This is expressed in proportion to the full-scale value.

Remark t

CYK: system clock cycle time

Page 69

PD784031Y

D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Resolution 8 bit Total error Load VDD = AVDD = AVREF2 0.6 %

condition = +2.7 to 5.5 V 4 MΩ, 30 pF AVREF3 = 0 V

VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD

Load VDD = AVDD = AVREF2 0.8 % condition = +2.7 to 5.5 V 2 MΩ, 30 pF AVREF3 = 0 V

VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD

AVREF3 = 0.25VDD Settling time Load condition 2 MΩ, 30 pF 10 Output resistance RO DACS0, 1 = 55 H 10 kΩ Analog reference voltage AVREF2 0.75VDD VDD V

AVREF3 0 0.25VDD V AVREF2, AVREF3 resistance value RAIREF DACS0, 1 = 55 H 4 8 kΩ Reference supply input current AIREF2 05mA

AIREF3 –5 0 mA

0.8 %

1.0 %

Page 70

PD784031Y

Data Retention Characteristics (TA = –40 to +85°C)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Data retention voltage VDDDR STOP mode 2.5 5.5 V Data retention current IDDDR VDDDR = +2.7 to 5.5 V 10 50

VDDDR = +2.5 V 2 10 VDD rise time tRVD 200 VDD fall time tFVD 200 VDD hold time tHVD 0ms

(from setting STOP mode) STOP release signal input time tDREL 0ms Oscillation stabilization wait time tWAIT Crystal resonator 30 ms

Ceramic resonator 5 ms Input voltage low-level VIL Specified pins Input voltage high-level VIH 0.9VDDDR VDDDR V

Note

0 0.1VDDDR V

Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5,

P27/SI0, P32/SCK0/SCL, and P33/SO0/SDA pins

AC Timing Test Point

–1 V

0.45 V

0.8VDD or 2.2 V

0.8 V

0.8VDD or 2.2 V

Test Points

0.8 V

Page 71

Timing Waveform

(1) Read operation

ASTB

A8 to A19

AD0 to AD7

WSTH

SAST

DAR

DSTR

HSTLA

DAID

DSTID

FRA

DRID

DRST

HRA

DRA

HRID

PD784031Y

(2) Write operation

ASTB

A8 to A19

AD0 to AD7

WSTH

SAST

DAW

DSTW

HSTLA

DSTOD

DWOD

WRL

SODW

DWST

HWA

HWOD

WWL

Page 72

Hold Timing

ADTB, A8 to A19,

AD0 to AD7, RD, WR

tFHQC tDCFHA

HLDRQ

HLDAK

External WAIT Signal Input Timing

(1) Read operation

ASTB

DSTWT

tDHQHHAH

DSTWTH

HSTWTH

tDHQLHAL

tDHAC

PD784031Y

A8 to A19

AD0 to AD7

WAIT

(2) Write operation

ASTB

A8 to A19

AD0 to AD7

DAWT

DSTWT

DRWTL

DSTWTH

HSTWTH

HRWT

DRWTH

DWTID

DWTR

WAIT

DAWT

DWWTL

HWWT

DWWTH

DWTW

Page 73

Refresh Timing Waveform

(1) Random read/write cycle

ASTB

(2) When refresh memory access is simultaneous with read, write

ASTB

PD784031Y

RD, WR

REFRQ

(3) Refresh after read

ASTB

REFRQ

(4) Refresh after write

DSTRFQ

WRFQL

DRRFQ

WRFQH

DRFQST

WRFQL

DRFQST

ASTB

REFRQ

DWRFQ

WRFQL

DRFQST

Page 74

Serial Operation

(1) CSI

SCK

WSKL0

CYSK0

WSKH0

SSSK0tHSSK0

PD784031Y

DSBSK1

SO Output Data

(2) I

HIGH

LOW

SCL

SDA

tHD ; DAT tSU ; DAT

(3) IOE1, IOE2

WSKL1

SCK

CYSK1

WSKH1

HSBSK1

Input Data

SSSK1tHSSK1

(4) UART, UART2

ASCK2

ASCK,

WASKH

CYASK

DSOSK

HSOSK

Output Data

WASKL

Input Data

Page 75

Interrupt Input Timing

NMI

INTP0

WNIH

WIT0H

WIT1H

WNIL

WIT0L

WIT1L

PD784031Y

INTP1 to INTP3

INTP4, INTP5

Reset Input Timing

RESET

CI,

WIT2H

WRSH

WIT2L

WRSL

Page 76

External Clock Timing

Data Retention Characteristics

STOP Mode Setting

HVD

FVD

PD784031Y

WXH

CYX

DDDR

RVD

WXL

DREL

WAIT

RESET

NMI

(release by falling edge)

NMI

(release by rising edge)

Page 77

14. PACKAGE DRAWINGS

80 PIN PLASTIC QFP (14×14)

PD784031Y

NOTE

Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.

detail of lead end

ITEM MILLIMETERS INCHES

A 17.2±0.4 0.677±0.016 B 14.0±0.2 0.551

C 14.0±0.2 0.551 D 17.2±0.4 0.677±0.016

F 0.825 0.032 G 0.825 0.032

H 0.30±0.10 0.012

I 0.13 0.005

J 0.65 (T.P.) 0.026 (T.P.)

K 1.6±0.2 0.063±0.008

L 0.8±0.2 0.031

M 0.15 0.006 N 0.10 0.004

P 2.7 0.106 Q 0.1±0.1 0.004±0.004 R5°±5° 5°±5° S 3.0 MAX. 0.119 MAX.

+0.10 –0.05

+0.009 –0.008

+0.004 –0.005

+0.009 –0.008

+0.004 –0.003

S80GC-65-3B9-4

Remark Dimensions and materials of ES products are the same as those of mass-produced products.

Page 78

80 PIN PLASTIC QFP (14×14)

PD784031Y

A B

4160

4061

detail of lead end

2180

201

NOTE

Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.

C D

ITEM MILLIMETERS INCHES

A 17.20±0.20 0.677±0.008

+0.009

B 14.00±0.20 0.551

C 14.00±0.20 0.551 D 17.20±0.20 0.677±0.008

F 0.825 0.032

G 0.825 0.032

H 0.32±0.06 0.013

I 0.13 0.005

J 0.65 (T.P.) 0.026 (T.P.)

K 1.60±0.20 0.063±0.008

L 0.80±0.20 0.031

+7° –3°

+0.03 –0.07

M 0.17 0.007

N 0.10 0.004 P 1.40±0.10 0.055±0.004

Q 0.125±0.075 0.005±0.003

R3° 3° S 1.70 MAX. 0.067 MAX.

+0.009 –0.008

–0.008 +0.009

–0.008

+0.002 –0.003

+0.009 –0.008

+0.001 –0.003

+7° –3°

P80GC-65-8BT

Remark Dimensions and materials of ES products are the same as those of mass-produced products.

Page 79

80-PIN PLASTIC TQFP (FINE PITCH) (12 × 12 mm)

A B

PD784031Y

NOTE

Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.

detail of lead end

ITEM MILLIMETERS INCHES

A 14.0±0.2 0.551

B 12.0±0.2 0.472

C 12.0±0.2 0.472

D 14.0±0.2 0.551

1.25

G 1.25

0.10

+0.05 –0.04

+0.055 –0.045

H 0.22 0.009±0.002

J 0.5 (T.P.) K 1.0±0.2 0.039

L 0.5±0.2 0.020

M 0.145 0.006±0.002 N 0.10 0.004

P 1.05 0.041 Q 0.05±0.05 R 5°±5° 5°±5°

S 1.27 MAX. 0.050 MAX.

+0.009 –0.008

0.049

0.004

0.020 (T.P.) +0.009

–0.008 +0.008

–0.009

0.002±0.002

P80GK-50-BE9-4

Remark Dimensions and materials of ES products are the same as those of mass-produced products.

Page 80

PD784031Y

15. RECOMMENDED SOLDERING CONDITIONS

This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC sales representative.

Table 15-1. Surface Mounting Type Soldering Conditions (1/2)

PD784031YGC-3B9: 80-pin plastic QFP (14 × 14 mm, thickness 2.7 mm)

(1)

Soldering Method Soldering Conditions Symbol

Infrared reflow Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above), IR35-00-3

Number of times: 3 times max.

VPS Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above), VP15-00-3

Number of times: 3 times max.

Wave soldering Solder bath temperature: 260°C max., Duration: 10 sec. max., Number of times: Once, WS60-00-1

Preliminary heat temperature: 120°C max. (Package surface temperature)

Partial heating Pin temperature: 300°C max. Duration: 3 sec. max. (per device side) —

Caution Use of more than one soldering method should be avoided (except in the case of partial heating).

(2)µPD784031YGC-8BT: 80-pin plastic QFP (14 × 14 mm, thickness 1.4 mm)

Soldering Method Soldering Conditions Symbol

Infrared reflow Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above), IR35-00-2

Number of times: Twice max.

VPS Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above), VP15-00-2

Number of times: Twice max.

Wave soldering Solder bath temperature: 260°C max., Duration: 10 sec. max., Number of times: Once, WS60-00-1

Preliminary heat temperature: 120°C max. (Package surface temperature)

Partial heating Pin temperature: 300°C max. Duration: 3 sec. max. (per device side) —

Caution Use of more than one soldering method should be avoided (except in the case of partial heating).

Page 81

PD784031Y

Table 15-1. Surface Mounting Type Soldering Conditions (2/2)

PD784031YGK-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

(3)

Soldering Method Soldering Conditions Symbol

Infrared reflow Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above), IR35-107-2

Number of times: Twice max., Time limit: 7 days required at 125°C) <precaution> Do not bake devices by packing them in non-heat resistant trays or packing materials such as magazine cases and tapes. Use heat-resistant trays.

VPS Package peak temperature: 215°C, Duration: 40 sec. (at 200°C or above), VP15-107-2

Partial heating Pin temperature: 300°C max. Duration: 3 sec. max. (per device side) —

Note

(thereafter 10 hours prebaking

Note

(thereafter 10 hours prebaking

Note For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65 % RH.

Caution Use of more than one soldering method should be avoided (except in the case of partial heating).

Page 82

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for supporting development of a system using the µPD784031Y.

Language Processor Software

RA78K4 CC78K4 CC78K4-L

PG-1500 PROM programmer PA-78P4026GC Programmer adapter connected to PG-1500

PA-78P4038GK PA-78P4026KK

PG-1500 controller

Note 1 Note 1

Note 1

PROM Writing Tool

Note 2

Assembler package common to 78K/IV Series C compiler package common to 78K/IV Series C compiler library source file common to 78K/IV Series

PG-1500 control program

PD784031Y

Debugging Tool

IE-784000-R In-circuit emulator common to 78K/IV Subseries IE-784000-R-BK Break board common to 78K/IV Series IE-784038-R-EM1 Emulation board for evaluation of

PD784038Y Subseries

IE-784000-R-EM IE-70000-98-IF-B Interface adapter when PC-9800 Series (except notebook type) is used as host machine IE-70000-98N-IF Interface adapter and cable when notebook type PC-9800 Series is used as host

machine IE-70000-PC-IF-B Interface adapter when IBM PC/ATTM is used as host machine IE-78000-R-SV3 Interface adapter and cable when EWS is used as host machine EP-78230GC-R Emulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types) common to

PD784038Y Subseries

EP-78054GK-R Emulation probe for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) common to

PD784038Y Subseries

EV-9200GC-80 Socket mounted on board of target system created for 80-pin plastic QFP (GC-3B9 and

GC-8BT types) TGK-080SDW Adapter mounted on board of target system created for 80-pin plastic TQFP (fine pitch)

(GK-BE9 type) EV-9900 Jig used to remove µPD78P4038YKK-T from EV-9200GC-80 SM78K4 ID78K4 DF784038

Note 3

Note 4

System simulator common to 78K/IV Series

Integrated debugger for IE-784000-R

Device file for µPD784038Y Subseries

Real-time OS

RX78K/IV MX78K4

Note 4

Note 2

Real-time OS for 78K/IV Series

OS for 78K/IV Series

Page 83

Notes 1. • PC-9800 Series (MS-DOSTM) based

• IBM PC/AT and compatible machine (PC DOSTM, WindowsTM, MS-DOS, IBM DOSTM) based

• HP9000 Series 700

• SPARCstationTM (SunOSTM) based

• NEWSTM (NEWS-OSTM) based

2. • PC-9800 Series (MS-DOS) based

• IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based

3. • PC-9800 Series (MS-DOS + Windows) based

• IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based

• HP9000 Series 700 (HP-UX) based

• SPARCstation (SunOS) based

4. • PC-9800 Series (MS-DOS) based

• IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based

• HP9000 Series 700 (HP-UX) based

• SPARCstation (SunOS) based

Remarks 1. RA78K4, CC78K4, SM78K4, and ID78K4 are used in combination with DF784038.

2. TGK-080SDW is manufactured by TOKYO ELETECH Corporation. Consult your local NEC sales

representative when purchasing it.

(HP-UXTM) based

PD784031Y

Page 84

APPENDIX B. RELATED DOCUMENTS

Documents Related to Device

Document Name Document No.

English Japanese

PD784031Y Data Sheet This manual U11504J

PD784035Y, 784036Y, 784037Y, 784038Y Data Sheet U10741E U10741J

PD78P4038Y Data Sheet U10742E U10742J

PD784038, 784038Y Subseries User’s Manual - Hardware U11316E U11316J

PD784038Y Subseries Special Function Register Table – U11091J 78K/IV Series User’s Manual - Instruction U10905E U10905J 78K/IV Series Instruction Table – U10594J 78K/IV Series Instruction Set – U10595J 78K/IV Series Application Note - Software Basics – U10095J

PD784031Y

Documents Related to Development Tools (User’s Manuals)

Document Name Document No.

English Japanese

RA78K4 Assembler Package Operation U11334E U11334J

Language – U11162J RA78K Series Structured Assembler Preprocessor EEU-1402 EEU-817 CC78K4 Series Operation – EEU-960

Language – EEU-961 CC78K Series Library Source File – U12322J PG-1500 PROM Programmer EEU-1335 U11940J PG-1500 Controller - PC-9800 Series (MS-DOS) Based EEU-1291 EEU-704 PG-1500 Controller - IBM PC Series (PC DOS) Based U10540E EEU-5008 IE-784000-R EEU-1534 EEU-5004 IE-784038-R-EM1 U11383E U11383J EP-78230 EEU-1515 EEU-985 EP-78054GK-R EEU-1468 EEU-932 SM78K4 System Simulator - Windows Based Reference U10093E U10093J SM78K Series External Part User Open Interface Specifications U10092E U10092J ID78K4 Integrated Debugger - Windows Based Reference U10440E U10440J ID78K4 Integrated Debugger

- HP9000 Series 700 (HP-UX) Based

Reference To be released soon U11960J

Caution The above related documents are subject to change without prior notice. Be sure to use the latest

version when starting design.

Page 85

PD784031Y

Documents Related to Embedded Software (User’s Manual)

Document Name Document No.

English Japanese

78K/IV Series Real-time OS Basics U10603E U10603J

Installation U10604E U10604J Debugger – U10364J

78K/IV Series OS MX78K4 Basics – U11779J

Datasheet UPD784031YGK-BE9, UPD784031YGC-8BT, UPD784031YGC-3B9 Datasheet (NEC)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATION FIELDS

ORDERING INFORMATION

78K/IV SERIES PRODUCT DEVELOPMENT

FUNCTIONS

3. PIN CONFIGURATION (Top View)

4. BLOCK DIAGRAM

5. PIN FUNCTION

5.1 Port Pins

5.2 Non-port Pins

5.3 Types of Pin I/O Circuits and Connections for Unused Pins

6. CPU ARCHITECTURE

6.1 Memory Space

6.2 CPU Registers

6.2.1 General-purpose registers

6.2.2 Control registers

6.2.3 Special function registers (SFRs)

7. PERIPHERAL HARDWARE FUNCTIONS

7.1 Ports

7.2 Clock Generation Circuit

7.3 Real-time Output Port

7.4 Timer/Counter

7.5 PWM Output (PWM0, PWM1)

7.6 A/D Converter

7.7 D/A Converter

7.8 Serial Interface

7.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)

7.8.2 Clocked serial interface (CSI)

7.9 Edge Detection Function

7.10 Watchdog Timer

8. INTERRUPT FUNCTION

8.1 Interrupt Sources

8.2 Vectored Interrupt

8.3 Context Switching

8.4 Macro Service

8.5 Application Example of Macro Service

9. LOCAL BUS INTERFACE

9.1 Memory Expansion

9.2 Memory Space

9.3 Programmable Wait

9.4 Pseudo Static RAM Refresh Function

9.5 Bus Hold Function

10. STANDBY FUNCTION

11. RESET FUNCTION

12. INSTRUCTION SET

13. ELECTRICAL SPECIFICATIONS

14. PACKAGE DRAWINGS

15. RECOMMENDED SOLDERING CONDITIONS

APPENDIX A. DEVELOPMENT TOOLS

APPENDIX B. RELATED DOCUMENTS