Datasheet UPD3794CY Datasheet (NEC)

Page 1
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3794
2700 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
The µPD3794 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
µ
The And it has reset feed-through level clamp circuits, a clamp pulse generation circuit, an RGB selector and voltage amplifiers. Therefore, it is suitable for 300 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
• Valid photocell : 2700 pixels × 3
• Photocell's pitch : 8 µm
• Line spacing : 32 µm (4 lines) Green line-Blue line, Blue line-Red line
7
• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10
• Resolution : 12 dot/mm A4 (210 × 297 mm) size (shorter side)
300 dpi US letter (8.5” × 11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate : 4 MHz MAX.
• Power supply : +12 V
• On-chip circuits : Reset feed-through level clamp circuits
Clamp pulse generation circuit RGB selector Voltage amplifiers
lx•hour)
ORDERING INFORMATION
Part Number Package
µ
PD3794CY CCD linear image sensor 22-pin plastic DIP (400 mil)
Document No.S13125EJ1V0DS00(1st edition) Date published December 1997 N CP(K) Printed in Japan
The information in this document is subject to change without notice.
©
1997
Page 2
BLOCK DIAGRAM
µ
PD3794
SEL1
SEL2 GND GNDV
22120
V
OUT
Clamp pulse generator
OD
19 2 11 15 14
······
D15
······
D15
······
D15
3
φ
RB
D64
CCD analog shift register
D64
CCD analog shift register
D64
CCD analog shift register
Photocell
S1
S2
(Green)
Transfer gate
Photocell
S1
S2
(Blue)
Transfer gate
Photocell
S1
S2
(Red)
Transfer gate
S2699
S2700
S2699
S2700
S2699
S2700
D65
D65
D65
D66
D66
D66
D67
D67
D67
φ
GND 1
9
φ
2
13
12
10
φ
TG1
(Green)
φ
TG2
(Blue)
φ
TG3
(Red)
2
Page 3
PIN CONFIGURATION (Top View)
Green photocell array
8 m
µ
Blue photocell array
8 m
µ
Red photocell array
8 m
µ
4 lines
(32 m)
µ
4 lines
(32 m)
µ
CCD linear image sensor 22-pin plastic DIP (400 mil)
µ
PD3794
Output signal
Ground
Reset gate clock
No connection
No connection
No connection
No connection
No connection
Shift register clock 2
Transfer gate clock 3 (for Red)
Ground
V
GND
φ
φ
TG3
GND
OUT
RB
NC
NC
NC
NC
NC
φ
1
2
1
1
1
3
4
5
6
Red
Blue
Green
7
8
9
2
10
2700
2700
2700
11
22NCSEL1
21
NC
SEL2
20
V
19
18
17
NC
16
NC
GND
15
14
φ
φ
13
12
φ
RGB select input 1
No connection
RGB select input2
Output drain voltage
OD
No connection
No connection
No connection
Ground
1
Shift register clock 1
Transfer gate clock 1
TG1
(for Green)
Transfer gate clock 2
TG2
(for Blue)
PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
3
m
µ
Channel stopper
5 m
µ
Aluminum shield
µ
8 m
3
Page 4
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
Parameter Symbol Ratings Unit
Output drain voltage VOD –0.3 to +15 V
µ
PD3794
Shift register clock voltage V Reset gate clock voltage V Transfer gate clock voltage V
φ
1, Vφ2 –0.3 to +8 V
φ
RB –0.3 to +8 V
φ
TG1
to V
φ
TG3 –0.3 to +8 V
RGB select input voltage VSEL1,VSEL2 –0.3 to +8 V Operating ambient temperature TA –25 to +60 °C Storage temperature Tstg –40 to +70 °C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)
Parameter Symbol MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level V Shift register clock low level V Reset gate clock high level V Reset gate clock low level V Transfer gate clock high level V Transfer gate clock low level V RGB select input high level VSEL1H, VSEL2H 4.5 5.0 5.5 V
φ
1H, Vφ2H 4.5 5.0 5.5 V
φ
1L, Vφ2L –0.3 0 +0.5 V
φ
RBH 4.5 5.0 5.5 V
φ
RBL –0.3 0 +0.5 V
φ
TG1H
φ
TG1L
to V
φ
TG3H 4.5 V
to V
φ
TG3L –0.3 0 +0.5 V
Note
φ
1H
Note
V
φ
1H
V
RGB select input low level VSEL1L, VSEL2L –0.3 0 +0.5 V Data rate f
Note When Transfer gate clock high level (V
φ
RB 1.0 4.0 MHz
φ
TG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H),
Image lag can increase.
4
Page 5
ELECTRICAL CHARACTERISTICS
µ
PD3794
TA = +25 °C, VOD = 12 V, data rate (f
φ
RB) = 1 MHz, storage time = 10 ms,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Saturation voltage Vsat 2.0 3.0 V Saturation exposure Red SER 0.205 lx•s
Green SEG 0.225 lx•s
Blue SEB 0.375 lx•s Photo response non-uniformity PRNU VOUT = 1.0 V 6 20 % Average dark signal ADS Light shielding 0.5 5.0 mV Dark signal non-uniformity DSNU Light shielding 4.0 10.0 mV Power consumption PW 300 600 mW Output impedance ZO 0.5 1 k Response Red RR 10.3 14.6 18.9 V/lx•s
Green RG 9.4 13.3 17.2 V/lx•s
Blue RB 5.6 8.0 10.4 V/lx•s Image lag IL VOUT = 1.0 V 5.0 10.0 % Offset level Output fall delay time
Note1
Note2
VOS 4.5 6.0 7.5 V td VOUT = 1.0 V 70 ns
Total transfer efficiency TTE VOUT = 1.0 V, 92 98 %
data rate = 4 MHz
Response peak Red 630 nm
Green 540 nm
Blue 460 nm Dynamic range DR1 Vsat /DSNU 750 times
DR2 Vsat /σ 3000 times Reset feed-through noise Random noise σ Light shielding 1.0 mV
Note1
RFTN Light shielding –1000 –300 +500 mV
Notes 1. Refer to TIMING CHART 2.
2. When the fall time of
φ
1 (t1) is the TYP. value (refer to TIMING CHART 2).
5
Page 6
INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V)
Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit
µ
PD3794
Shift register clock pin capacitance 1 C Shift register clock pin capacitance 2 C Reset gate clock pin capacitance C Transfer gate clock pin capacitance C
φ
1
φ
2
φ
RB
φ
TG
φ
1 14 300 pF
φ
2 9 300 pF
φ
RB 3 20 pF
φ
TG1 13 50 pF
φ
TG2 12 50 pF
φ
TG3 10 50 pF
RGB select input pin capacitance CSEL SEL1 22 50 pF
SEL2 20 50 pF
RGB SELECT FUNCTION
RGB select input
SEL1 SEL2 High level High level Blue High level Low level Green Low level High level Red Low level Low level Prohibited
Output color
6
Page 7
123456789101112131415
6162636465
66
2763
2764
2765
2766
2767
2768
2769
SEL2
SEL1
φ
TG1 to
TG3
φ
1
2
φ
φ
RB
φ
V
OUT
a
b
(Blue)
Optical black
(48 pixels)
Invalid photocell
(2 pixels)
Valid photocell (2700 pixels)
Invalid photocell
(3 pixels)
Note
Note
Note
φ
RB pluse continuously during this period, too.Input the
TIMING CHART 1-1
16
7
µ
PD3794
Page 8
8
123456789101112131415
6162636465
66
2763
2764
2765
2766
2767
2768
2769
SEL2
SEL1
φ
TG1 to
TG3
φ
1
2
φ
φ
RB
φ
V
OUT
b
c
(Green)
Optical black
(48 pixels)
Invalid photocell
(2 pixels)
Valid photocell (2700 pixels)
Invalid photocell
(3 pixels)
Note
Note
Note
φ
RB pluse continuously during this period, too.Input the
TIMING CHART 1-2
16
µ
PD3794
Page 9
123456789101112131415
6162636465
66
2763
2764
2765
2766
2767
2768
2769
SEL2
SEL1
φ
TG1 to
TG3
φ
1
2
φ
φ
RB
φ
V
OUT
c
a
(Red)
Optical black
(48 pixels)
Invalid photocell
(2 pixels)
Valid photocell (2700 pixels)
Invalid photocell
(3 pixels)
Note
Note
Note
φ
RB pluse continuously during this period, too.Input the
TIMING CHART 1-3
16
9
µ
PD3794
Page 10
TIMING CHART 2 (for each color)
φ
µ
PD3794
t2t1
φ
1
φ
2
t5
φ
RB
V
OUT
φ
TG1 to φTG3, φ1, φ2 TIMING CHART
90 %
10 %
φ
TG1 to TG3
φ
t6
t3
90 %
10 %
90 %
10 %
t4
+
t
10 %
90 %
10 %
t10
d
t8
t7
RFTN
RFTN
_
t9
t11
OS
V
φ
1, φ2 cross points
90 %
φ
1
φ
2
Symbol MIN. TYP. MAX. Unit t1, t2 0 25 ns t3 30 50 ns t4 150 250 ns t5, t6 0 25 ns t7 3000 10000 ns t8, t9 0 50 ns t10, t11 900 1000 ns
φ
1
2 V or more 2 V or more
2
Remark Adjust cross points of φ1 and φ2 with input resistance of each pin.
10
Page 11
µ
PD3794
APPLICATION TIMING EXAMPLE (for reference)
The µPD3794 can be operated under the following timing to switch Red, Green, and Blue outputs and get each color data in a 1-pixel period. However the offset level of each color is not the same. Therefore, offset level compensation is required to each color by using each color’s data at dark or the optical black pixels.
The following timing and parameters are for reference only.
SEL1
SEL2
φ
φ
φ
RB
V
OUT
t
R
1
2
t
G
t
B
at dark
with light
Red Green Blue
Symbol MIN. TYP. MAX. Unit tR, tG, tB 300 ns
11
Page 12
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost.
2. Saturation exposure: SE Product of intensity of illumination (I
3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
X) and storage time (s) when saturation of output voltage occurs.
µ
PD3794
PRNU (%) =
x
× 100
x
x : maximum of x
x = x
OUT
V
Register Dark
DC level
j x
2700
xj
Σ
j=1
2700
j : Output voltage of valid pixel number j
x
x
4. Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
2700
d
j
Σ
ADS (mV) =
j=1
2700
j
: Dark signal of valid pixel number j
d
5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of d
ADS
j = 1 to 2700
j
dj : Dark signal of valid pixel number j
V
OUT
ADS
Register Dark
DC level
DSNU
12
Page 13
6. Output impedance: ZO Impedance of the output pins viewed from outside.
7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source (spectral characteristic).
8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line.
φ
TG
µ
PD3794
Light
V
OUT
ON OFF
V
OUT
V
1
V1 IL (%) = ×100
V
OUT
9. Random noise: σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding).
100
(Vi – V)
σ (mV) = , V =
Σ
i=1
2
100
i: A valid pixel output signal among all of the valid pixels for each color
V
OUT
1
100
100
Σ
i=1
V
i
V
1
V
2
line 1V
line 2
V
100
line 100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
13
Page 14
STANDARD CHARACTERISTIC CURVES
g
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
8
4
2
1
0.5
Relative Output Voltage
0.25
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
2
1
Relative Output Voltage
0.2
A = +25 °C)
µ
PD3794
0.1 100 20304050
Operatin
100
80
60
40
Response Ratio (%)
20
Ambient Temperature TA(°C) Storage Time (ms)
0.1 1510
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter) (T
R
B
G
A
= +25 °C)
G
14
0
400
500 600
Wavelength (nm)
B
700 800
Page 15
APPLICATION CIRCUIT EXAMPLE
VOUT
PD3794
µ
NC
GND
NC
NC
NC
NC
NC
NC
NC
GND
NC
GND
φ
TG3
φ
φ
2
φ
TG1
φ
1
φ
TG2
47
4.7
10
10
4.7
10
122
21
20
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
10
11
B
SEL1
SEL2
V
OD
φ
RB
+12 V
10
µ
0.1 Fµ47 F/25 V SEL1
SEL2
µ
0.1 F
µ
10 F/16 V
TG
1
φ
φ
RB
φ
+
+5 V
+5 V
+
2
47
47
µ
0.1 Fµ10 F/16 V
+
µ
PD3794
Remark Inverters: 74HC04
OUT
B EQUIVALENT CIRCUIT
CCD V
100
100
12 V
+
µ
47 F/25 V
2SC945
2 k
15
Page 16
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22PIN PLASTIC DIP (400 mil)
(Unit : mm)
1st valid pixel
µ
PD3794
3.95±0.3
1.02±0.15
0.46±0.1
3
37.5
44.0±0.3
25.4
2.54
(5.42)
4.21±0.5
2.0
9.25±0.3
4.39±0.4
0~10°
(1.99)
10.16
2.35±0.2
0.25±0.05
1
16
Name Dimensions
Plastic cap
1 The bottom of the package The surface of the chip 2 The thickness of the cap over the chip 3 The 1st valid pixel The center of the pin 1.
42.9 x 8.35 x 0.7
Refractive index
2
22C-1CCD-PKG10-1
1.5
Page 17
µ
PD3794
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E).
Type of Through-hole Device
µ
PD3794CY: CCD linear image sensor 22-pin plastic DIP (400 mil)
Process
Partial heating method
Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap.
The optical characteristics could be degraded by such contact.
Pin temperature: 260 °C or below, Heat Time: 10 seconds or less (per pin)
Conditions
17
Page 18
NOTES ON CLEANING THE PLASTIC CAP
1 CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used.
µ
PD3794
2 RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent.
Solvents Symbol
Ethyl Alcohol EtOH Methyl Alcohol MeOH Isopropyl Alcohol IPA N-methyl Pyrrolidone NMP
18
Page 19
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
µ
PD3794
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
19
Page 20
µ
PD3794
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
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