Datasheet UPD3778CY Datasheet (NEC)

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD3778

10600 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR

The µPD3778 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to

electrical signal and has the function of color separation.

µ

PD3778 has 3 rows of 10600 pixels, and each row has a double-sided readout type of charge transfer register.

The
And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color
image scanners and so on.

FEATURES

• Valid photocell : 10600 pixels × 3

• Photocell's pitch : 4 µm

• Photocell size : 4 × 4 µm

• Line spacing : 48 µm (12 lines) Red line-Green line, Green line-Blue line

• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)

• Resolution : 48 dot/mm A4 (210 × 297 mm) size (shorter side)

1200 dpi US letter (8.5” × 11”) size (shorter side)

• Drive clock level : CMOS output under 5 V operation

• Data rate : 5 MHz MAX.

• Power supply : +12 V

• On-chip circuits : Reset feed-through level clamp circuits

Voltage amplifiers

2

ORDERING INFORMATION

Part Number Package

µ

PD3778CY CCD linear image sensor 32-pin plastic DIP (400 mil)

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.

Document No. S14374EJ1V0DS00 (1st edition)
Date published July 1999 N CP(K)
Printed in Japan

©

1999

2

V
(

V
(

V
(

BLOCK DIAGRAM

Data Sheet S14374EJ1V0DS00

OUT

1

Blue)

OUT

2

Green)

OUT

3

Red)

30

31

32

φ

V

OD

GND GND

1

1629

........

D14

........

D14

........

D14

CCD analog shift register

Transfer gate

Photocell

S1

S2

D64

CCD analog shift register

CCD analog shift register

D64

CCD analog shift register

CCD analog shift register

D64

CCD analog shift register

(Blue)

Transfer gate

Transfer gate

Photocell

S1

S2

(Green)

Transfer gate

Transfer gate

Photocell

S1

S2

(Red)

Transfer gate

S10599

S10600

S10599

S10600

S10599

S10600

D65

D65

D65

D66

D66

D66

2

22

D67

D67

D67

φ

19

1

φ

TG1

18

(Blue)

φ

TG2

17

(Green)

φ

TG3

15

(Red)

14

φ

2

φ

3

CLB

2

φ

RB

11

φ

µ

PD3778

1

PIN CONFIGURATION (Top View)

CCD linear image sensor 32-pin plastic DIP (400 mil)

•µPD3778CY

1

φ

Reset gate clock

Reset feed-through level
clamp clock

φ

RB

CLB

2

1

3

µ

PD3778

OUT

3GND

V

32

V

31

1

1

V

30

Output signal 3 (Red)Ground

OUT

2

Output signal 2 (Green)

OUT

1

Output signal 1 (Blue)

No connection

No connection

No connection

No connection NC

No connection NC

Shift register clock 1

Shift register clock 2

Transfer gate clock 3
(for Red)

Ground

φ

GND

NC

NC

NC

φ

φ

TG3

4

5

6

ICInternal connection

7

ICInternal connection

8

9

10

11

1

ICInternal connection

12

ICInternal connection

13

2

14

15

16

Red

10600

Green

10600

Blue

10600

V

29

NC

28

IC

27

IC

26

NC

25

NC No connection

24

NC No connection

23

φ

22

21

IC Internal connection

20

IC Internal connection

φ

19

φ

18

φ

17

Output drain voltage

OD

No connection

Internal connection

Internal connection

No connection

Shift register clock 2

2

1

Shift register clock 1
Transfer gate clock 1

TG1

(for Blue)
Transfer gate clock 2

TG2

(for Green)

Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.

Data Sheet S14374EJ1V0DS00

3

µ

PD3778

PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM

(Line spacing)

4 m

2 m

µ

Aluminum
shield

µ

4 m

2

m

µ

Channel stopper

µ

4 m

µ

4 m

µ

Blue photocell array

Green photocell array

Red photocell array

12 lines
(48 m)

µ

12 lines
(48 m)

µ

4

Data Sheet S14374EJ1V0DS00

µ

PD3778

ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)

Parameter Symbol Ratings Unit
Output drain voltage VOD –0.3 to +15 V
Shift register clock voltage V
Reset gate clock voltage V
Reset feed-through level clamp clock voltage V
Transfer gate clock voltage V

φ

1, Vφ2 –0.3 to +8 V

φ

RB –0.3 to +8 V

φ

CLB –0.3 to +8 V

φ

TG1

to V

φ

TG3 –0.3 to +8 V

Operating ambient temperature TA –25 to +60 °C
Storage temperature Tstg –40 to +70 °C

Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;

exceeding the ratings could cause permanent damage. The parameters apply independently.

RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)

Parameter Symbol MIN. TYP. MAX. Unit
Output drain voltage VOD 11.4 12.0 12.6 V
Shift register clock high level V
Shift register clock low level V
Reset gate clock high level V
Reset gate clock low level V
Reset feed-through level clamp clock high level V
Reset feed-through level clamp clock low level V
Transfer gate clock high level V
Transfer gate clock low level V
Data rate f

φ

1H, Vφ2H 4.5 5.0 5.5 V

φ

1L, Vφ2L –0.3 0 +0.5 V

φ

RBH 4.5 5.0 5.5 V

φ

RBL –0.3 0 +0.5 V

φ

CLBH 4.5 5.0 5.5 V

φ

CLBL –0.3 0 +0.5 V

φ

TG1H

to V

φ

TG3H 4.5 V

φ

TG1L

to V

φ

TG3L –0.3 0 +0.5 V

φ

RB – 1.0 5.0 MHz

Note

φ

1H

Note

V

φ

1H

V

Note When Transfer gate clock high level (V

Image lag can increase.

Data Sheet S14374EJ1V0DS00

φ

TG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H),

5

ELECTRICAL CHARACTERISTICS

µ

PD3778

TA = +25 °C, VOD = 12 V, data rate (f

φ

RB) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p,

light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm) + HA-50 (heat absorbing filter, t = 3 mm)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Saturation voltage Vsat 2.0 2.5 – V
Saturation exposure Red SER 0.694 lx•s

Green SEG 0.757 lx•s

Blue SEB 1.250 lx•s
Photo response non-uniformity PRNU VOUT = 1.0 V 6 20 %
Average dark signal ADS Light shielding 0.2 4.0 mV
Dark signal non-uniformity DSNU Light shielding 1.5 4.0 mV
Power consumption PW 400 600 mW
Output impedance ZO 0.5 1 kΩ
Response Red RR 2.52 3.60 4.68 V/lx•s

Green RG 2.31 3.30 4.29 V/lx•s

Blue RB 1.40 2.00 2.60 V/lx•s
Image lag IL VOUT = 1.0 V 2.0 10.0 %
Offset level
Output fall delay time
Total transfer efficiency TTE VOUT = 1.0 V, 92 98 %

Register imbalance RI VOUT = 1.0 V 0 1.0 4.0 %
Response peak Red 630 nm

Dynamic range DR1 Vsat /DSNU 1666 times

Reset feed-through noise
Random noise (CDS) σ CDS Light shielding – 1.0 – mV

Note1

VOS 4.0 6.0 7.0 V

Note2

Green 540 nm

Blue 460 nm

Note1

td VOUT = 1.0 V 50 ns

data rate = 5 MHz

DR2 Vsat /σ CDS 2500 times
RFTN Light shielding –1000 –300 +500 mV

Notes 1. Refer to TIMING CHART 2.

2. When each fall time of

6

φ

1 and φ2 (t2, t1) is the TYP. value (refer to TIMING CHART 2).

Data Sheet S14374EJ1V0DS00

INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V)

Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit

Shift register clock pin capacitance 1 C

Shift register clock pin capacitance 2 C

Reset gate clock pin capacitance C
Reset feed-through level clamp clock pin capacitance
Transfer gate clock pin capacitance C

Remark Pins 11 and 19 (φ1), 14 and 22 (φ2) are each connected inside of the device.

φ

1

φ

1 11 400 pF

19 400 pF

φ

2

φ

2 14 400 pF

22 400 pF

φ

RB

C

φ

CLB

φ

TG

φ

RB 2 15 pF

φ

CLB 3 15 pF

φ

TG1 18 120 pF

φ

TG2 17 120 pF

φ

TG3 15 120 pF

µ

PD3778

Data Sheet S14374EJ1V0DS00

7

8

12345678910111213

141615

6162636465

66

10663

10664

10665

10666

10667

10668

10669

V

OUT

1 to

V

OUT

3

CLB

φ

RB

φ

2

φ

1

φ

TG1 to

φ

TG3

φ

NoteNote

Invalid photocell

(3 pixels)

Invalid photocell

(2 pixels)

Valid photocell

(10600 pixels)

Optical black

(49 pixels)

1

2

3

4

5

6

7

8

TIMING CHART 1 (for each color)

Data Sheet S14374EJ1V0DS00

Note Input the

φ

RB and

φ

CLB pulses continuously during this period, too.

µ

PD3778

TIMING CHART 2 (for each color)

φ

VOUT

CLB

φ

RB

φ

2

φ

1

90 %

10 %

90 %

10 %

90 %

10 %

90 %

10 %

+

_

RFTN

RFTN

V

OS

t2t1

t4

t6

t3

t5

t10

t8

t7

t9

t11

t

d

10 %

td

10 %

Data Sheet S14374EJ1V0DS00

9

µ

PD3778

φ

TG1 to φTG3, φ1, φ2 TIMING CHART

µ

PD3778

φ

TG1 to TG3

φ

t13

90 %

10 %

t15

90 %

φ

1

φ

2

Symbol MIN. TYP. MAX. Unit
t1, t2 0 25 – ns
t3 20 50 – ns
t4 70 250 – ns
t5, t6 0 25 – ns
t7 30 50 – ns
t8, t9 0 25 – ns
t10 30 50 – ns
t11 5 15 – ns
t12 5000 10000 – ns
t13, t14 0 50 – ns
t15, t16 900 1000 – ns

t12

t14

t16

φ

1, φ2 cross points

φ

1

2.0 V or more

φ

2

Remark Adjust cross points of φ1 and φ2 with input resistance of each pin.

10

Data Sheet S14374EJ1V0DS00

2.0 V or more

µ

PD3778

DEFINITIONS OF CHARACTERISTIC ITEMS

1. Saturation voltage: Vsat
Output signal voltage at which the response linearity is lost.

2. Saturation exposure: SE
Product of intensity of illumination (I

3. Photo response non-uniformity: PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.

X) and storage time (s) when saturation of output voltage occurs.

PRNU (%) =

∆x

× 100

x

∆x : maximum of x

x =

j : Output voltage of valid pixel number j

x

V

OUT

Register Dark

DC level

10600

Σ

j=1

10600

j − x 

xj

x

∆x

4. Average dark signal: ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.

10600

d

j

Σ

ADS (mV) =

j=1

10600

j

: Dark signal of valid pixel number j

d

5. Dark signal non-uniformity: DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.

DSNU (mV) : maximum of d

− ADS 

j = 1 to 10600

j

dj : Dark signal of valid pixel number j

V

OUT

ADS

Register Dark

DC level

DSNU

Data Sheet S14374EJ1V0DS00

11

6. Output impedance: ZO
Impedance of the output pins viewed from outside.

7. Response: R
Output voltage divided by exposure (Ix•s).
Note that the response varies with a light source (spectral characteristic).

8. Image Lag: IL
The rate between the last output voltage and the next one after read out the data of a line.

φ

TG

µ

PD3778

Light

OUT

V

ON OFF

V

OUT

V

1

V1
IL (%) = ×100

V

OUT

9. Register imbalance: RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average
output voltage of all the valid pixels.

n
2

2

(V2j – 1 – V2j)

∑

n

RI (%) =

j = 1

1

∑

n

j = 1

n

×100

V j

n : Number of valid pixels

j : Output voltage of each pixel

V

12

Data Sheet S14374EJ1V0DS00

µ

PD3778

10. Random noise (CDS): σCDS
Random noise (CDS) σCDS is defined as the standard deviation of a valid pixel output signal with 100 times (=
100 lines) data sampling at dark (light shielding). This is measured by the following procedure.

1. One valid photocell in one reading is fixed as measurement point.

2. The output level is measured during the Reset feed-through period which is averaged over 100 ns to get “VD

3. The output level is measured during the Video output time averaged over 100 ns to get “VOi”.

4. The correlated double sampling output is defined by “VCDSi = VDi – VOi”.

5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).

6. Calculate the standard deviation σCDS using the following formula.

i”.

100

(VCDSi – V)

σCDS (mV) = , V =

V

OUT

Σ

i=1

100

Reset feed-through

2

100

1

Σ

100

i=1

Video output

VCDSi

Data Sheet S14374EJ1V0DS00

13

STANDARD CHARACTERISTIC CURVES (Nominal)

g

DARK OUTPUT TEMPERATURE

CHARACTERISTIC

8

4

2

1

0.5

Relative Output Voltage

0.25

STORAGE TIME OUTPUT VOLTAGE

CHARACTERISTIC (T

2

1

Relative Output Voltage

0.2

A = +25 °C)

µ

PD3778

0.1
100 20304050

Operatin

Ambient Temperature TA(°C) Storage Time (ms)

100

80

60

40

Response Ratio (%)

20

0.1

TOTAL SPECTRAL RESPONSE CHARACTERISTICS

(without infrared cut filter and heat absorbing filter) (T

R

B

G

1510

A

= +25 °C)

G

14

0

400

500 600

Wavelength (nm)

Data Sheet S14374EJ1V0DS00

B

700 800

APPLICATION CIRCUIT EXAMPLE

PD3778

µ

µ

PD3778

φ

φ

RB

CLB

φ

φ

φ

TG

+5 V

10 F/16 V

1

2

1

47 Ω

47 Ω

+

µ

µ

0.1 F

4.7 Ω

4.7 Ω

4.7 Ω

10

11

12

13

14

15

16

2

φ

RB

3

φ

CLB

4

NC

5

NC

6

IC

7

IC

8

NC

9

NC

NC

φ

1

IC

IC

φ

2

φ

TG3

GND

V

V

V

φ

φ

OUT

OUT

OUT

V

OD

NC

IC

IC

NC

NC

NC

φ

IC

IC

φ

TG1

TG2

32

3GND

2

1

2

1

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

B3

B2

B1

4.7 Ω

4.7 Ω

4.7 Ω

4.7 Ω

µ

0.1 F

10 Ω

+

µ

47 F/25 V

µ

0.1 F

+12 V

+5 V

+

µ

10 F/16 V

Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.

Remark The inverters shown in the above application circuit example are the 74HC04 or 74AC04.

Data Sheet S14374EJ1V0DS00

15

B1 to B3 EQUIVALENT CIRCUIT

12 V

+

100 Ω

µ

47 F/25 V

µ

PD3778

CCD
V

OUT

100 Ω

2SC945

2 kΩ

16

Data Sheet S14374EJ1V0DS00

PACKAGE DRAWING

CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (400 mil)

(Unit : mm)

µ

PD3778

1st valid pixel

32

12.6±0.5

6.15±0.3

116

1.02±0.15

0.46±0.06

1

54.8±0.5

55.2±0.5

38.1

4.1±0.5

2.54

17

(5.42)

4.21±0.5

4.55±0.5

9.05±0.3

9.25±0.3

0~10°

10.16
(1.80)

2.58±0.3

0.25±0.05

2

3

1 The 1st valid pixel The center of the pin1
2 The surface of the chip The top of the cap
3 The bottom of the package The surface of the chip
4 Thickness of plastic cap over CCD chip

Data Sheet S14374EJ1V0DS00

Refractive indexDimensionsName

4

1.552.2×6.4×0.7Plastic cap

32C-1CCD-PKG3

17

RECOMMENDED SOLDERING CONDITIONS

When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure

to consult with our sales offices.

For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E).

Type of Through-hole Device

µ

PD3778CY : CCD linear image sensor 32-pin plastic DIP (400 mil)

µ

PD3778

Process

Partial heating method

Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap.

The optical characteristics could be degraded by such contact.

Pin temperature: 300 °C or below,
Heat time: 3 seconds or less (per pin)

Conditions

18

Data Sheet S14374EJ1V0DS00

NOTES ON CLEANING THE PLASTIC CAP

1 CLEANING THE PLASTIC CAP

Care should be taken when cleaning the surface to prevent scratches.
The optical characteristics of the CCD will be degraded if the cap is scratched during
cleaning.

We recommend cleaning the cap with a soft cloth moistened with one of the recommended
solvents below. Excessive pressure should not be applied to the cap during cleaning. If the
cap requires multiple cleanings it is recommended that a clean surface or cloth be used.

2 RECOMMENDED SOLVENTS

µ

PD3778

The following are the recommended solvents for cleaning the CCD plastic cap. Use of
solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.

Solvents Symbol

Ethyl Alcohol EtOH
Methyl Alcohol MeOH
Isopropyl Alcohol IPA
N-methyl Pyrrolidone NMP

Data Sheet S14374EJ1V0DS00

19

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

DD or GND with a resistor, if it is considered to have a possibility of

µ

PD3778

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

20

Data Sheet S14374EJ1V0DS00

[MEMO]

µ

PD3778

Data Sheet S14374EJ1V0DS00

21

[MEMO]

µ

PD3778

22

Data Sheet S14374EJ1V0DS00

[MEMO]

µ

PD3778

Data Sheet S14374EJ1V0DS00

23

µ

PD3778

[MEMO]

• The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

M7 98.8