Datasheet UPD3777CY Datasheet (NEC)

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD3777

µ µ

5400 PIXELS

The

PD3777 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical

µ

signal and has the function of color separati on.

The

PD3777 has 3 rows of 5400 pixels, and each row has a double-sided readout type of charge transfer register. And

µ

it has reset feed-through level clamp circuits, a clamp pulse generation circuit and voltage amplifiers. Therefore, it is suitable for 600 dpi/A4 color image scanners, color facsimiles and so on.

FEATURES

Valid photocell : 5400 pixels × 3

•

Photocell’s pitch : 5.25

•

Photocell size : 5.25 × 5.25

•

Line spacing : 42

•

Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)

•

Resolution : 24 dot/mm A4 (210 × 297 mm) size (shorter side)

•

m

µ

m (8 lines) Red line - Green line, Green line - Blue line

µ

3 COLOR CCD LINEAR IMAGE SENSOR

××××

2

m

µ

: 600 dpi US letter (8.5” × 11”) size (shorter side)

Drive clock level : CMOS output under 5 V operation

•

Data rate : 4 MHz MAX.

•

Power supply : +12 V

•

On-chip circuits : Reset feed-through level clamp circuits

•

: Clamp pulse generation circuit : Voltage amplifiers

ORDERING INFORMATION

Part Number Package

PD3777CY CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))

µ

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. S14583EJ1V0DS00 (1st edition) Date Published December 1999 NS CP (K) Printed in Japan

©

1999

2

BLOCK DIAGRAM

φ

V

OD

19

OUT

1

V (Blue)

Data Sheet S14583EJ1V0DS00

OUT

V (Green)

OUT

V (Red)

21

2

22

3

1

Clamp pulse

generator

2L

GND GND

2

1117

........

D14

........

D14

........

D14

CCD analog shift register

Transfer gate

Photocell

S1

S2

D64

CCD analog shift register

D64

CCD analog shift register

D64

CCD analog shift register

(Blue)

Transfer gate

Photocell

S1

S2

(Green)

Transfer gate

Photocell

S1

S2

(Red)

Transfer gate

S5399

S5400

S5399

S5400

S5399

S5400

D65

D66

D67

φ

14

1

φ

TG1

13

(Blue)

φ

TG2

12

(Green)

φ

TG3

10

(Red)

µ µ

µ

PD3777

3

φ

RB

4

φ

1L

9

φ

2

PIN CONFIGURATION (Top View)

CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))

PD3777CY

•

µ

PD3777

µ µ

Output signal 3 (Red)

Ground

Reset gate clock

Last stage shift register clock 1

No connection

Shift register clock 2

Transfer gate clock 3 (for Red)

Ground

V

GND

φ

GND

OUT

RB

φ

1L

NC

NCNo connection

NC

φ

TG3

1

3

2

1

3

4

5

6

7

8

2

9

10

11

Red

5400

Green

5400

Blue

5400

V

22

V

21

NC No connection

20

V

19

NC

18

φ

17

NC

16

NC

15

φ

14

φ

13

φ

12

Output signal 2 (Green)

OUT

2

Output signal 1 (Blue)

OUT

1

Output drain voltage

OD

No connection

Last stage shift register clock 2

2L

No connection

Shift register clock 1

1

Transfer gate clock 1

TG1

(for Blue) Transfer gate clock 2

TG2

(for Green)

PHOTOCELL STRUCTURE DIAGRAM

2.5

µ

2.75 m

µ

Aluminum shield

µ

5.25 m

m

Channel stopper

PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)

5.25 m

µ

5.25 m

µ

5.25 m

µ

Data Sheet S14583EJ1V0DS00

Blue photocell array

Green photocell array

Red photocell array

8 lines

µ

(42 m)

8 lines

(42 m)

µ

3

µ

PD3777

µ µ

ABSOLUTE MAXIMUM RATINGS (TA = +25

C)

°°°°

Parameter Symbol Ratings Unit Output drain voltage V Shift register clock voltage V Reset gate clock voltage V Transfer gate clock voltage V Operating ambient temperature T Storage temperature T

OD

φ

, V

φ

1L

2L

, V

φ

TG3

1

2

, V

φ

RB

φ

TG1

to V

A

stg

−

0.3 to +15 V

−

0.3 to +8 V

−

0.3 to +8 V

−

0.3 to +8 V

−

25 to +60

−

40 to +70

°

C

°

C

Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;

exceeding the ratings could cause permanent damage. The parameters apply independently.

RECOMMENDED OPERATING CONDITIONS (TA = +25

Parameter Symbol MIN. TYP. MAX. Unit Output drain voltage V Shift register clock high level V Shift register clock low level V Reset gate clock high level V Reset gate clock low level V Transfer gate clock high level V Transfer gate clock low level V Data rate f

OD

φ

TG3H

TG3L

1LL

1LH

, V

φ

2LH

φ

2LL

1H

2H

, V

φ

1L

2L

, V

φ

RBH

φ

RBL

φ

TG1H

to V

φ

RB

TG1L

to V

φ

C)

°°°°

11.4 12.0 12.6 V

4.5 5.0 5.5 V

−

0.3 0 +0.5 V

4.5 5.0 5.5 V

−

0.3 0 +0.5 V

4.5 V

−

0.3 0 +0.5 V

−

Note

φ

1H

Note

φ

1H

V

1.0 4.0 MHz

V

When Transfer gate clock high level (V

Note

lag can increase.

φ

TG1H

to V

TG3H

) is higher than Shift register clock high level (V

φ

1H

), Image

φ

4

Data Sheet S14583EJ1V0DS00

ELECTRICAL CHARACTERISTICS

µ

PD3777

µ µ

TA = +25 °C, VOD = 12 V, data rate (f

RB

) = 1 MHz, storage time = 5.5 ms, input signal clock = 5 V

φ

p-p

,

light source : 3200 K halogen lamp + C−500S (infrared cut filter, t = 1 mm) + HA−50 (heat absorbing filter, t = 3 mm)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Saturation voltage V Saturation exposure

Red SER 0.420 lx•s

sat

2.0 2.5

Green SEG 0.429 lx•s Blue SEB 0. 739 lx•s

Photo response non-uniformity PRNU V

OUT

= 1.0 V 6 20 % Average dark signal ADS Light shielding 0.2 2.0 mV Dark signal non-uniformity DSNU Light shielding 1.5 5.0 mV Power consumption P Output impedance Z Response

Red R Green R

Blue R Image lag IL V Offset level Output fall delay time

Note 1

Note 2

Total transfer efficiency TTE V Register imbalance RI V Response peak

Red 630 nm

W

O

R

G

B

OUT

= 1.0 V 2.0 7.0 %

OS

V

d

t

OUT

V

= 1.0 V 50 ns

OUT

= 1.0 V, data rate = 4 MHz 92 98 %

OUT

= 1.0 V 0 1.0 4.0 %

4.15 5.94 7.72 V/lx•s

4.07 5.82 7.57 V/lx•s

2.36 3.38 4.39 V/lx•s

4.0 5.5 7.0 V

360 540 mW

0.5 1 k

Green 540 nm

Blue 460 nm

sat

/DSNU 1666 timesDynamic range

sat

σ

/

Light shielding

−

1000

2500 times

−

300 +500 mV

−

1.0

Reset feed-through noise Random noise

Note 1

DR1 V DR2 V RFTN Light shielding

σ

−

V

mV

Ω

Notes 1.

Refer to When each fall time of

2.

TIMING CHART 2

1L and

φ

.

2L (t2’, t1’) is the TYP. value (refer to

φ

Data Sheet S14583EJ1V0DS00

TIMING CHART 2

).

5

µ

PD3777

µ µ

INPUT PIN CAPACITANCE (TA = +25

Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit Shift register clock pin capacitance 1 C Shift register clock pin capacitance 2 C

Reset gate clock pin capacitance C Transfer gate clock pin capacitance C

C, VOD = 12 V)

°°°°

φ

1

φ

2

φ

L

φ

RB

φ

TG

φ

1 14 650 pF

φ

2 9 650 pF

φ

1L 4 10 pFLast stage shift register clock pin capacitance C

φ

2L 17 10 pF

φ

RB 3 10 pF

φ

TG1 13 60 pF

φ

TG2 12 60 pF

φ

TG3 10 60 pF

6

Data Sheet S14583EJ1V0DS00

TIMING CHART 1 (for each color)

TG1 to

φ

TG3

φ

1

φ

2

φ

1L

φ

2L

φ

Data Sheet S14583EJ1V0DS00

RB

φ

V

OUT

1 to

V

OUT

3

1

12345678910111213

2

3

4

5

6

7

8

NoteNote

5463

5464

5465

5466

5467

141615

6162636465

66

5468

5469

Valid photocell

(5400 pixels)

Invalid photocell

(3 pixels)

µ µ

µ

Note

Input the

RB pulse continuously during this period, too.

φ

Optical black

(49 pixels)

Invalid photocell

(2 pixels)

PD3777

7

8

TIMING CHART 2 (for each color)

t2t1

φ

1

φ

2

φ

1L

Data Sheet S14583EJ1V0DS00

φ

2L

t5

φ

RB

90 %

10 %

t6

t3

90 %

10 %

90 %

10 %

t2't1'

90 %

10 %

90 %

10 %

t4

+

t

d

RFTN

t

d

V

OUT

V

OS

10 %

_

RFTN

10 %

µ µ

µ

PD3777

µ

PD3777

µ µ

TG1 to

φφφφ

TG3,

φφφφ

TG1 to TG3

φ

1,

2 TIMING CHART

φφφφ

φ

1

φ

2

Symbol MIN. TYP. MAX. Unit t1, t2 0 50 t1’, t2’ 0 5 t3 20 150 t4 130 300 t5, t6 0 50 t7 3000 10000 t8, t9 0 50 t10, t11 900 1000

90 %

10 %

t10

t8

t7

t9

t11

−

ns ns ns ns ns ns ns ns

1,

2 cross points

φ

φ φ

1L,

φ

φ φ

φ

φ φ

2 cross points

φ

φ φ

1,

2L cross points

φ

φ φ

φ

1

2 V or more 2 V or more

φ

2

φ

2

2 V or more

φ

1L

φ

1

2 V or more

φ

2L

0.5 V or more

Remark

Adjust cross points (

1,

2), (

φ

1L,

2) and (

φ

Data Sheet S14583EJ1V0DS00

1,

2L) with input resistance of each pin.

φ

9

DEFINITIONS OF CHARACTERISTIC ITEMS

µ

PD3777

µ µ

1. Saturation voltage : Output signal voltage at which the response linearity is lost.

2. Saturation exposure : Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.

3. Photo response non-uniformity : The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.

PRNU (%) =

∆x

sat

V

SE

× 100

x

∆x : maximum of x

x = x

j

: Output voltage of valid pixel number j

5400

Σ

j = 1

5400

PRNU

x

OUT

V

j

− x 

j

Register Dark

DC level

4. Average dark signal : Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.

ADS (mV) =

5400

Σ

j = 1

5400

ADS

d

j

: Dark signal of valid pixel number j

d

∆x

x

10

Data Sheet S14583EJ1V0DS00

µ

PD3777

µ µ

5. Dark signal non-uniformity :

DSNU

Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula.

DSNU (mV) : maximum of d

j − ADS j = 1 to 5400

dj : Dark signal of valid pixel number j

OUT

V

ADS

Register Dark

DC level

DSNU

6. Output impedance :

O

Z

Impedance of the output pins viewed from outside.

7. Response :

R

Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic).

8. Image lag :

IL

The rate between the last output voltage and the next one after read out the data of a line.

φ

TG

Light

V

OUT

V

IL (%) =

VOUT

1

× 100

9. Register imbalance :

RI

ON OFF

V

OUT

V

1

The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.

n 2

2

(V

RI (%) =

2j – 1 – V2j

∑

n

j = 1

1 n

∑

j = 1

)

n

V

j

× 100

: Number of valid pixels

n

j

: Output voltage of each pixel

V

Data Sheet S14583EJ1V0DS00

11

µ

PD3777

µ µ

10. Random noise :

Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding).

σ

(mV) =

This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).

σσσσ

100

Σ

i = 1

(Vi – V)

2

100 100

Vi : A valid pixel output signal among all of the valid pixels for each color

, V =

OUT

100

1

V

i

Σ

i = 1

V1

V2

…

V100

line 1V

line 2

…

line 100

12

Data Sheet S14583EJ1V0DS00

STANDARD CHARACTERISTIC CURVES (Nominal)

DARK OUTPUT TEMPERATURE

CHARACTERISTIC

8

4

2

1

0.5

Relative Output Voltage

0.25

STORAGE TIME OUTPUT VOLTAGE

CHARACTERISTIC (T

2

1

Relative Output Voltage

0.2

µ

µ µ

A

= +25 °C)

PD3777

0.1 100 20304050

Operating Ambient Temperature TA(°C) Storage Time (ms)

0.1 1510

TOTAL SPECTRAL RESPONSE CHARACTERISTICS

A

(without infrared cut filter and heat absorbing filter) (T

100

80

60

40

Response Ratio (%)

20

B

R

G

= +25 °C)

G

0

400

500 600

Wavelength (nm)

Data Sheet S14583EJ1V0DS00

B

700 800

13

APPLICATION CIRCUIT EXAMPLE

µ

PD3777

µ µ

φ

RB

φ

2

µ

10 F/16 V

+

µ

0.1 F

+5 V

47 Ω

150 Ω

4.7 Ω

10 Ω

PD3777

µ

122

V

OUT

GND

φ

RB

φ

1L

NC

φ

2

φ

TG3

GND

3

B3

2

3

4

5

6

7

8

9

10

11

V

φ

OUT

NC

V

NC

φ

2L

NC

φ

TG1

TG2

2

1

OD

1

21

20

19

18

17

16

15

14

13

12

B2

B1

150 Ω

4.7 Ω

10 Ω

+

µ

0.1 Fµ47 F/25 V

µ

0.1 Fµ10 F/16 V

10 Ω

+

+12 V

+5 V

φ

1

φ

TG

Remark

14

The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the 74AC04 (data rate: 2 to 4 MHz).

B1 to B3 EQUIVALENT CIRCUIT

12 V

+

µ

100 Ω

CCD V

OUT

100 Ω

Data Sheet S14583EJ1V0DS00

47 F/25 V

2SC945

2 kΩ

PACKAGE DRAWING

CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400))

(Unit : mm)

1bit

0.5±0.3

2.0

9.25±0.3

37.5

44.0±0.3

µ

PD3777

µ µ

1.02±0.15

0.46±0.1

25.4

2.54

10.16

(1.79)

2.55±0.2

(5.42)

4.21±0.5

4.39±0.4

Name Dimensions

Plastic cap

1 The bottom of the package The surface of the chip 2 The thickness of the cap over the chip

42.9 × 8.35 × 0.7

0 ∼ 10°

2

0.25±0.05

Refractive index

1.5

1

Data Sheet S14583EJ1V0DS00

22C-1CCD-PKG6-1

15

µ

PD3777

µ µ

RECOMMENDED SOLDERING CONDITIONS

When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to

consult with our sales offices.

For more details, refer to our document

Type of Through-hole Device

µµµµ

PD3777CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))

Process Conditions

Partial heating method Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin)

Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The

optical characteristics could be degraded by such contact.

“Semiconductor Device Mounting Technology Manual” (C10535E)

.

16

Data Sheet S14583EJ1V0DS00

[MEMO]

µ

PD3777

µ µ

Data Sheet S14583EJ1V0DS00

17

NOTES ON CLEANING THE PLASTIC CAP

1 CLEANING THE PLASTIC CAP

Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning.

We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used.

2 RECOMMENDED SOLVENTS

µ

PD3777

µ µ

The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent.

Solvents Symbol

Ethyl Alcohol EtOH Methyl Alcohol MeOH Isopropyl Alcohol IPA N-methyl Pyrrolidone NMP

18

Data Sheet S14583EJ1V0DS00

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

DD

pin should be connected to V being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

or GND with a resistor, if it is considered to have a possibility of

µ

PD3777

µ µ

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

Data Sheet S14583EJ1V0DS00

19

µ

PD3777

µ µ

[MEMO]

• The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.

M7 98. 8