Datasheet UPD3729D Datasheet (NEC)

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD3729

5000 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR

The µPD3729 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which

changes optical images to electrical signal and has the function of color separation.

µ

PD3729 has 3 rows of 5000 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge

The
transfer register, which transfers the photo signal electrons of 5000 pixels separately in odd and even pixels.
Therefore, it is suitable for 400 dpi/A3 high-speed color digital copiers and so on.

FEATURES

• Valid photocell : 5000 pixels × 3

• Photocell's pitch : 10 µm

• Line spacing : 40 µm (4 lines) Red line-Green line, Green line-Blue line

7

• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10

• Resolution : 16 dot/mm (400 dpi) A3 (297 × 420 mm) size (shorter side)

• Drive clock level : CMOS output under 5 V operation

• Data rate : 30 MHz MAX. (15 MHz/1 output)

• Output type : 2 outputs in phase/color

• Power supply : +12 V

• On-chip circuits : Reset feed-through level clamp circuits

Voltage amplifiers

lx•hour)

ORDERING INFORMATION

Part Number Package

µ

PD3729D CCD linear image sensor 24-pin ceramic DIP (400 mil)

Document No. S12883EJ1V0DS00(1st edition)
Date published November 1998 N CP(K)
Printed in Japan

The information in this document is subject to change without notice.

©

1998

BLOCK DIAGRAM

µ

PD3729

V

OUT

2

(Blue, even)

OUT

1

V
(Blue, odd)

V

OUT

3

(Green, odd)

V

OUT

4

(Green, even)

22

23

24

1

φ

CLB 1L GND GNDV

20

φφφ

19

OD

12

5

4

21

CCD analog shift register

Transfer gate

. . . . . . . . . .

D27

D128

S1

Photocell

S2

(Blue)

S5000

S4999

D129

Transfer gate

CCD analog shift register

CCD analog shift register

Transfer gate

. . . . . . . . . .

D27

D128

S1

Photocell

S2

(Green)

S5000

S4999

D129

Transfer gate

CCD analog shift register

D134

D134

15

16

21GND

φ

TG1

14

(Blue)

TG2

φ

13

(Green)

V

OUT

6

(Red, even)

V

OUT

5

(Red, odd)

2

3

6

RB

CCD analog shift register

Transfer gate

. . . . . . . . . .

D27

D128

S1

Photocell

S2

(Red)

S5000

S4999

D129

Transfer gate

CCD analog shift register

D134

910

12

φ

TG3

11

(Red)

φφφ

2

PIN CONFIGURATION (Top View)

Blue photocell array

10 m

µ

Green photocell array

10 m

µ

Red photocell array

10 m

µ

4 lines

(40 m)

µ

4 lines

(40 m)

µ

CCD linear image sensor 24-pin ceramic DIP (400 mil)

•µPD3729D

1V

OUT

4Output signal 4 (Green, even)

24

OUT

3

Output signal 3 (Green, odd)

V

µ

PD3729

Ground

Output drain voltage

Reset gate clock

No connection

No connection

Shift register clock 1

Shift register clock 2

Transfer gate clock 3 (for Red)

OUT

OUT

2V

6Output signal 6 (Red, even)

1

1

1

5Output signal 5 (Red, odd)

3V

4GND

OD

5V

6RB

7NC

8NC

φ

91

102

φ

11TG3

Red

Green

Blue

23

22

21

20

19

18

17

16

15

14

OUT

1 Output signal 1 (Blue, odd)

V

V

OUT

2

Output signal 2 (Blue, even)

GND

Ground

Reset feed-through level

φ

CLB

clamp clock

φφ

1L

Last stage shift register clock 1

NC

No connection

NC

No connection

φ

2

Shift register clock 2

φ

1

Shift register clock 1

φφ

TG1

Transfer gate clock 1 (for Blue)

5000

5000

5000

Ground

12GND

13

φ

TG2

Transfer gate clock 2 (for Green)

PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM

(Line spacing)

3

m

µ

Channel stopper

Aluminum
shield

7 m

µ

µ

10 m

3

µ

PD3729

ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)

Parameter Symbol Ratings Unit
Output drain voltage VOD –0.3 to +15 V
Shift register clock voltage V
Reset gate clock voltage V
Reset feed-through level clamp clock voltage V
Transfer gate clock voltage V

φ

1, Vφ1L, Vφ2 –0.3 to +15 V

φ

RB –0.3 to +15 V

φ

CLB –0.3 to +15 V

φ

TG1

to V

φ

TG3 –0.3 to +15 V

Operating ambient temperature TA –25 to +70 °C
Storage temperature Tstg –40 to +100 °C

Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;

exceeding the ratings could cause permanent damage. The parameters apply independently.

RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)

Parameter Symbol MIN. TYP. MAX. Unit
Output drain voltage VOD 11.4 12.0 12.6 V
Shift register clock high level V
Shift register clock low level V
Reset gate clock high level V
Reset gate clock low level V
Reset feed-through level clamp clock high level V
Reset feed-through level clamp clock low level V
Transfer gate clock high level V
Transfer gate clock low level V
Data rate 2f

φ

1H, Vφ1LH, Vφ2H 4.5 5.0 5.5 V

φ

1L, Vφ1LL, Vφ2L –0.3 0 +0.5 V

φ

RBH 4.5 5.0 5.5 V

φ

RBL –0.3 0 +0.5 V

φ

CLBH 4.5 5.0 5.5 V

φ

CLBL –0.3 0 +0.5 V

φ

TG1H

to V

φ

TG3H 4.5 V

φ

TG1L

to V

φ

TG3L –0.3 0 +0.5 V

φ

RB – 2 30 MHz

Note

φ

1H

Note

V

φ

1H

V

Note When Transfer gate clock high level (V

lag can increase.

4

φ

TG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H), Image

ELECTRICAL CHARACTERISTICS

µ

PD3729

TA = +25 °C, VOD = 12 V, f

φ

RB = 1 MHz, data rate = 2 MHz, storage time = 10 ms,

light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Saturation voltage Vsat 1.5 2.0 – V
Saturation exposure Red SER 0.32 lx•s

Green SEG 0.37 lx•s
Blue SEB 0.29 lx•s

Photo response non-uniformity PRNU VOUT = 1 V 6 18 %

Note 1

Note 1

Note 1

Note 1

Green RG 3.8 5.4 7.0 V/lx•s
Blue RB 4.7 6.8 8.9 V/lx•s

Note 3

Green 540 nm
Blue 460 nm

Note 2

ADS1 Light shielding 1.0 5.0 mV
ADS2 0.5 5.0 mV
DSNU1 Light shielding 2.0 5.0 mV
DSNU2 1.0 5.0 mV

IL1 VOUT = 1 V 2.0 5.0 %
IL2 1.0 5.0 %
VOS 4.0 5.0 6.0 V
td VOUT = 1 V 25 ns

data rate = 30 MHz

DR11 Vsat /DSNU1 1000 times
DR12 Vsat/DSNU2 2000 times
DR21 Vsat /σ1 2000 times
DR22 Vsat/σ2 4000 times
RFTN Light shielding –500 +200 +500 mV

σ1 Light shielding – 1.0 – mV
σ2 – 0.5 – mV

Average dark signal

Dark signal non-uniformity

Power consumption P W 500 700 mW
Output impedance ZO 0.3 0.5 kΩ
Response Red RR 4.3 6.2 8.1 V/lx•s

Image lag

Offset level
Output fall delay time
Register imbalance RI VOUT = 1 V 0 4.0 %
Total transfer efficiency TTE VOUT = 1 V, 95 98 %

Response peak Red 630 nm

Dynamic range

Reset feed-through noise
Random noise

Note 1

Note 2

Notes 1. ADS1, DSNU1, IL1, DR11 and DR21 show the specification of VOUT1 and VOUT2.

ADS2, DSNU2, IL2, DR12 and DR22 show the specification of V

OUT3 to VOUT6.

2. Refer to TIMING CHART 2.

3. When the fall time of φ1L (t2’) is the TYP. value (refer to TIMING CHART 2).

5

INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V)

Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit

Shift register clock pin capacitance 1 C

Shift register clock pin capacitance 2 C

Last stage shift register clock pin capacitance C
Reset gate clock pin capacitance C
Reset feed-through level clamp clock pin capacitance C
Transfer gate clock pin capacitance C

Remark Pins 9 and 15 (φ1), 10 and 16 (φ2) are each connected inside of the device.

φ

1

φ

1 9 500 800 pF

15 500 800 pF

φ

2

φ

2 10 500 800 pF

16 500 800 pF

φ

L

φ

1L 19 50 pF

φ

RB

φ

RB 6 50 p F

φ

CLB

φ

CLB 20 50 pF

φ

TG

φ

TG1 14 70 pF

φ

TG2 13 70 pF

φ

TG3 11 70 pF

µ

PD3729

6

91113

101214

TG1 to

1

2

RB

CLB

V

OUT

1, 3, 5

V

OUT

2, 4, 6

TG3

135

7

1517192123

25

246

8

1618202224

26

Optical black

(96 pixels)

Invalid photocell

(6 pixels)

Valid photocell

(5000 pixels)

Invalid photocell

(6 pixels)

28

30

120

122

27

29

119

121

123

125

127

129

124

126

128

130

131132

5126

5128

5130

5132

5125

5127

5129

5131

5133

5135

5137

5134

5136

5138

1L

Note

Note

φ

φ

φ

φ

φ

φ

φ

TIMING CHART 1 (for each color)

7

Note Input the

φ

RB and

φ

CLB pulses continuously during this period, too.

µ

PD3729

TIMING CHART 2 (for each color)

t1 t2

µ

PD3729

φ

OUT1 to

V

V

φ

φ

RB

CLB

OUT6

t1'

90 %

10 %

90 %

90 %

10 %

t5 t6

t3

RFTN

t10

90 %

10 %

t4

t2'

t11

t9t8

t7

t

d

VOS

10 %

1

φ

10 %

2

φ

1L

90 %

10 %

φ

TG1 to φTG3, φ1, φ2 TIMING CHART

φφ

TG1 to TG3

φ

1

φ

2

90 %

90 %

10 %

t15

t13

t12

t14

t16

8

Symbol MIN. TYP. MAX. Unit
t1, t2 0 50 ns
t1’, t2’ 0 5 ns
t3 20 50 ns
t4 20 100 – ns
t5, t6 0 20 ns
t7 20 150 ns
t8, t9 0 20 ns
t10 –10
t11 –5
t12 5000 10000 ns
t13, t14 0 50 ns
t15, t16 900 1000 ns

Note 1

Note 2

+50 – ns
+50 ns

Notes 1. MIN. of t10 shows that the φRB and φCLB overlap each other.

µ

PD3729

2. MIN. of t11 shows that the φ1L and φCLB overlap each other.

φ

1, φ2 cross points

φ

1

φ

RB

φ

CLB

φ

φ

1L

CLB

90 %

90 %

t10

90 %

t11

90 %

φ

1L, φ2 cross points

φ

2

2 V or more 2 V or more

2

φ

1L

φ

2 V or more 0.5 V or more

Remark Adjust cross points (φ1, φ2) and (φ1L, φ2) with input resistance of each pin.

9

DEFINITIONS OF CHARACTERISTIC ITEMS

1. Saturation voltage: Vsat
Output signal voltage at which the response linearity is lost.

2. Saturation exposure: SE
Product of intensity of illumination (I

3. Photo response non-uniformity: PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.

X) and storage time (s) when saturation of output voltage occurs.

µ

PD3729

PRNU (%) =

4. Average dark signal: ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.

ADS (mV) =

∆x

× 100

x

∆x : maximum of x

x =
x

V

OUT

Register Dark

DC level

5000

d

j

Σ

j=1

5000

d

j

− x 

5000

x

j

Σ

j=1

5000

j

: Output voltage of valid pixel number j

∆x

j

: Dark signal of valid pixel number j

x

10

µ

PD3729

5. Dark signal non-uniformity: DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.

DSNU (mV) : maximum of d

− ADS 

j = 1 to 5000

j

dj : Dark signal of valid pixel number j

V

OUT

ADS

Register Dark

DC level

DSNU

6. Output impedance: Z

O

Impedance of the output pins viewed from outside.

7. Response: R
Output voltage divided by exposure (Ix

•s).

Note that the response varies with a light source (spectral characteristic).

8. Image lag: IL
The rate between the last output voltage and the next one after read out the data of a line.

φ

TG

Light

V

OUT

ON OFF

V

OUT

V1
IL (%) = ×100

V

OUT

V

1

11

9. Register imbalance: RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average
output voltage of all the valid pixels.

n
2

2

(V2j – 1 – V2j)

∑

n

RI (%) =

j = 1

1

∑

n

j = 1

n

×100

V j

n : Number of valid pixels

j : Output voltage of each pixel

V

10. Random noise: σ
Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines)
data sampling at dark (light shielding).

µ

PD3729

100

(Vi – V)

σ (mV) = , V =

Σ

i=1

2

100

i: A valid pixel output signal among all of the valid pixels for each color

V

OUT

1

100

100

Σ

i=1

Vi

V

1

V

2

…

V

100

line 1V

line 2

…

line 100

This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).

12

STANDARD CHARACTERISTIC CURVES

DARK OUTPUT TEMPERATURE

CHARACTERISTIC

8

4

2

1

0.5

Relative Output Voltage

0.25

STORAGE TIME OUTPUT VOLTAGE

CHARACTERISTIC (T

2

1

Relative Output Voltage

0.2

µ

A = +25 °C)

PD3729

0.1
100 20304050

Operating Ambient Temperature T

100

80

60

40

Response Ratio (%)

20

B

0.1
1510

A(°C) Storage Time (ms)

TOTAL SPECTRAL RESPONSE CHARACTERISTICS

(without infrared cut filter) (T

G

A

= +25 °C)

R

G

B

0

400 500 600 700 800

Wavelength (nm)

13

APPLICATION CIRCUIT EXAMPLE

µ

PD3729

+5 V

+

µ

φ

RB

φ

1

φ

2

TG

+12 V

10 Ω

+

PD3729

µ

0.1 F 47 F/25 V

µ

µ

0.1 F10 F/16 V
24

OUT

3

V

23

V

OUT

1

22

V

OUT

2

21

GND

20

CLB

19

1L

18

NC

17

NC

16

φ

2

15

φ

1

14

TG1

13

TG2

B3

B1

B2

47 Ω

47 Ω

2 Ω

2 Ω

2 Ω

2 Ω

47 Ω

2 Ω

2 Ω

2 Ω

B4

B6

B5

1

OUT

4

V

2

V

OUT

6

3

V

OUT

5

4

GND

5

V

OD

6

φφ

RB

7

NC

8

NC

9

φ

1

10

φ

2

11

φφ

TG3

12

GND

φ

φ

φ

µ

0.1 F 10 F/16 V

µµ

+

+5 V

CLB

φ

φ

1L

Remark The inverters shown in the above application circuit example are the 74AC04.

B1 to B6 EQUIVALENT CIRCUIT

4.7 kΩ

CCD
V

OUT

47 Ω

2SA1005

110 Ω

+12 V

2SC945

47 F/25 V

µ

+

µ

0.1 F

1 kΩ

14

PACKAGE DRAWING

CCD LINEAR IMAGE SENSOR 24-PIN CERAMIC DIP (400mil)

(Unit : mm)

68.0±0.4

10.03±0.15

1

10.6±0.6
The 1st valid pixel

9.4±0.7

2

µ

PD3729

0.46±0.05

27.94

10.16

1.27±0.05

2.54

(4.33) (2.33)

3.50±0.5

0.97±0.3

3.30±0.32

3

2.0±0.3

0.25±0.05

4

Name Dimensions Refractive index

Glass cap 67.0 × 8.5 × 1.0 1.5

1 The 1st valid pixel The edge of the package
2 The 1st valid pixel The center of the pin1
3 The surface of the chip The top of the glass cap (Reference)
4 The bottom of the package The surface of the chip

24D-1CCD-PKG1-1

15

RECOMMENDED SOLDERING CONDITIONS

When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure

to consult with our sales offices.

For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E).

Type of Through-hole Device

µ

PD3729D: CCD linear image sensor 24-pin ceramic DIP (400 mil)

Process Conditions

Partial heating method Pin temperature: 300 °C or below,

Heat time: 3 seconds or less (per pin)

µ

PD3729

16

[MEMO]

µ

PD3729

17

[MEMO]

µ

PD3729

18

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.

µ

PD3729

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered
to have a possibility of being an output pin. All handling related to the unused
pins must be judged device by device and related specifications governing the
devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee out­pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately
after power-on for devices having reset function.

19

µ

PD3729

[MEMO]

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5