Datasheet UPD3720ACY Datasheet (NEC)

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD3720A

2700 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR

The µPD3720A is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to

electrical signal and has the function of color separation.

µ

PD3720A has 3 rows of 2700 pixels and 3 pairs of 2 rows of 1350-bit charge transferred registers, reset feed-

The through level clamp circuits, clamp pulse generation circuit and voltage amplifiers. It is suitable for color image scanners, color facsimiles and so on.

FEATURES

• Valid photocell : 2700 pixels × 3

µ

• Photocell's pitch : 10.5

• Line spacing : 42 µm (4 lines) Red line-Green line, Green line-Blue line

• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)

• Resolution : 12 dot/mm A4 (210 × 297 mm) size (shorter side)

• Drive clock level : CMOS output under 5 V operation

• Data rate : 3 MHz MAX.

• Power supply : +12 V

• On-chip circuits : Reset feed-through level clamp circuits

• Pin assign : Compatible with the

m

300 dpi US letter (8.5” × 11”) size (shorter side)

Clamp pulse generation circuit Voltage amplifiers

µ

PD3720

ORDERING INFORMATION

Part Number Package

µ

PD3720ACY CCD linear image sensor 22-pin plastic DIP (400 mil)

Document No. S12035EJ1V0DS00(1st edition) Date published November 1996 N Printed in Japan

The information in this document is subject to change without notice.

©

1996

COMPARISON CHART

µ

PD3720A

PIN CONFIGURATION Pin 11 Analog ground Digital ground ELECTRICAL Output fall delay time 70 80

CHARACTERISTICS TYP. (ns) TIMING CHART Output signal waveform Spike noise reduced –

BLOCK DIAGRAM

V

19 2 11 17

OUT

1

V (B)

21

Item

OD

AGND AGND 2L

φ

........

D14

µ

PD3720A

CCD analog shift register

Transfer gate

Photocell

S1

S2

D64

Transfer gate

CCD analog shift register

S2699

S2700

D65

D66

µ

PD3720

D67

14

φ

1

13

φ

TG1

V (G)

V (R)

OUT

CCD analog shift register

Transfer gate

2

22

Clamp pulse generator

3

1

3

φ

RB

4

φ

1L

........

D14

........

D14

Photocell

S1

S2

D64

Transfer gate

CCD analog shift register

Transfer gate

Photocell

S1

S2

D64

Transfer gate

CCD analog shift register

S2699

S2700

S2699

S2700

D65

D66

D67

12

φ

TG2

10

φ

TG3

9

φ

2

PIN CONFIGURATION (Top View)

CCD linear image sensor 22-pin plastic DIP(400 mil)

µ

PD3720A

Output signal 3 (RED)

Analog ground

Reset gate clock

Last stage shift register clock 1

No connection

Shift register clock 2

V

OUT

AGND

φ

RB

φ

1L

NC

φ

V

NC

V

NC

φ

NC

φ

OUT

OD

2L

1

3

1

2

1

3

4

5

6

R

G

B

7

8

9

2

22

21

20

19

18

17

16

15

14

Output signal 2 (GREEN)

2

1

Output signal 1 (BLUE)

No connection

Output drain voltage

No connection

Last stage shift register clock 2

No connection

Shift register clock 1

φ

Transfer gate clock 3

Analog ground

TG3

AGND

10

11

PHOTOCELL STRUCTURE DIAGRAM

2700

7.5 m

µ

Aluminum shield

2700

µ

10.5 m

13

12

µ

3

m

φ

TG1

φ

TG2

Channel stopper

Transfer gate clock 1

Transfer gate clock 2

3

ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)

Parameter Symbol Ratings Unit

Output drain voltage VOD –0.3 to +15 V

µ

PD3720A

Shift register clock voltage V Reset gate clock voltage V Transfer gate clock voltage V

φ

1, Vφ2, Vφ1L, Vφ2L –0.3 to +15 V

φ

RB –0.3 to +15 V

φ

TG1

– V

φ

TG3 –0.3 to +15 V

Operating ambient temperature TA –25 to +60 °C Storage temperature Tstg –40 to +70 °C

Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;

exceeding the ratings could cause permanent damage. The parameters apply independently.

RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)

Parameter Symbol MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock signal high level V Shift register clock signal low level V Reset gate clock high level V Reset gate clock low level V Transfer gate clock high level V Transfer gate clock low level V Data rate f

φ

1H, Vφ2H, Vφ1LH, Vφ2LH 4.5 5.0 5.5 V

φ

1L, Vφ2L, Vφ1LL, Vφ2LL –0.3 0 +0.5 V

φ

RBH 4.5 5.0 5.5 V

φ

RBL –0.3 0 +0.5 V

φ

TG1H

– V

φ

TG3H 4.5 5.0 5.5 V

φ

TG1L

– V

φ

TG3L –0.3 0 +0.5 V

φ

RB – 1 3 MHz

4

ELECTRICAL CHARACTERISTICS

µ

PD3720A

TA = +25 °C, VOD = 12 V, f

φ

RB = 1 MHz, data rate = 1 MHz, storage time = 5 ms,

light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Saturation voltage Vsat 2.0 3.0 – V Saturation exposure Red SER 0.15 lx•s

Green SEG 0.16 lx•s

Blue SEB 0.27 lx•s Photo response non-uniformity PRNU VOUT = 1 V 6 20 % Average dark signal ADS Light shielding 0.5 2.5 mV Dark signal non-uniformity DSNU Light shielding 1.5 8.0 mV Power consumption PW 400 600 mW Output impedance ZO 0.5 1 kΩ Response Red RR 14.14 20.20 26.26 V/lx•s

Green RG 12.95 18.50 24.05 V/lx•s

Blue RB 7.77 11.10 14.43 V/lx•s Image lag IL VOUT = 1 V 2 10 % Offset level Output fall delay time

Note1

Note2

VOS 3 4.5 6.6 V td VOUT = 1 V 70 ns

Total transfer efficiency TTE VOUT = 1 V, 92 98 %

data rate = 3 MHz

Register imbalance RI VOUT = 1 V 0 1.0 4.0 % Response peak Red 630 nm

Green 540 nm

Blue 460 nm Dynamic range DR1 Vsat /DSNU 2000 times

DR2 Vsat /σ 3000 times Reset feed-through noise Random noise σ Light shielding – 1.0 – mV

Note1

RFTN Light shielding –1000 –300 +300 mV

Notes 1. Refer to TIMING CHART2.

2. When each fall delay time of

φ

1L and φ2L (t2´, t1´) is the TYP. value (refer to TIMING CHART 2).

5

INPUT PIN CAPACITANCE

Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit

µ

PD3720A

Transfer gate clock pin capacitance C

Reset gate clock pin capacitance C Last stage shift register clock pin capacitance C

Shift register clock pin capacitance 1 C Shift register clock pin capacitance 2 C

φ

TG

φ

RB

φ

L

φ

1

φ

2

φ

TG1 13 200 pF

φ

TG2 12 200 pF

φ

TG3 10 200 pF

φ

RB 3 50 pF

φ

1L 4 30 pF

φ

2L 17 30 pF

φ

1 14 700 pF

φ

2 9 700 pF

6

φ

TG1 to TG3

TIMING CHART 1 (for each color)

1

2

3

4

5

φ

1

φ

2

φ

1L

φ

2L

φ

RB

6

µ

PD3720A

7

8

V

OUT

1 to V

OUT

123456789101112131415

3

16

6162636465

66

2763

2764

2765

2766

2767

2768

2769

Valid photocell

Optical black (49 pixels)

(2700 pixels)

Invalid photocell (2 pixels) Invalid photocell (3 pixels)

TIMING CHART 2 (for each color)

t1 t2

φ

1

φ

2

φ

1L

φ

2L

t6t3t5

90 %

10 %

90 %

10 % 90 %

10 %

90 %

10 %

t4 t

t1'

d

t2'

φ

RB

90 %

10 %

+

RFTN

90 %

V

OUT

RFTN

−

10 %

V

OS

7

φ

TG1 to φTG3, φ1, φ2 TIMING CHART

µ

PD3720A

φ

TG

φ

1

φ

2

t7

90 % 10 %

t9

90 %

Symbol MIN. TYP. MAX. Unit t1, t2 0 50 – ns t1´, t2´ 0 5 – ns t4 130 300 – ns t3 20 150 – ns t5, t6 0 50 – ns t7, t8 0 50 – ns t9, t11 900 1000 – ns t10 3000 10000 – ns

t10

t8

t11

φφ

1, 2 cross points

φ

1

φ

2

φφ

1, 2L cross points

φ

1

φ

2L

2 V or more 2 V or more

2 V or more

0.5 V or more

φφ

1L, 2 cross points

φ

2

φ

1L

2 V or more

Remark Adjust cross points (φ1, φ2), (φ1L, φ2) and (φ1, φ2L) with input resistance of each pin.

8

0.5 V or more

µ

PD3720A

DEFINITIONS OF CHARACTERISTIC ITEMS

1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost.

2. Saturation exposure: SE Product of intensity of illumination (I

3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.

X) and storage time(s) when saturation of output voltage occurs.

PRNU (%) =

4. Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.

∆x

× 100

x

V

OUT

Register Dark

DC level

j

∆x : maximum of x

2700

x

j

Σ

j=1

x =

2700

j

: Output voltage of valid pixel number j

x

− x 

∆x

x

ADS (mV) =

2700

Σ

j=1

2700

dj

j : Dark signal of valid pixel number j

d

9

5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula.

µ

PD3720A

DSNU (mV): maximum of | d

j – ADS | j = 1 to 2700

dj: Dark signal of valid pixel number j

V

OUT

Register Dark

DC level

6. Output impedance: Z

O

Impedance of the output pins viewed from outside.

7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source (spectral characteristic).

8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line.

ADS

DSNU

φ

TG

Light

V

OUT

IL (%) = ×100

V

V1

OUT

ON OFF

V

OUT

V

1

10

µ

j

PD3720A

9. Register Imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.

n 2

2

(V

2j – 1

Σ

n

RI (%) =

10. Random noise: σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding).

j=1

– V2j)

n

1

V

j

Σ

n

=1

× 100

n : Number of valid pixels

j : Output voltage of each pixel

V

100

(Vi – V)

σ = , V =

This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).

Σ

i=1

100

2

OUT

100

1

V

i

Σ

100

i=1

i : A valid pixel output signal among all of the valid pixels for each color

V

1

V

2

…

V

100

line 1V

line 2

…

line 100

11

STANDARD CHARACTERISTIC CURVES (TA = +25 °C)

DARK OUTPUT TEMPERATURE

CHARACTERISTIC

8

4

2

1

0.5

Relative Output Voltage

0.25

STORAGE TIME OUTPUT VOLTAGE

2

1

Relative Output Voltage

0.2

CHARACTERISTIC

µ

PD3720A

0.1

100

80

60

40

Response Ratio (%)

20

100 20304050

Operating Ambient Temperature T

TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter)

B

0.1 1510

A

(°C) Storage Time (ms)

R

G

B

12

0

600500400

Wavelength (nm)

700 800

APPLICATION CIRCUIT EXAMPLE

B3

µ

PD3720A

+12 V

10 Ω

+

-

1

OUT

3

V

22

OUT

2

V

B2

µ

0.1 Fµ47 F/25 V

2

AGND

φ

RB

φ

2

47 Ω

10 Ω

10

11

3

4

5

6

7

8

9

φ

RB

φ

1L

NC

φ

2

φ

TG3

AGND

V

φ

OUT

NC

V

NC

φ

2L

NC

TG1

TG2

21

1

OD

φ

1

20

19

18

17

16

15

14

13

12

B1

47 Ω

10 Ω

φ

1

φ

TG

B1 to B3 EQUIVALENT CIRCUIT

12 V

+

100 Ω

CCD V

Remark Inverters : PD74HC04

100 Ω

OUT

2SC945

2 kΩ

µ

47 F/25 V

13

PACKAGE DRAWING

CCD LINEAR IMAGE SENSOR 22PIN PLASTIC DIP (400 mil)

(Unit : mm)

1bit

0.5±0.3

2.0

9.25±0.3

37.5

44.0±0.3

µ

PD3720A

1.02±0.15

0.46±0.1

25.4

2.54

10.16

(1.79)

2.55±0.2

(5.42)

4.21±0.5

4.39±0.4

0 ∼ 10°

Name Dimensions

Plastic cap

1 The bottom of the package The surface of the chip 2 The thickness of the cap over the chip

42.9 × 8.35 × 0.7

2

0.25±0.05

Refractive index

1.5

1

14

22C-1CCD-PKG6

µ

PD3720A

RECOMMENDED SOLDERING CONDITIONS

When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure

to consult with our sales offices.

For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E).

Type of Through-hole Device

µ

PD3720ACY: CCD linear image sensor 22-pin plastic DIP (400 mil)

Process

Wave soldering (only to leads)

Partial heating method

Caution For through-hole device, the wave soldering process must be applied only to leads, and make

sure that the package body dose not get jet soldered. During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact.

Solder temperature: 260 ˚C or below, Flow time: 10 seconds or less.

Pin temperature: 260 ˚C or below, Heat time: 10 seconds or less (per each lead).

Conditions

15

NOTES ON CLEANING THE PLASTIC CAP

1 CLEANING THE PLASTIC CAP

Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning.

We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used.

2 RECOMMENDED SOLVENTS

µ

PD3720A

The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent.

Solvents Symbol

Ethyl Alcohol EtOH Methyl Alcohol MeOH Isopropyl Alcohol IPA N-methyl Pyrrolidone NMP

16

[MEMO]

µ

PD3720A

17

[MEMO]

µ

PD3720A

18

µ

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

PD3720A

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

19

µ

PD3720A

[MEMO]

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.

M4 96.5