Page 1
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3719
10600 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
The µPD3719 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
µ
PD3719 has 3 rows of 10600 pixels, and each row has a single-sided readout type of charge transfer register.
The
It has reset feed-through level clamp circuits and voltage amplifiers. Moreover, a large dynamic range is realized
by using a large saturation voltage and a low-noise amplifier. Therefore, it is suitable for 1200 dpi/A4 professional
color image scanners and so on.
FEATURES
• Valid photocell : 10600 pixels × 3
• Photocell's pitch : 7 µm
µ
• Line spacing : 70
• Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
• Resolution : 48 dot/mm A4 (210 × 297 mm) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate : 2 MHz MAX.
• Power supply : +15 V
• On-chip circuits : Reset feed-through level clamp circuits
ORDERING INFORMATION
Part Number Package
µ
PD3719D CCD linear image sensor 36-pin ceramic DIP (600 mil)
m (10 lines) Red line-Green line, Green line-Blue line
1200 dpi US letter (8.5” × 11”) size (shorter side)
Voltage amplifiers
Document No. S13492EJ1V0DS00(1st edition)
Date published September 1998 N CP(K)
Printed in Japan
The information in this document is subject to change without notice.
©
1998
Page 2
BLOCK DIAGRAM
φ
CLB
31
V
OUT
1
33
(Blue)
V
OUT
2
V
OUT
(Red)
35
3
2
(Green)
µ
PD3719
φ
φ
2
34
GND
32
GND
15
D14
D14
D14
······
······
······
S1
D64
Transfer gate
CCD analog shift register
S1
D64
Transfer gate
CCD analog shift register
S1
D64
Transfer gate
CCD analog shift register
Photocell
S2
(Blue)
Photocell
S2
(Green)
Photocell
S2
(Red)
S10599
S10600
S10599
S10600
S10599
S10600
D65
D65
D65
D66
D66
D66
D67
D67
D67
GNDGND
3
25 24
1
22
GND
φ
TG
23
GND
21
GND
14
4
5 6
φ
V
RB
OD
V
RD
1312
φ
φ
2
1
2
Page 3
PIN CONFIGURATION (Top View)
CCD linear image sensor 36-pin ceramic DIP (600 mil)
µ
PD3719
No connection
Output signal 3 (Red)
Ground
Output drain voltage
Reset gate clock
Reset drain voltage
No connection
No connection
No connection
V
OUT
GND
V
φ
V
NC
RB
NC
NC
NC
36
35
34
33
32
31
30
29
28
NC
V
OUT
GND
V
OUT
GND
φ
CLB
NC
NC
NC
1
3
2
1
1
Green
1
Blue
3
4
OD
5
6
RD
7
8
9
Red
No connection
Output signal 2 (Green)
2
Ground
1
Output signal 1 (Blue)
Ground
Reset feed-through level
clamp clock
No connection
No connection
No connection
No connection
No connection
Shift register clock 2
Shift register clock 1
Ground
Ground
No connection
No connection
No connection
NC
NC
φ
φ
GND
GND
NC
NC
NC
27
26
25
24
23
22
21
20
19
NC
NC
φ
φ
φ
GND
GND
NC
NC
10
11
12
2
1
13
14
15
16
10600
10600
10600
17
18
2
1
TG
No connection
No connection
Shift register clock 2
Shift register clock 1
Transfer gate clock
Ground
Ground
No connection
No connection
3
Page 4
µ
PD3719
PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
7 m
µ
Blue photocell array
4 m
µ
Aluminum
shield
µ
7 m
3
m
µ
Channel stopper
7 m
µ
7 m
µ
Green photocell array
Red photocell array
10 lines
(70 m)
µ
10 lines
(70 m)
µ
4
Page 5
µ
PD3719
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
Parameter Symbol Ratings Unit
Output drain voltage VOD –0.3 to +16 V
Reset drain voltage VRD –0.3 to +16 V
Shift register clock voltage V
Reset gate clock voltage V
Reset feed-through level clamp clock voltage V
Transfer gate clock voltage V
φ
1, Vφ2 –0.3 to +8 V
φ
RB –0.3 to +8 V
φ
CLB –0.3 to +8 V
φ
TG –0.3 to +8 V
Operating ambient temperature TA –25 to +60 °C
Storage temperature Tstg –40 to +100 °C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)
Parameter Symbol MIN. TYP. MAX. Unit
Output drain voltage VOD 14.0 15.0 16.0 V
Reset drain voltage VRD 14.0 VOD VOD V
Shift register clock high level V
Shift register clock low level V
Reset gate clock high level V
Reset gate clock low level V
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high level V
Transfer gate clock low level V
Data rate f
Note When Transfer gate clock high level (V
φ
1H, Vφ2H 4.5 5.0 5.5 V
φ
1L, Vφ2L –0.3 0 +0.5 V
φ
RBH 4.5 5.0 5.5 V
φ
RBL –0.3 0 +0.5 V
V
φ
CLBH 4.5 5.0 5.5 V
V
φ
CLBL –0.3 0 +0.5 V
φ
TGH 4.5 V
φ
TGL –0.3 0 +0.3 V
φ
RB – 1 2 MHz
φ
TGH) is higher than Shift register clock high level (Vφ1H), Image lag
Note
φ
1H
Note
V
φ
1H
can increase.
V
5
Page 6
ELECTRICAL CHARACTERISTICS
µ
PD3719
TA = +25 °C, VOD = 15 V, VRD = 15 V, data rate (f
φ
RB) = 2 MHz, storage time = 5.5 ms,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Saturation voltage Vsat 4.0 5.0 – V
Saturation exposure Red SER 0.52 lx•s
Green SEG 0.57 lx•s
Blue SEB 0.94 lx•s
Photo response non-uniformity PRNU VOUT = 2.5 V 6 20 %
Average dark signal ADS Light shielding 0.8 3.0 mV
Dark signal non-uniformity DSNU Light shielding 1.5 5.0 mV
Power consumption PW 400 600 mW
Output impedance ZO 0.5 1 kΩ
Response Red RR 6.8 9.7 12.6 V/lx•s
Green RG 6.2 8.8 11.4 V/lx•s
Blue RB 3.8 5.3 6.8 V/lx•s
Image lag IL VOUT = 2.5 V 2.0 5.0 %
Offset level
Output fall delay time
Total transfer efficiency TTE VOUT = 2.5 V 92 98 %
Response peak Red 630 nm
Dynamic range DR1 Vsat /DSNU 3333 times
Reset feed-through noise
Random noise σ Light shielding – 0.5 – mV
Note1
VOS 8.8 10.8 12.8 V
Note2
Green 540 nm
Blue 460 nm
Note1
td VOUT = 2.5 V 70 ns
DR2 Vsat /σ 10000 times
RFTN Light shielding 0 1500 2500 mV
Notes 1. Refer to TIMING CHART 2.
2. When the fall time of
6
φ
1 (t1) is the TYP. value (refer to TIMING CHART 2).
Page 7
INPUT PIN CAPACITANCE (TA = +25 °C, VOD = VRD = 15 V)
Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit
Shift register clock pin capacitance 1 C
Shift register clock pin capacitance 2 C
Reset gate clock pin capacitance C
Reset feed-through level clamp clock pin capacitance
Transfer gate clock pin capacitance C
Remark Pins 13 and 24 (φ1), 12 and 25 (φ2) are each connected inside of the device.
φ
1
φ
1 13 1600 pF
24 1600 pF
φ
2
φ
2 12 1600 pF
25 1600 pF
φ
RB
C
φ
CLB
φ
TG
φ
RB 5 15 pF
φ
CLB 31 15 pF
φ
TG 23 200 pF
µ
PD3719
7
Page 8
8
123456789101112131415
6162636465
66
10663
10664
10665
10666
10667
10668
10669
Note
Note
Optical black
(49 pixels)
Invalid photocell
(2 pixels)
Valid photocell
(10600 pixels)
Invalid photocell
(3 pixels)
TG
φ
1
2
φ
φ
RB
φ
V
OUT
1 to
φ
CLB
V
OUT
3
TIMING CHART 1 (for each color)
Note Input the
φ
RB and
φ
CLB pulses continuously during this period, too.
µ
PD3719
Page 9
φ
V
OUT
1 to
V
OUT
3
CLB
φ
RB
φ
2
φ
1
90 %
10 %
90 %
10 %
90 %
10 %
90 %
10 %
RFTN
V
OS
t2t1
t4
t6
t3
t5
t10
t8
t7
t9
t11
t
d
TIMING CHART 2 (for each color)
10 %
µ
PD3719
9
Page 10
φ
TG, φ1, φ2 TIMING CHART
µ
PD3719
t12
90 %
TG
φ
φ
1
φ
2
10 %
t15
90 %
Symbol MIN. TYP. MAX. Unit
t1, t2 0 25 — ns
t3 30 50 — ns
t4 70 150 — ns
t5, t6 0 25 — ns
t7 30 75 — ns
t8, t9 0 25 — ns
t10 10 20 — ns
t11 5 10 — ns
t12, t13 0 50 — ns
t14 3000 10000 — ns
t15, t16 900 1000 — ns
t14
t13
t16
Remark TYP. is an example of at 1 MHz data rate (f
φ
1, φ2 cross points
φ
1
φ
2
2 V or more
φ
RB) operation.
Remark Adjust cross points of φ1 and φ2 with input resistance of each pin.
10
2 V or more
Page 11
µ
PD3719
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure: SE
Product of intensity of illumination (I
3. Photo response non-uniformity: PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
X) and storage time (s) when saturation of output voltage occurs.
PRNU (%) =
∆x
× 100
x
∆x : maximum of x
x =
x
V
OUT
Register Dark
DC level
j − x
10600
xj
Σ
j=1
10600
j : Output voltage of valid pixel number j
∆x
x
4. Average dark signal: ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
10600
dj
Σ
ADS (mV) =
j=1
10600
j : Dark signal of valid pixel number j
d
5. Dark signal non-uniformity: DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of d
− ADS
j = 1 to 10600
j
dj : Dark signal of valid pixel number j
V
OUT
ADS
Register Dark
DC level
DSNU
11
Page 12
6. Output impedance: ZO
Impedance of the output pins viewed from outside.
7. Response: R
Output voltage divided by exposure (Ix•s).
Note that the response varies with a light source (spectral characteristic).
8. Image Lag: IL
The rate between the last output voltage and the next one after read out the data of a line.
φ
TG
µ
PD3719
Light
V
OUT
ON OFF
V
OUT
V
1
V1
IL (%) = ×100
V
OUT
9. Random noise: σ
Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines)
data sampling at dark (light shielding).
100
(Vi – V)
σ (mV) = , V =
Σ
i=1
2
100
i: A valid pixel output signal among all of the valid pixels for each color
V
OUT
1
100
100
Σ
i=1
V
i
V
1
V
2
…
line 1V
line 2
…
V
100
line 100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
12
Page 13
STANDARD CHARACTERISTIC CURVES
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
8
4
2
1
0.5
Relative Output Voltage
0.25
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
2
1
Relative Output Voltage
0.2
µ
A
= +25 °C)
PD3719
0.1
100 20304050
Operating Ambient Temperature T
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
100
80
60
40
Response Ratio (%)
20
B
0.1
1510
A
(°C) Storage Time (ms)
A
(without infrared cut filter) (T
R
G
= +25 °C)
G
0
400
500 600
Wavelength (nm)
B
700 800
13
Page 14
APPLICATION CIRCUIT EXAMPLE
µ
PD3719
+5 V
µ
F/16 V 0.1µF
10
φ
RB
2
φ
+15 V
10 Ω
47
+
µ
F/25 V0.1µF
+5 V
+
10µF/16 V0.1µF
φ
CLB
φ
1
φ
TG
+
B3 B2
47 Ω
+
47
µ
F/25 V
4.7 Ω
4.7 Ω
µ
1
NC NC
2
V
OUT
3
GND
4
OD
V
5
φ
RB
6
RD
V
7
NC
8
NC
9
NC
10
NC NC
11
NC
12
φ
2
13
φ
1
14
GND
15
GND
16
NC
17
NC
18
NC
PD3719
3
V
GND
V
GND
φ
GND
GND
OUT
OUT
CLB
NC
NC
NC
NC
φ
TG
NC
NC
36
35
2
34
33
1
B1
32
31
47 Ω
30
29
28
27
26
25
φ
2
24
φ
1
23
4.7 Ω
4.7 Ω
4.7 Ω
22
21
20
19
Remark The inverters shown in the above application circuit example are the 74HC04.
B1 to B3 EQUIVALENT CIRCUIT
15 V
+
µ
47 F/25 V
CCD
V
OUT
100 Ω
100 Ω
2SC945
2 kΩ
14
Page 15
PACKAGE DRAWING
Name Dimensions Refractive index
Glass cap 93.0 × 13.6 × 1.0 1.5
1 The 1st valid pixel The center of the pin1
2 The 1st valid pixel The center of the package
3 The surface of the chip The top of the glass cap (Reference)
4 The bottom of the package The surface of the chip
36D-1CCD-PKG-1
CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (600mil)
The 1st valid pixel
2.54
20.32
15.24
94.00±0.50
0.46±0.05
1.27±0.05 (4.33)
3.50±0.5
2.0±0.3
4
0.25±0.05
0.97±0.3
3.30±0.35
88.9±0.6
14.99±0.3
8.1±0.6
1
36.4±0.6
2
(2.33)
3
(Unit : mm)
µ
PD3719
15
Page 16
µ
PD3719
NOTES ON THE USE OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips to
come off internally. Particular care should be taken when mounting the package on the circuit board.
When mounting the package, use a circuit board which will not subject the package to bending stress, or use a
socket.
Note
For this product, the reference value for the three-point bending strength
however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body
(ceramic).
Note Three-point bending strength test
Distance between supports: 70 mm, Support R: R 2 mm, Loading rate: 0.5 mm / min.
Load Load
is 30 kg. Avoid imposing a load,
70 mm 70 mm
16
Page 17
[MEMO]
µ
PD3719
17
Page 18
[MEMO]
µ
PD3719
18
Page 19
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
µ
PD3719
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered
to have a possibility of being an output pin. All handling related to the unused
pins must be judged device by device and related specifications governing the
devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
19
Page 20
µ
PD3719
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
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