Because this device can be programmed by users, it is ideally suited for system evaluation, small-lot and multiple-
device production, and early development and time-to-market.
µ
PD178P018A is a PROM version corresponding to the µPD178004A, 178006A, and 178016A.
The
Note
is a device in which the internal mask ROM of the µPD178018A is replaced with a one-
NoteUnder development
Caution The µPD178P018AKK-T does not maintain planned reliability when used in your system’s mass-
produced products. Please use only experimentally or for evaluation purposes during trial manufacture.
For more information on functions, refer to the following User’s Manuals. Be sure to read them when
designing.
µ
PD178018A Subseries User’s Manual: To be prepared
78K/0 Series User’s Manual Instruction: U12326E
FEATURES
• Pin-compatible with mask ROM version (except for VPP pin)
• Internal PROM: 60 Kbytes
•µPD178P018AGC : One-time programmable (ideally suited for small-lot production)
•µPD178P018AKK-T: Reprogrammable (ideally suited for system evaluation)
• Internal high-speed RAM: 1 024 bytes
• Internal expansion RAM: 2 048 bytes
• Buffer RAM: 32 bytes
• Can be operated in the same power supply voltage as the mask ROM version
(During PLL operation: VDD = 4.5 to 5.5 V)
The electrical specifications (power supply current, etc.) and PLL analog specifications of the
from that of mask ROM versions. So, these differences should be considered and verified before application sets
are mass-produced.
In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions.
The information in this document is subject to change without notice.
Document No. U12642EJ1V0DS00 (1st Edition)
Date Published July 1997 N
Printed in Japan
80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)One-Time PROMStandard
80-pin ceramic WQFN (14 × 14 mm, 0.65-mm pitch)EPROMNot applicable
µ
PD178P018AGC-3B9
µ
PD178P018AKK-T
NoteUnder planning
Please refer to the Quality grade on NEC Semiconductor Devices (Document number C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
µ
PD178018A SUBSERIES AND µPD178003 SUBSERIES EXPANSION
NoteWhen using the I2C bus mode (including when this mode is implemented by program without using the
peripheral hardware), consult your local NEC sales representative when you place an order for mask.
3
Page 4
ItemFunction
PLL frequencyDivision modeTwo types
synthesizer• Direct division mode (VCOL pin)
• Pulse swallow mode (VCOH and VCOL pins)
Reference frequency7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz)
Charge pumpError out output: 2 (EO0 and EO1 pins
Phase comparatorUnlock detectable by program
Frequency counter• Frequency measurement
• AMIFC pin: for 450-kHz count
• FMIFC pin: for 450-kHz/10.7-MHz count
D/A converter (PWM output)8-/9-bit resolution × 3 channels (shared by 8-bit timer)
Standby function• HALT mode
• STOP mode
Reset• Reset via the RESET pin
• Internal reset by watchdog timer
• Reset by power-ON clear circuit (3-value detection)
• Detection of less than 4.5 V
• Detection of less than 3.5 V
• Detection of less than 2.5 V
Power supply voltage• VDD = 4.5 to 5.5 V (with PLL operating)
•VDD = 3.5 to 5.5 V (with CPU operating, CPU clock: fX/2 or less)
•VDD = 4.5 to 5.5 V (with CPU operating, CPU clock: fX)
Package• 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
• 80-pin ceramic WQFN (14 × 14 mm, 0.65-mm pitch)
Note 2
Note 1
)
Note 2
(CPU clock: fX)
(CPU clock: fX/2 or less and on power application)
Note 2
(in STOP mode)
µ
PD178P018A
(2/2)
Notes 1. The EO1 pin can be set to high impedance for the µPD178P018A.
The following figure shows an application example.
µ
PD178P018A
EO0
EO1
VCOH
VCOL
LPFVCO
LPF : Low path filter
VCO : Voltage controlled oscillator
• To lock to a target frequency at high speed
Setting the EO0 and EO1 pins to error out output improves the output current potential and LPF
voltage control potential.
• Normal state
Setting only the EO0 pin to error out output maintains the LPF stable.
2. These voltage values are maximum values. Reset is actually executed at a voltage lower than these
values.
4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-
DDPLL
FMIFC
V
VCOL
VCOH
EO0
GNDPLL
EO1
PP
V
P50
P51
P52
P53
µ
F capacitor.
5
Page 6
µ
PD178P018A
AMIFC: AM Intermediate Frequency Counter Input
ANI0 to ANI5: A/D Converter Input
BEEP: Buzzer Output
BUSY: Busy Output
EO0, EO1: Error Out Output
FMIFC: FM Intermediate Frequency Counter Input
GND: Ground
GNDPLL: PLL Ground
GNDPORT: Port Ground
INTP0 to INTP6 : Interrupt Inputs
P00 to P06: Port 0
P10 to P15: Port 1
P20 to P27: Port 2
P30 to P37: Port 3
P40 to P47: Port 4
P50 to P57: Port 5
P60 to P67: Port 6
P120 to P125: Port 12
P132 to P134: Port 13
PWM0 to PWM2 : PWM Output
REGCPU: Regulator for CPU Power Supply
REGOSC: Regulator for Oscillator
RESET: Reset Input
SB0, SB1: Serial Data Bus Input/Output
SCK0, SCK1: Serial Clock Input/Output
SCL: Serial Clock Input/Output
SDA0, SDA1: Serial Data Input/Output
SI0, SI1: Serial Data Input
SO0, SO1: Serial Data Output
STB: Strobe Output
TI1, TI2: Timer Clock Input
VCOL, VCOH: Local Oscillation Input
VDD: Power Supply
VDDPLL: PLL Power Supply
VDDPORT: Port Power Supply
VPP: Programming Power Supply
X1, X2: Crystal Resonator Connection
P132 toOutputPort 13. —PWM0 to
P1343-bit output port.PWM2
7-bit input/output port.
6-bit input/output port.
Input/output mode can be specified bit-wise.
8-bit input/output port.
Input/output mode can be specified bit-wise.
8-bit input/output port.
Input/output mode can be specified bit-wise.
8-bit input/output port.
Input/output mode can be specified in 8-bit units.
Test input flag (KRIF) is set to 1 by falling edge detection.
8-bit input/output port.
Input/output mode can be specified bit-wise.
8-bit input/output port.input/output port.
specified bit-wise.
Input/output mode can be specified bit-wise.
N-ch open-drain output port.
Input/output mode can be specified bit-wise.
InputINTP1 to INTP6
Alternate Function
SO1
SCK1
SO0/SB1/SDA1
TI1
TI2
10
Page 11
(2) Non-port pins (1 of 2)
µ
PD178P018A
Pin NameI/OFunctionAfter Reset
INTP0 toInputExternal maskable interrupt inputs with specifiable valid edges (risingInputP00 to P06
INTP6edge, falling edge, both rising and falling edges).
SI0InputSerial interface serial data inputInput
SI1P20
SO0OutputSerial interface serial data outputInput
SO1P21
SB0I/OSerial interface serial data input/outputInputP25/SI0/SDA0
SB1
SDA0P25/SI0/SB0
SDA1P26/SO0/SB1
SCK0I/OSerial interface serial clock input/outputInputP27/SCL
SCK1P22
SCLP27/SCK0
STBOutputSerial interface automatic transmit/receive strobe outputInputP23
BUSYInputSerial interface automatic transmit busy inputInputP24
TI1InputExternal count clock input to 8-bit timer (TM1)InputP33
TI2External count clock input to 8-bit timer (TM2)P34
BEEPOutputBuzzer outputInputP36
ANI0 to ANI5
PWM0 toOutputPWM output—P132 to P134
PWM2
EO0, EO1OutputError out output from charge pump of the PLL frequency synthesizer——
VCOLInputInputs PLL local band oscillation frequency (In HF, MF mode).——
VCOHInputInputs PLL local band oscillation frequency (In VHF mode).——
AMIFCInputInputs AM intermediate frequency counter.——
FMIFCInputInputs FM intermediate frequency counter.——
RESETInputSystem reset input——
X1InputCrystal resonator connection for system clock oscillation——
X2 ———
REGOSC —Regulator for oscillator. Connected to GND via a 0.1-µF capacitor.——
REGCPU —Regulator for CPU power supply. Connected to GND via a 0.1-µF capacitor.——
VDD —Positive power supply——
GND —Ground——
VDDPORT —Positive power supply for port block——
GNDPORT —Ground for port block——
VDDPLL
GNDPLL
InputA/D converter analog inputInputP10 to P15
Note
—Positive power supply for PLL——
Note
—Ground for PLL——
Alternate Function
P25/SB0/SDA0
P26/SB1/SDA1
P26/SO0/SDA1
Note Connect a capacitor of approximately 1 000 pF between VDDPLL pin and GNDPLL pin.
11
Page 12
(2) Non-port pins (2/2)
µ
PD178P018A
Pin NameI/OFunctionAfter Reset
VPP—High-voltage applied during program write/verification.——
Connected directly to GND in normal operating mode.
When +5 V or +12.5 V is applied to VPP pin and a low-level signal is applied to the RESET pin, this
chip is set in the PROM programming mode.
VPPInputPROM programming mode setting and high-voltage applied during program write/verification.
A0 to A16InputAddress bus
D0 to D7I/OData bus
CEInputPROM enable input/program pulse input
OEInputRead strobe input to PROM
PGMInputProgram/program inhibit input in PROM programming mode.
VDD—Positive power supply
GND—Ground potential
12
Page 13
µ
PD178P018A
1.3 Pins Input/Output Circuits and Recommended Connection of Unused Pins
Table 1-1 shows the input/output circuit types of pins and the recommended conditions for unused pins.
Refer to Figure 1-1 for the configuration of the input/output circuit of each type.
Table 1-1. Type of I/O Circuit of Each Pin
Pin NameI/O Circuit TypeI/ORecommended Connections of Unused Pins
P00/INTP02InputConnected to GND or GNDPORT
P01/INTP1 to P06/INTP68I/OSet in general-purpose input port mode by software and
P10/ANI0 to P15/ANI511-A
P20/SI18
P21/SO15
P22/SCK18
P23/STB5
P24/BUSY8
P25/SI0/SB0/SDA010
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30 to P325
P33/TI1, P34/TI28
P355
P36/BEEP
P37
P40 to P475-G
P50 to P575
P60 to P6313-D
P64 to P675
P120 to P125
P132/PWM0 to P134/PWM219OutputSet to the low-level output by software and open
EO0DTS-EO1Open
EO1DTS-EO3
VCOL, VCOHDTS-AMPInputSet to disabled status by software and open
AMIFC, FMIFC
VPP — —Connected to GND or GNDPORT directly
individually connected to VDD, VDDPORT, GND, or GNDPORT
via a resistor.
13
Page 14
Figure 1-1. Types of Pin Input/Output Circuits (1/2)
Type 2Type 8
data
IN
output
disable
Schmitt-Triggered Input with Hysteresis Characteristics
V
DD
P-ch
N-ch
µ
PD178P018A
IN/OUT
Type 5
data
V
DD
P-ch
Type 10
IN/OUT
output
disable
N-ch
open-drain
output disable
input
enable
Type 5-GType 11-A
V
data
output
disable
DD
P-ch
IN/OUT
N-ch
data
output
disable
comparator
input
enable
data
P-ch
+
–
N-ch
V
REF (Threshold voltage)
V
DD
P-ch
N-ch
V
P-ch
N-ch
IN/OUT
DD
IN/OUT
Remark All V
14
DD and GND in the above figures are the positive power supply and ground potential of the ports,
and should be read as VDDPORT and GNDPORT, respectively.
Page 15
Figure 1-1. Types of Pin Input/Output Circuits (2/2)
Type 13-DType DTS-EO3
µ
PD178P018A
output disable
data
Type 19
N-ch
VDD
RD
Middle-Voltage Input Buffer
N-ch
P-ch
OUT
IN/OUT
Type DTS-AMP
IN
DW
UP
DDPLL
V
P-ch
OUT
N-ch
GNDPLL
VDDPLL
Type DTS-EO1
DDPLL
V
DW
UP
P-ch
OUT
N-ch
GNDPLL
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports,
and should be read as VDDPORT and GNDPORT, respectively.
15
Page 16
µ
PD178P018A
2. PROM PROGRAMMING
The µPD178P018A has an internal 60-Kbyte PROM as a program memory. For programming, set the PROM
programming mode with the VPP and RESET pins. For the connection of unused pins, refer to “PIN CONFIGURA-
TIONS (TOP VIEW) (2) PROM programming mode.”
Caution Programs must be written in addresses 0000H to EFFFH (the last address EFFFH must be
specified). They cannot be written by a PROM writer which cannot specify the write address.
2.1 Operating Modes
When +5 V or +12.5 V is applied to the V
PP pin and a low-level signal is applied to the RESET pin, the PROM
programming mode is set. This mode will become the operating mode as shown in Table 2-1 when the CE, OE, and
PGM pins are set as shown.
Further, when the read mode is set, it is possible to read the contents of the PROM.
Table 2-1. Operating Modes of PROM Programming
PinRESETVPPVDDCEOEPGMD0 to D7
Operating Mode
Page data latchL+12.5 V+6.5 VHLHData input
Page writeHHLHigh-impedance
Byte writeLHLData input
Program verifyLLHData output
Program inhibit×HHHigh-impedance
Data output becomes high-impedance, and is in the output disable mode, if OE = H is set.
Therefore, it allows data to be read from any device by controlling the OE pin, if multiple µPD178P018As are
connected to the data bus.
(3) Standby mode
Standby mode is set if CE = H is set.
In this mode, data outputs become high-impedance irrespective of the OE status.
(4) Page data latch mode
Page data latch mode is set if CE = H, PGM = H, and OE = L are set at the beginning of page write mode.
In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit.
(5) Page write mode
After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed
by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H and OE = H. Then, program
verification can be performed, if CE = L and OE = L are set.
If programming is not performed by a one-time program pulse, X times (X ≤ 10) write and verification operations
should be executed repeatedly.
(6) Byte write mode
Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L and OE
= H. Then, program verification can be performed if OE = L is set.
If programming is not performed by a one-time program pulse, X times (X ≤ 10) write and verification operations
should be executed repeatedly.
(7) Program verify mode
Program verify mode is set if CE = L, PGM = H, and OE = L are set.
In this mode, check if a write operation is performed correctly after the write.
(8) Program inhibit mode
Program inhibit mode is used when the OE pin, V
connected in parallel and a write is performed to one of those devices.
When a write operation is performed, the page write mode or byte write mode described above is used. At this
time, a write is not performed to a device which has the PGM pin driven high.
PP pin, and D0 to D7 pins of multiple
µ
PD178P018As are
17
Page 18
2.2 PROM Write Procedure
Figure 2-1. Page Program Mode Flow Chart
Start
Address = G
V
DD = 6.5 V, VPP = 12.5 V
X = 0
Latch
Address = Address + 1
Latch
µ
PD178P018A
Address = Address + 1
Address = Address + 1
Latch
Address = Address + 1
Latch
X = X + 1
0.1-ms Program Pulse
Verify
4 bytes
No
Address = N?
V
DD = 4.5 to 5.5 V, VPP = VDD
Pass
Yes
Fail
No
X = 10?
Yes
Remark G = Start address
N = Program last address
18
Pass
Verify
All Bytes
All Pass
Write EndDefective Product
Fail
Page 19
A2 to A16
A0, A1
D0 to D7
VPP
V
PP
VDD
Figure 2-2. Page Program Mode Timing
Page Data LatchProgram VerifyPage Program
Data InputData Output
µ
PD178P018A
VDD
CE
PGM
OE
VDD + 1.5
V
DD
IH
V
VIL
IH
V
VIL
IH
V
VIL
19
Page 20
Figure 2-3. Byte Program Mode Flow Chart
Start
Address = G
DD = 6.5 V, VPP = 12.5 V
V
X = 0
µ
PD178P018A
Address = Address + 1
X = X + 1
0.1-ms Program Pulse
No
Pass
Address = N?
DD = 4.5 to 5.5 V, VPP = VDD
V
All Bytes
Write EndDefective Product
Vefity
Verify
Pass
Yes
All Pass
Fail
Fail
No
X = 10?
Yes
Remark G = Start address
N = Program last address
20
Page 21
Figure 2-4. Byte Program Mode Timing
ProgramProgram Verify
A0 to A16
D0 to D7Data InputData Output
VPP
PP
V
VDD
VDD + 1.5
VDD
V
DD
µ
PD178P018A
V
IH
CE
VIL
IH
V
PGM
VIL
IH
V
OE
VIL
Cautions 1. VDD should be applied before VPP, and removed after VPP.
2. VPP must not exceed +13.5 V including overshoot.
3. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being
applied to VPP.
21
Page 22
µ
PD178P018A
2.3 PROM Read Procedure
The contents of PROM are readable to the external data bus (D0 to D7) according to the read procedure shown
below.
(1) Fix the RESET pin at low level, supply +5 V to the V
(2) Supply +5 V to the V
(3) Input address of read data into the A0 to A16 pins.
(4) Read mode
(5) Output data to D0 to D7 pins.
The timings of the above steps (2) to (5) are shown in Figure 2-5.
DD and VPP pins.
PP pin, and connect all other unused pins as shown in
Figure 2-5. PROM Read Timings
Address InputA0 to A16
CE (Input)
OE (Input)
Hi-ZHi-Z
Data OutputD0 to D7
22
Page 23
µ
PD178P018A
3. PROGRAM ERASURE (µPD178P018AKK-T ONLY)
The µPD178P018AKK-T is capable of erasing (FFH) the data written in a program memory and rewriting.
To erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400
nm. Normally, irradiate ultraviolet rays of 254-nm wavelength. The amount of exposure required to completely erase
the programmed data is as follows:
2
• UV intensity x erasure time: 30 W•s/cm
• Erasure time: 40 min. or more (When a UV lamp of 12 000 µW/cm2 is used. However, a longer time may be
needed because of deterioration in performance of the UV lamp, soiled erasure window, etc.)
When erasing the contents of the data, set up the UV lamp within 2.5 cm from the erasure window. Further, if a
filter is provided for a UV lamp, irradiate the ultraviolet rays after removing the filter.
or more
4. OPAQUE FILM ON ERASURE WINDOW (µPD178P018AKK-T ONLY)
To protect from an intentional erasure by rays other than that of the lamp for erasing EPROM contents, or to protect
internal circuit other than EPROM from misoperating by rays, cover the erasure window with an opaque film when
EPROM contents erasure is not performed.
5. ONE-TIME PROM VERSION SCREENING
The one-time PROM version (µPD178P018AGC-3B9) cannot be tested completely by NEC before it is shipped,
because of its structure. It is recommended to perform screening to verify PROM after writing necessary data and
performing high-temperature storage under the condition below.
Storage TemperatureStorage Time
125 °C24 hours
23
Page 24
µ
PD178P018A
6. ELECTRICAL SPECIFICATIONS (PRELIMINARY)
Caution The following electrical specifications are preliminary values for this product. When designing,
be sure to refer to the data sheet describing the official electrical specifications.
µ
PD178P018A Data Sheet: to be prepared
ABSOLUTE MAXIMUM RATINGS (T
ParameterSymbolTest ConditionsRatingsUnit
Power supply voltageVDD–0.3 to +7.0V
VPP–0.3 to +13.5V
Input voltageVI1Excluding P60 to P63–0.3 to VDD + 0.3V
VI2P60 to P63N-ch open-drain–0.3 to +16V
VI3A9PROM programming mode–0.3 to +13.5V
Output voltageVO–0.3 to VDD + 0.3V
Output withstandV
voltage
Analog input voltage
Output current highIOH1 pin–10mA
Output current lowI
Operating ambientT
temperature
Storage temperature T
BDSP132 to P134N-ch open-drain16V
VANP10 to P15Analog input pin–0.3 to VDD+ 0.3V
P01 to P06, P30 to P37, P56, P57, P60 to P67,–15mA
P120 to P125 total
P10 to P15, P20 to P27, P40 to P47, P50 to P55,–15mA
P132 to P134 total
Note
OL
1 pinPeak value15mA
A–40 to +85°C
stg –65 to +150°C
A = 25 °C)
r.m.s. value7.5mA
Note r.m.s. (root mean square) value should be calculated as follows: [r.m.s value] = [Peak value] ×√duty
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single
parameter even momentarily. That is, the absolute maximum ratings are rated values at which
the product is on the verge of suffering physical damage, and therefore the product must be
used under conditions which ensure that the absolute maximum ratings are not exceeded.
Remark The characteristics of an alternate-function pin and a port pin are the same unless specified otherwise.
RECOMMENDED SUPPLY VOLTAGE RANGES (T
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
Power supply voltageVDD1During CPU operation and PLL operation.4.55.5V
V
DD2While the CPU is operating and the PLL is stopped.3.55.5V
Cycle Time: TCY≥ 0.89 µs
VDD3While the CPU is operating and the PLL is stopped.4.55.5V
Cycle Time: TCY = 0.44 µs
A = –40 to +85 °C)
Remark TCY: Cycle Time (Minimum instruction execution time)
24
Page 25
µ
PD178P018A
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
Input voltage highVIH1P10 to P15, P21, P23,0.7 VDDVDDV
P30 to P32, P35 to P37,
P40 to P47, P50 to P57,
P64 to P67, P120 to P125
VIH2P00 to P06, P20, P22,0.85 VDDVDDV
P24 to P27, P33, P34,
RESET
VIH3P60 to P630.7 VDD15V
(N-ch open-drain)
Input voltage lowVIL1P10 to P15, P21, P23,00.3 VDDV
P30 to P32, P35 to P37,
P40 to P47, P50 to P57,
P64 to P67, P120 to P125
VIL2P00 to P06, P20, P22,00.15 VDDV
P24 to P27, P33, P34,
RESET
VIL3P60 to P634.5 V ≤ VDD≤ 5.5 V00.3 VDDV
(N-ch open-drain)
Output voltage highVOH14.5 V ≤ VDD ≤ 5.5 V,VDD – 1.0V
Output voltage lowVOL1P50 to P57, P60 to P63VDD = 4.5 to 5.5 V,0.42.0V
P01 to P06, P10 to P15,VDD = 4.5 to 5.5 V,0.4V
P20 to P27, P30 to P37,IOL = 1.6 mA
P40 to P47, P64 to P67,
P120 to P125,
P132 to P134
V
OL2SB0, SB1, SCK0VDD = 4.5 to 5.5 V,0.2 VDDV
3.5 V ≤ VDD < 4.5 V00.2 VDDV
IOH = –1 mA
3.5 V ≤ VDD < 4.5 V,VDD – 0.5V
IOH = –100 µA
IOH = 15 mA
N-ch open-drain pulled-up
(R = 1 KΩ)
(1/3)
Remark The characteristics of an alternate-function pin and a port pin are the same unless specified otherwise.
25
Page 26
µ
PD178P018A
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
Input leakageI LIH1P00 to P06, P10 to P15,VIN = VDD3
current highP20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67, P120 to P125,
RESET
ILIH2P60 to P63VIN = 15 V80
Input leakageILIL1P00 to P06, P10 to P15,VIN = 0 V–3
current lowP20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67, P120 to P125,
RESET
ILIL2P60 to P63–3
Output leakageILOHP132 to P134VOUT = 15 V3
current high
Output leakageILOLP132 to P134VOUT = 0 V–3
current low
Output off leakI LOFEO0, EO1VOUT = VDD,±1
currentVOUT = 0 V
Note
Note When an input instruction is executed, the low-level input leakage current for P60 to P63 becomes –200
µ
A (MAX.) only in one clock cycle (at no wait). It remains at –3 µA (MAX.) for other than an input instruction.
(2/3)
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
Remark The characteristics of an alternate-function pin and a port pin are the same unless specified otherwise.
REFERENCE CHARACTERISTICS (T
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
Output current highIOH1EO0VOUT = VDD – 1 V–4mA
EO1 (EOCON0 = 0)–1.8mA
Output current lowIOL1EO0VOUT = 1 V6mA
EO1 (EOCON0 = 0)3.5mA
A = 25 °C, VDD = 5 V)
(1/2)
26
Page 27
µ
PD178P018A
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
Power supplyI
Note 1
current
DD1While the CPU is operatingTCY = 0.89
and the PLL is stopped
fX = 4.5-MHz operation
IDD2
TCY = 0.44 µs
µ
Note 2
s
Note 3
2.515mA
4.027mA
VDD = 4.5 to 5.5 V
IDD3While the CPU is operating TCY = 0.89 µs
Note 2
14mA
and the PLL is stopped
HALT Mode.
IDD4Pin X1 sine waveTCY = 0.44 µs
Note 3
1.66mA
input VIN = VDDVDD = 4.5 to 5.5 V
fX = 4.5-MHz operation
Data holdVDDR1When the crystal is oscillating TCY = 0.44 µs4.55.5V
power supply
voltage
V
DDR2TCY = 0.89
V
DDR3When the crystal oscillation is stopped2.75.5V
µ
s3.55.5V
When power off by Power On Clear is detected
Data hold
power supply current
IDDR1While the crystal oscillationTA = 25 °C, VDD = 5 V24
IDDR2
is stopped
230
Notes 1. The port current is not included.
2. When the Processor Clock Control register (PCC) is set at 00H, and the Oscillation Mode Select
register (OSMS) is set to 00H.
3. When PCC is set to 00H and OSMS is set to 01H.
(3/3)
µ
A
µ
A
Remarks 1. TCY: Cycle Time (Minimum instruction execution time)
2. fX: System clock oscillation frequency.
REFERENCE CHARACTERISTICS (T
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
Power supplyI
currentand PLL operation.
DD5During CPU operationTCY = 0.44
VCOH pin sine wave
input
fIN = 130 MHz,
VIN = 0.15 Vp-p
A = 25 °C, VDD = 5 V)
Note
µ
s
7mA
Note When the Processor Clock Control register (PCC) is set to 00H, and the Oscillation Mode Select register
(OSMS) is set to 01H.
Remark TCY: Cycle Time (Minimum instruction execution time)
Notes 1. When the Oscillation Mode Selection register (OSMS) is set to 00H.
2. When OSMS is set to 01H.
3. In combination with bits 0 (SCS0) and 1 (SCS1) of the Sampling Clock Select register (SCS),
selection of fsam is possible among fXX/2N, fXX/32, fXX/64, and fXX/128 (when N = 0 to 4).
Remarks 1. f
XX: System clock frequency (fX or fX/2)
2. fX: System clock oscillation frequency
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
CY vs VDD
T
(when system clock fXX is operating at fX/2)
60
10
s]
µ
CY [
2.0
1.0
Cycle Time T
0.5
0.4
0
123456
Power Supply Voltage VDD [V]Power Supply Voltage VDD [V]
Operation
Guaranteed
Range
T
CY vs VDD
(when system clock fXX is operating at fX)
60
10
s]
µ
[
CY
2.0
1.0
Cycle Time T
0.5
0.4
0
123456
Operation
Guaranteed
Range
28
Page 29
µ
PD178P018A
(2) SERIAL INTERFACE (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0 ... internal clock output)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
SCK0 cycle timetKCY14.5 V ≤ VDD ≤ 5.5 V800ns
3.5 V ≤ VDD < 4.5 V1 600ns
SCK0 high-/low-level widthtKH1,4.5 V ≤ VDD ≤ 5.5 V
tKL1
SI0 setup time (to SCK0↑)tSIK14.5 V ≤ VDD ≤ 5.5 V100ns
SI0 hold time (from SCK0↑)tKSI1400ns
SO0 output delay time from SCK0↓tKSO1C = 100 pF
3.5 V ≤ VDD < 4.5 V
3.5 V ≤ VDD < 4.5 V150ns
Note
tKCY1/2 – 50
tKCY1/2 – 100
300ns
Note C is the load capacitance of the SO0 output line.
ns
ns
(ii) 3-wire serial I/O mode (SCK0 ... external clock input)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
SCK0 cycle timetKCY24.5 V ≤ VDD ≤ 5.5 V800ns
3.5 V ≤ VDD < 4.5 V1 600ns
SCK0 high-/low-level widthtKH2,4.5 V ≤ VDD ≤ 5.5 V400ns
tKL2
SI0 setup time (to SCK0↑)tSIK2100ns
SI0 hold time (from SCK0↑)tKSI2400ns
SO0 output delay time from SCK0↓tKSO2C = 100 pF
SCK0 rising or falling edge timetR2, tF21 000ns
3.5 V ≤ VDD < 4.5 V800ns
Note
300ns
Note C is the load capacitance of the SO0 output line.
29
Page 30
µ
PD178P018A
(iii) SBI mode (SCK0 ... internal clock output)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
SCK0 cycle timetKCY34.5 V ≤ VDD ≤ 5.5 V800ns
3.5 V ≤ VDD < 4.5 V3 200ns
SCK0 high-/low-level widthtKH3,4.5 V ≤ VDD ≤ 5.5 V
tKL33.5 V ≤ VDD < 4.5 V
SB0, SB1 setup time (to SCK0↑)tSIK34.5 V ≤ VDD ≤ 5.5 V100ns
3.5 V ≤ VDD < 4.5 V300ns
SB0, SB1 hold time (from SCK0↑)
SB0, SB1 output delay time fromtKSO3R = 1 kΩ4.5 V ≤ VDD ≤ 5.5 V0250ns
SCK0↓
SB0, SB1↓ from SCK0
SCK0↓ from SB0, SB1↓tSBKtKCY3ns
SB0, SB1 high-level widthtSBHtKCY3ns
SB0, SB1 low-level widtht
↑
tKSI3tKCY3/2ns
C = 100 pF
tKSBtKCY3ns
SBLtKCY3ns
Note
3.5 V ≤ VDD < 4.5 V01 000ns
tKCY3/2 – 50
tKCY3/2 – 150
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
(iv) SBI mode (SCK0 ... external clock input)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
SCK0 cycle timetKCY44.5 V ≤ VDD ≤ 5.5 V800ns
3.5 V ≤ VDD < 4.5 V3 200ns
SCK0 high-/low-level widthtKH4,4.5 V ≤ VDD ≤ 5.5 V400ns
tKL43.5 V ≤ VDD < 4.5 V1 600ns
ns
ns
SB0, SB1 setup time (to SCK0↑)tSIK44.5 V ≤ VDD ≤ 5.5 V100ns
3.5 V ≤ VDD < 4.5 V300ns
SB0, SB1 hold time (from SCK0↑)
SB0, SB1 output delay time fromtKSO4R = 1 kΩ4.5 V ≤ VDD ≤ 5.5 V0300ns
SCK0↓
SB0, SB1↓ from SCK0
SCK0↓ from SB0, SB1↓tSBKtKCY4ns
SB0, SB1 high-level widthtSBHtKCY4ns
SB0, SB1 low-level widthtSBLtKCY4ns
SCK0 rising or falling edge timetR4, tF41 000ns
↑
tKSI4tKCY4/2ns
C = 100 pF
tKSBtKCY4ns
Note
3.5 V ≤ VDD < 4.5 V01 000ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
30
Page 31
µ
PD178P018A
(v) 2-wire serial I/O mode (SCK0 ... internal clock output)
SDA0, SDA1↓ from SCL↑ ort KSB200ns
SDA0, SDA1↑ from SCL↑
tSIK8200ns
C = 100 pF
Note
3.5 V ≤ VDD < 4.5 V0500ns
SCL↓ from SDA0, SDA1↓t SBK400ns
SDA0, SDA1 high-level widthtSBH500ns
SCL rising or falling edge timetR8, tF81 000ns
Note R and C are the load resistance and load capacitance of the SDA0 and SDA1 output lines.
32
Page 33
µ
PD178P018A
(b) Serial interface channel 1
(i) 3-wire serial I/O mode (SCK1 ... internal clock output)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
SCK1 cycle timetKCY94.5 V ≤ VDD ≤ 5.5 V800ns
3.5 V ≤ VDD < 4.5 V1 600ns
SCK1 high-/low-level widthtKH9,4.5 V ≤ VDD ≤ 5.5 V
tKL93.5 V ≤ VDD < 4.5 V
SI1 setup time (to SCK1↑)tSIK94.5 V ≤ VDD ≤ 5.5 V100ns
3.5 V ≤ VDD < 4.5 V150ns
SI1 hold time (from SCK1↑)tKSI9400ns
SO1 output delay time (from SCK1↓)
tKSO9C = 100 pF
Note
tKCY9/2 – 50
tKCY9/2 – 100
ns
ns
300ns
Note C is the load capacitance of the SO1 output line.
(ii) 3-wire serial I/O mode (SCK1 ... external clock input)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
SCK1 cycle timetKCY104.5 V ≤ VDD ≤ 5.5 V800ns
3.5 V ≤ VDD < 4.5 V1 600ns
SCK1 high-/low-level widthtKH10,4.5 V ≤ VDD ≤ 5.5 V400ns
tKL103.5 V ≤ VDD < 4.5 V800ns
SI1 setup time (to SCK1↑)tSIK10100ns
SI1 hold time (from SCK1↑)tKSI10400ns
SO1 output delay time (from SCK1↓
SCK1 rising or falling edge timetR10, tF101 000ns
)tKSO10C = 100 pF
Note
300ns
Note C is the load capacitance of the SO1 output line.
33
Page 34
µ
PD178P018A
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... internal clock
output)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
SCK1 cycle timet KCY114.5 V ≤ VDD ≤ 5.5 V800ns
3.5 V ≤ VDD < 4.5 V1 600ns
SCK1 high-/low-level widthtKH11,4.5 V ≤ VDD ≤ 5.5 V
tKL113.5 V ≤ VDD < 4.5 V
SI1 setup time (to SCK1↑)tSIK114.5 V ≤ VDD ≤ 5.5 V100ns
3.5 V ≤ VDD < 4.5 V150ns
SI1 hold time (from SCK1↑)tKSI11400ns
SO1 output delay time (from SCK1↓
STB↑ from SCK1
Strobe signal high-level widthtSBW
Busy signal setup timetBYS100ns
(to busy signal detection timing)
Busy signal hold timet BYH4.5 V ≤ VDD ≤ 5.5 V100ns
(from busy signal detection timing)
SCK1↓ from busy inactivetSPS2tKCY11ns
↑
)tKSO11C = 100 pF
tSBD
3.5 V ≤ VDD < 4.5 V150ns
Note
tKCY11/2 – 50
tKCY11/2 – 100
300ns
tKCY11/2 – 100tKCY11/2 + 100
tKCY11 – 30tKCY11 + 30
ns
ns
ns
ns
Note C is the load capacitance of the SO1 output line.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... external clock
input)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
SCK1 cycle timet KCY124.5 V ≤ VDD ≤ 5.5 V800ns
3.5 V ≤ VDD < 4.5 V1 600ns
SCK1 high-/low-level widthtKH12,4.5 V ≤ VDD ≤ 5.5 V400ns
tKL123.5 V ≤ VDD < 4.5 V800ns
SI1 setup time (to SCK1↑)tSIK12100ns
SI1 hold time (from SCK1↑)tKSI12400ns
SO1 output delay time (from SCK1↓
SCK1 rising or falling edge timetR12, tF121 000ns
)tKSO12C = 100 pF
Note
300ns
Note C is the load capacitance of the SO1 output line.
34
Page 35
AC Timing Test Point (Excluding X1 Input)
µ
PD178P018A
TI Timing
TI1, TI2
Interrupt Input Timing
INTP0 to INTP6
0.8 VDD
0.2 VDD
Test Points
1/fTI
tTILtTIH
tINTLtINTH
0.8 VDD
0.2 VDD
RESET Input Timing
RESET
t
RSL
35
Page 36
Serial Transfer Timing
3-Wire Serial I/O Mode:
tKCYm
µ
PD178P018A
SCK0, SCK1
SI0, SI1
tKSOm
SO0, SO1
Remark m = 1, 2, 9, 10
n = 2, 10
SBI Mode (Bus Release Signal Transfer):
tKLm
tRn
Input Data
tKHm
tFn
tKSImtSIKm
Output Data
SCK0
SB0, SB1
tKSBtSBLtSBHtSBK
tKCY3, 4
tKL3, 4tKH3, 4
tKSO3, 4
tF4tR4
tSIK3, 4
tKSI3, 4
36
Page 37
SBI Mode (Command Signal Transfer):
SCK0
tKCY3, 4
tKL3, 4tKH3, 4
µ
PD178P018A
tF4tR4
SB0, SB1
2-Wire Serial I/O Mode:
tKSBtSBK
SCK0
SB0, SB1
tKSO5, 6
tKSO3, 4
tKCY5, 6
tKL5, 6tKH5, 6
tSIK5, 6
tKSI5, 6
tSIK3, 4
tF6tR6
tKSI3, 4
2
C Bus Mode:
I
SCL
SDA0, SDA1
F8
tR8
t
tKL7, 8
tSBKtSBH
tKSI7, 8
tKCY7, 8
tKH7, 8
tKSO7, 8
tSIK7, 8
tKSB
tKSB
tSBK
37
Page 38
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function:
µ
PD178P018A
SO1
SI1
SCK1
STB
D2D1D0
D2D1D0
tSIK11, 12
tKSO11, 12
tKL11, 12
tKCY11, 12tSBDtSBW
tKSI11, 12
tKH11, 12
tF12
tR12
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function (Busy Processing):
789
Note
tBYS
10
Note
Note
10+n
tBYHtSPS
D7
D7
1SCK1
BUSY
(Active high)
Note The signal is not actually driven low here; it is shown as such to indicate the timing.
38
Page 39
µ
PD178P018A
A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
Resolution888bit
Conversion total±3.0LSB
error
Conversion timetCONV22.244.4
Sampling timetSAMP15/fXX
Analog inputVIAN0VDDV
voltage
Remarks 1. fXX: System clock frequency (fX/2)
2. fX: System clock oscillation frequency
PLL CHARACTERISTICS (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V)
ParameterSymbolTest ConditionsMIN.TYP.MAX.Unit
OperatingfIN1VCOL Pin MF Mode Sine wave input VIN = 0.1 Vp-p0.53MHz
frequency
Note The condition of a sine wave input of VIN = 0.1 Vp-p is the standard value for operation of this device during
stand-alone operation, so in consideration of the effect of noise, it is recommended that operation be at
an input amplitude condition of VIN = 0.15 Vp-p.
ParameterSymbol
Address setup time (to OE ↓)tAStAS2
OE setup timetOEStOES2
CE setup time (to OE ↓)tCEStCES2
Input data setup time (to OE ↓)tDStDS2
Address hold time (from OE ↑)tAHtAH2
Input data hold time (from OE ↑)tDHtDH2
Data output float delay timet
A = 25 ± 5 °C, VDD = 6.5 ± 0.25 V, VPP = 12.5 ± 0.3 V)
Note
Symbol
Test ConditionsMIN.TYP.MAX.Unit
tAHLtAHL2
tAHVtAHV0
DFtDF0250ns
µ
µ
µ
µ
µ
µ
µ
µ
from OE ↑
VPP setup time (to OE ↓)tVPStVPS1.0ms
VDD setup time (to OE ↓)tVDStVCS1.0ms
Program pulse widthtPWtPW0.0950.10.105ms
Valid data delay time from OE ↓tOEtOE1
OE pulse width during datat
LWtLW1
µ
µ
latching
PGM setup timetPGMStPGMS2
CE hold timetCEHtCEH2
OE hold timet
OEHtOEH2
µ
µ
µ
s
s
s
s
s
s
s
s
s
s
s
s
s
(b) Byte program mode (T A = 25 ± 5 °C, V DD = 6.5 ± 0.25 V, VPP = 12.5 ± 0.3 V)
ParameterSymbol
Address setup time (to PGM ↓)tAStAS2
OE set timetOEStOES2
CE setup time (to PGM ↓)tCEStCES2
Input data setup time (to PGM ↓)tDStDS2
Address hold time (from OE ↑)tAHtAH2
Input data hold timet
DHtDH2
(from PGM ↑)
Data output float delay timet
DFtDF0250ns
from OE ↑
VPP setup time (to PGM ↓)tVPStVPS1.0ms
VDD setup time (to PGM ↓)tVDStVCS1.0ms
Program pulse widthtPWtPW0.0950.10.105ms
Valid data delay time from OE ↓tOEtOE1
OE hold timet
PD178018A and µPD178018) is replaced with one-time PROM
or EPROM in the one-time PROM versions (µPD178P018A and µPD178P018).
µ
PD178P018
48
Page 49
µ
PD178P018A
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD178P018A Subseries.
Language Processing Software
RA78K/0
CC78K/0
DF178018
CC78K/0-L
PROM Writing Tools
PG-1500PROM writer
PG-178P018GCProgram writer adapters connected to a PG-1500
PA-178P018KK-T
PG-1500 controller
Debugging Tools
Notes 1, 2, 3, 4
Notes 1, 2, 3, 4
Notes 1, 2, 3, 4, 8
Notes 1, 2, 3, 4
Notes 1, 2
78K/0 Series common assembler package
78K/0 Series common C compiler package
µ
PD178018A Subseries common device file
78K/0 Series common C compiler library source file
PG-1500 control program
IE-78000-RIn-circuit emulator common to 78K/0 Series
IE-78000-R-AIn-circuit emulator common to 78K/0 Series (for the integrated debugger)
IE-78000-R-BKBreak board common to 78K/0 Series
IE-178018-R-EMEmulation board common to µPD178018A Subseries
IE-78000-R-SV3Interface adapter and cable when using EWS as a host machine (for IE-78000-R-A)
IE-70000-98-IF-BInterface adapter when using the PC-9800 Series (except notebooks) as a host machine
(for IE-78000-R-A)
IE-70000-98N-IFInterface adapter and cable when using the PC-9800 Series notebook as a host machine
(for IE-78000-R-A)
IE-70000-PC-IF-BInterface adapter when using IBM PC/ATTM as a host machine (for IE-78000-R-A)
EP-78230GC-REmulation probe common to µPD78234 Subseries
EV-9200GC-80Socket for mounting on target system board created for 80-pin plastic QFP (GC-3B9 type)
EV-9900Jig used when removing the µPD178P018AKK-T from the EV-9200GC-80.
SM78K0
ID78K0
SD78K/0
DF178018
Notes 5, 6, 7
Notes 4, 5, 6, 7
Notes 1, 2
Notes 1, 2, 4, 5, 6, 7, 8
78K/0 series common system simulator
Integrated debugger for IE-78000-R-A
IE-78000-R screen debugger
µ
PD178018A Subseries device file
49
Page 50
Real-Time OS
µ
PD178P018A
RX78K/0
MX78K0
Notes 1, 2, 3, 4
Notes 1, 2, 3, 4
78K/0 Series real-time OS
78K/0 Series OS
Notes 1. PC-9800 Series (MS-DOSTM) based
2. IBM PC/AT and compatibles (PC DOSTM/IBM DOSTM/MS-DOS) based
3. HP9000 Series 300TM (HP-UX™) based
4. HP9000 Series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM) based, EWS4800 Series
(EWS-UX/V) based
5. PC-9800 Series (MS-DOS + WindowsTM) based
6. IBM PC/AT and compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based
2. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based
3. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS) based
Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party
development tools.
2. The RA78K/0, CC78K/0, SD78K/0, ID78K/0, SM78K/0, and RX78K/0 are used in combination with
the DF178018.
50
Page 51
CONVERSION SOCKET DRAWING AND RECOMMENDED FOOTPRINT
A
F
D
1
No.1 pin index
E
EV-9200GC-80
B
C
M
NO
L
K
S
R
Q
P
I
H
J
G
EV-9200GC-80-G1E
ITEMMILLIMETERSINCHES
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
18.0
14.4
14.4
18.0
4-C 2.0
0.8
6.0
16.0
18.7
6.0
16.0
18.7
8.2
8.0
2.5
2.0
0.35
2.3
1.5
0.709
0.567
0.567
0.709
4-C 0.079
0.031
0.236
0.63
0.736
0.236
0.63
0.736
0.323
0.315
0.098
0.079
0.014
0.091
0.059
φ
φ
Based on EV-9200GC-80
(1) Package drawing (in mm)
φ
φ
Figure B-1. Drawing of EV-9200GC-80 (for Reference only)
µ
PD178P018A
51
Page 52
Figure B-2. Recommended Footprint of EV-9200GC-80 (for Reference only)
Based on EV-9200GC-80
(2) Pad drawing (in mm)
G
J
K
F
E
D
L
C
B
A
HI
µ
PD178P018A
EV-9200GC-80-P1E
ITEMMILLIMETERSINCHES
+0.001
–0.002
+0.001
–0.002
0.776
0.591
0.591
0.776
0.236
0.236
0.014
φ
0.093
φ
0.091
φ
0.062
+0.003
–0.002
+0.003
–0.002
+0.001
–0.001
+0.001
–0.002
+0.001
–0.002
A
B
C
D
E
F
G
H
I
J
K
L
Caution
19.7
15.0
±
0.65
0.02 × 19=12.35
±
0.65
0.02 × 19=12.35
±
0.026 × 0.748=0.486
0.05
±
0.026 × 0.748=0.486
0.05
15.0
19.7
6.0±0.05
6.0±0.05
0.35±0.02
φ
2.36±0.03
φ
2.3
φ
1.57±0.03
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (C10535E).
+0.003
–0.002
+0.003
–0.002
52
Page 53
APPENDIX C. RELATED DOCUMENTS
Device Documents
µ
PD178P018A
Title
µ
PD178018A Subseries User’s Manual
78K/0 Series User’s Manual—InstructionU12326JU12326E
78K/0 Series Instruction SetU10904J—
78K/0 Series Instruction TableU10903J—
µ
PD178018A Subseries Special Function Register Table
78K/0 Series Application NoteBasics (II)U10121JU10121E
Document No.Document No.
(Japanese)(English)
To be preparedTo be prepared
To be prepared
—
Development Tool Documents (User’s Manual)
Title
RA78K Series Assembler PackageOperationEEU-809EEU-1399
LanguageEEU-815EEU-1404
RA78K Series Structured Assembler PreprocessorEEU-817EEU-1402
RA78K0 Assembler PackageOperationU11802JU11802E
Assembly LanguageU11801JU11801E
Structured AssemblyU11789JU11789E
Language
CC78K Series C CompilerOperationEEU-656EEU-1280
LanguageEEU-655EEU-1284
CC78K/0 C CompilerOperationU11517JU11517E
LanguageU11518JU11518E
CC78K/0 C Compiler Application Notes
CC78K Series Library Source FileU12322J—
PG-1500 PROM ProgrammerU11940JEEU-1335
PG-1500 Controller PC-9800 Series (MS-DOS) BasedEEU-704EEU-1291
PG-1500 Controller IBM PC Series (PC DOS) BasedEEU-5008U10540E
IE-78000-RU11376JU11376E
IE-78000-R-AU10057JU10057E
IE-78000-R-BKEEU-867EEU-1427
IE-178018-R-EMU10668JU10668E
EP-78230EEU-985EEU-1515
SM78K0 System Simulator Windows BasedReferenceU10181JU10181E
SM78K Series System SimulatorU10092JU10092E
ID78K0 Integrated Debugger EWS BasedReferenceU11151JU11151E
ID78K0 Integrated Debugger PC BasedReferenceU11539JU11539E
ID78K0 Integrated Debugger Windows BasedGuideU11649JU11649E
SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based
SD78K/0 Screen Debugger IBM PC/AT (PC DOS) BasedIntroductionEEU-5024EEU-1414
Programming Know-how
External Parts User
open Interface
Specifications
IntroductionEEU-852U10539E
ReferenceU10952J—
ReferenceU11279JU11279E
Document No.Document No.
(Japanese)(English)
EEA-618EEA-1208
Caution The contents of the above documents are subject to change without notice. Please ensure that
the latest versions are used in design work, etc.
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Related Documents for Embedded Software (User’s Manual)
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Title
78K/0 Series Realtime OSBasicsU11537J—
InstallationU11536J—
78K/0 Series OS MX78K0BasicsU12257J—
Fuzzy Knowledge Data Creation ToolEEU-829EEU-1438
78K/0, 78K/II, 87AD SeriesEEU-862EEU-1444
Fuzzy Inference Development Support System—Translator
78K/0 Series Fuzzy Inference Development Support System—
78K/0 Series Fuzzy Inference Development Support SystemEEU-921EEU-1458
—Fuzzy Inference Debugger
Fuzzy Inference Module
Document No.Document No.
(Japanese)(English)
EEU-858EEU-1441
Other Documents
Title
IC Package ManualC10943X
Semiconductor Device Mounting Technology ManualC10535JC10535E
Quality Guides on NEC Semiconductor DevicesC11531JC11531E
NEC Semiconductor Device Reliability and Quality Control SystemC10983JC10983E
Electrostatic Discharge (ESD) TestMEM-539—
Semiconductor Device Quality Assurance GuideC11893JMEI-1202
Microcomputer-related Product Guide (Products by other Manufacturers)U11416J—
Document No.Document No.
(Japanese)(English)
Caution The contents of the above documents are subject to change without notice. Ensure that the
latest versions are used in design work, etc.
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NOTES FOR CMOS DEVICES
1PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices
must be stored and transported in an anti-static container, static shielding bag
or conductive material. All test and measurement tools including work bench
and floor should be grounded. The operator should be grounded using wrist
strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
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2HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS device
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
United Square, Singapore 1130
Tel:253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
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Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of
these products may be prohibited without governmental license. To export or re-export some or all of these
products from a country other than Japan may also be prohibited without a license from that country. Please call
an NEC sales representative.
License not needed:
The customer must judge the need for license :
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
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