Page 1
DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC1853
MATRIX SURROUND IC WITH I2C BUS
The µPC1853 is a phase shift matrix surround IC. Only 2 speakers on the front side implement wide sound
expansion, and by adding rear speakers, rich three-dimensional sound can obtained.
The µPC1853 can perform all controls (mode switching, volume control and so on) through the I2C bus.
FEATURES
• Any control is possible through the I2C bus.
• Surround effect can be realized by only 2 speakers on the front side.
• On-chip tone (bass and treble) control circuit.
• Level-adjustable output pin for heavy bass sound.
• Level-adjustable output pin for AV amplifier.
µ
PC1853-01 : On-chip low boost circuit.
•
On-chip volume and balance control circuits.
µ
PC1853-02 : On-chip L-channel volume and R-channel volume control circuits.
•
APPLICATION
• TV, audio
ORDERING INFORMATION
Part Number Package
µ
PC1853CT-01 30-pin plastic shrink DIP (400 mil)
µ
PC1853CT-02
"
The information in this document is subject to change without notice.
Document No. S10552EJ2V0DS00 (2nd edition)
(Previous No. ID-3126)
Date Published October 1995 P
Printed in Japan
©
1995
Page 2
SYSTEM BLOCK DIAGRAM
•TV
µ
PC1853
µ
PD17002
µ
PD17052
µ
PD17053
µ
PC2800A
µ
PC2801A
Tuner PIF & SIF
Digital
tuning
controller
Remote control
reception
amplifier
PIN photo diode
SDA
SCL
µ
PC1852
US MTS
processor
Color, intensity
and deflecting
Signal processor
µ
PC1853
L
Surround
Surround
processor
processor
R
RGB
output
Vertical
output
µ
PC1310
µ
PC1316C
Power amplifier
CRT
2
Page 3
820 kΩ
0.022 F
µ
0.022 F
12 V
µ
CC
V
0.1 F
µ
2200 pF
FC1FC2 FC3 FC4
680 pF
0.082 F
µ
MFO MFI LF1
29 30 28 2 3 4 5 15 6 25
1000 pF
LF2 OFC
–
+
µ
22 F
0.1 F
µ
LBC LTC
10 9
6800 pF
BLOCK DIAGRAM
(1)
µ
PC1853-01
L
in
–+
22 F
µ
in
R
–+
22 F
µ
26
27
A
Bass
Treble
D
A
Volume, balance
control/Mute
Volume control
/Mute
D
A
Volume
Balance
D
Volume control
/Mute
Volume, balance
control/Mute
Volume control
/Mute
D
A
D
L1 OUT
14
L2 OUT
17
VOL-C
18
+
3.3 F
µ
–
A
BAL-C
19
+
µ
3.3 F
–
R2 OUT
16
13
R1 OUT
11
Rear OUT
A
µ
12
L+R OUT
PC1853
Tone control/
Low boost
D
–
+
LPF
–
+
1
V
2
CC
I2C bus interface
PS1PS2PS3 PS4
Phase shifter
Effect
control
LPF
D
A
Offset
absorption
1
V
2
CC
Matrix
L + R volume
control/Mute
D
A
Tone control/
Low boost
23
1
CC
V
2
3
µ
22 F
+
–
ADS SDA SCL
20212224
1
GNDGND
RBC RTC
0.1 F
7
8
µ
6800 pF
Page 4
4
(2)
820 kΩ
µ
PC1853-02
0.082 F
µ
0.022 F
µ
0.022 F
12 V
µ
CC
V
0.1 F
µ
2200 pF
FC1FC2FC3 FC4
680 pF
MFIMFO LF1
3029 28 2 3 4 5 15 6 25
1000 pF
LF2 OFC
–
+
µ
22 F
0.1 F
µ
LBC LTC
10 9
6800 pF
L
in
–+
22 F
µ
in
R
–+
22 F
µ
26
27
A
Bass
Volume control
/Mute
Volume control
/Mute
D
A
D
A
L1 OUT
14
L2 OUT
17
LVC
18
+
3.3 F
µ
–
D
A
RVC
19
+
µ
3.3 F
–
LPF
–
+
Tone control
D
–
+
PS1PS2PS3PS4
Effect
control
LPF
Offset
absorption
1
V
CC
2
Matrix
Phase shifter
D
A
Treble
D
A
Volume control
/Mute
Tone control
1
V
2
CC
I2C bus interface
L + R volume
control/Mute
D
A
Volume control
/Mute
Volume control
/Mute
D
A
R2 OUT
16
13
R1 OUT
11
Rear OUT
12
L+R OUT
1
V
2
µ
22 F
23
CC
+
ADS SDA SCL
20212224
–
1
GNDGND
RBC RTC
µ
0.1 F
7
8
6800 pF
µ
PC1853
Page 5
PIN CONFIGURATION (Top View)
(1)µPC1853-01
µ
PC1853
Ground (for Analog) Monaural filter inputGND MFI
Phase shift filter 1 Monaural filter outputFC1 MFO
Phase shift filter 2 Low-pass filter 1FC2 LF1
Phase shift filter 3 R-channel signal inputFC3 R
Phase shift filter 4 L-channel signal inputFC4 L
Low-pass filter 2 Offset absorption capacitorLF2 OFC
R-channel treble capacitor Reference voltage filterRTC V
R-channel bass capacitor Ground (for I2C bus)RBC GND
L-channel treble capacitor Slave address selectLTC ADS
L-channel bass capacitor Serial data (for I
Rear output Serial clock (for I
L+R signal output Balance offset absorption capacitorL+R OUT BAL-C
R-channel signal output 1 Volume offset absorption capacitorR1 OUT VOL-C
130
229
328
427
526
625
724
823
922
10 21
11 20
12 19
13 18
µ
PC1853CT –01
in
in
1
CC
2
2
C bus)LBC SDA
2
C bus)Rear OUT SCL
L-channel signal output 1 L-channel signal output 2L1 OUT L2 OUT
Power supply R-channel signal output 2V
14 17
15 16
CC
R2 OUT
5
Page 6
(2)µPC1853-02
µ
PC1853
Ground (for Analog) Monaural filter inputGND MFI
Phase shift filter 1 Monaural filter outputFC1 MFO
Phase shift filter 2 Low-pass filter 1FC2 LF1
Phase shift filter 3 R-channel signal inputFC3 R
Phase shift filter 4 L-channel signal inputFC4 L
Low-pass filter 2 Offset absorption capacitorLF2 OFC
R-channel treble capacitor Reference voltage filterRTC V
R-channel bass capacitor Ground (for I2C bus)RBC GND
L-channel treble capacitor Slave address selectLTC ADS
L-channel bass capacitor Serial data (for I
Rear output Serial clock (for I
L+R signal output R-channel volume offset absorption capacitorL+R OUT RVC
R-channel signal output 1 L-channel volume offset absorption capacitorR1 OUT LVC
130
229
328
427
526
625
724
823
922
10 21
11 20
12 19
13 18
µ
PC1853CT –02
in
in
1
CC
2
2
C bus)LBC SDA
2
C bus)Rear OUT SCL
L-channel signal output 1 L-channel signal output 2L1 OUT L2 OUT
Power supply R-channel signal output 2V
14 17
15 16
CC
R2 OUT
6
Page 7
µ
PC1853
CONTENTS
1. EXPLANATION OF PINS................................................................................................................ 8
2. ATTENTIONS.................................................................................................................................... 16
3. I2C BUS INTERFACE...................................................................................................................... 17
3.1 Data Transfer............................................................................................................................................. 17
3.1.1 Start condition .............................................................................................................................. 17
3.1.2 Stop condition............................................................................................................................... 18
3.1.3 Data transfer.................................................................................................................................. 18
3.2 Data Transfer Format ............................................................................................................................... 18
3.2.1 1 byte data transfer....................................................................................................................... 19
3.2.2 Serial data transfer ....................................................................................................................... 20
3.2.3 Acknowledge................................................................................................................................. 20
4. EXPLANATION OF EACH COMMAND......................................................................................... 21
4.1 Subaddress List........................................................................................................................................ 21
4.2 Initialization ............................................................................................................................................... 23
4.3 Surround Function ................................................................................................................................... 24
4.4 Explanation of Each Command............................................................................................................... 25
µ
4.4.1
4.4.2
PC1853-01 ................................................................................................................................... 25
µ
PC1853-02 ................................................................................................................................... 32
5. ELECTRICAL CHARACTERISTICS ............................................................................................... 35
6. CHARACTERISTIC CURVES.......................................................................................................... 63
6.1 Frequency Response Characteristics in Each Mode ............................................................................ 63
6.2 Characteristics of Phase Shifter and Rear Output ................................................................................ 66
6.3 Control Characteristics ............................................................................................................................ 68
6.4 Input/Output Characteristics, Distortion Rate ....................................................................................... 73
7. MEASURING CIRCUIT .................................................................................................................... 74
8. PACKAGE DIMENSIONS ................................................................................................................ 75
7
Page 8
1. EXPLANATION OF PINS
Table 1-1 Explanation of Pins (1/8)
Pin Number Pin Name Equivalent Circuit Description
1 GND Ground for analog signal.
15
23
Pin voltage: approx. 0.0 V
1
µ
PC1853
2 FC1 Capacitor connection pin which
V
CC
36 kΩ
36 kΩ
determines time constant of phase
shifter.
Pin voltage: approx. 6.0 V
18 kΩ
V
CC
2
µ
F0.1
3 FC2
CC
V
36 kΩ
36 kΩ
18 kΩ
V
CC
3
8
4 FC3
2200 pF
V
CC
36 kΩ
36 kΩ
18 kΩ
V
CC
4
µ
F0.022
Page 9
Table 1-1 Explanation of Pins (2/8)
Pin Number Pin Name Equivalent Circuit Description
5 FC4 Capacitor connection pin which
V
CC
36 kΩ
36 kΩ
determines time constant of phase
shifter.
Pin voltage: approx. 6.0 V
18 kΩ
V
CC
5
µ
F0.022
µ
PC1853
6 LF2 Low-pass filter.
CC
V
17.7 kΩ
Pin voltage: approx. 6.0 V
17.7 kΩ
V
CC
6
1000 pF
7 RTC Capacitor connection pin for treble
CC
V
boost/cut frequency characteristic of
R-channel signal.
7.5 kΩ
Pin voltage: approx. 6.0 V
5.8 kΩ
V
CC
3 kΩ
7
6800 pF
8 RBC Capacitor connection pin for bass
CC
V
boost/cut frequency characteristic of Rchannel signal.
Pin voltage: approx. 6.0 V
6.5 kΩ
VCC
3 kΩ
8
µ
F0.1
9
Page 10
Table 1-1 Explanation of Pins (3/8)
Pin Number Pin Name Equivalent Circuit Description
9 LTC Capacitor connection pin for treble
CC
V
boost/cut frequency characteristic of
7.5 kΩ
L-channel signal.
Pin voltage: approx. 6.0 V
5.8 kΩ
V
CC
3 kΩ
9
pF6800
µ
PC1853
10 LBC Capacitor connection pin for bass
CC
V
boost/cut frequency characteristic of
L-channel signal.
6.5 kΩ
V
CC
3 kΩ
Pin voltage: approx. 6.0 V
10
µ
F0.1
V
4 kΩ
CC
500 Ω
output signal (φ(L-R) signal or (L-R)
signal) (see 4.4.1(4) or 4.4.2(2) Rear
output selection).
• φ(L-R): Phase-shifted.
• (L-R) : Not phase-shifted.
Pin voltage: approx. 6.0 V
11 Rear OUT L-R signal output pin. Select the
V
CC
4 kΩ
V
CC
15 kΩ
11
4 kΩ
4 kΩ
12 L+R OUT L+R signal output pin.
V
CC
4 kΩ
V
CC
4 kΩ
V
CC
Pin voltage: approx. 6.0 V
500 Ω
15 kΩ
12
4 kΩ
4 kΩ
10
Page 11
µ
Table 1-1 Explanation of Pins (4/8)
Pin Number Pin Name Equivalent Circuit Description
V
4 kΩ
4 kΩ
CC
500 Ω
output).
Pin voltage: approx. 6.0 V
13 R1 OUT R-channel signal output pin (for main
V
CC
4 kΩ
V
CC
15 kΩ
13
4 kΩ
PC1853
14 L1 OUT L-channel signal output pin (for main
V
CC
4 kΩ
V
CC
4 kΩ
V
CC
500 Ω
output).
Pin voltage: approx. 6.0 V
15 kΩ
14
4 kΩ
4 kΩ
15 VCC Supply voltage.
15
Pin voltage: approx. 12.0 V
1
V
16 R2 OUT R-channel signal output pin for
CC
external audio processor and so on.
V
CC
4 kΩ
V
CC
4 kΩ
500 Ω
Pin voltage: approx. 6.0 V
16
15 kΩ
4 kΩ
4 kΩ
11
Page 12
Table 1-1 Explanation of Pins (5/8)
Pin Number Pin Name Equivalent Circuit Description
17 L2 OUT L-channel signal output pin for external
VCC
4 kΩ
VCC
17
4 kΩ
18 VOL-C Capacitor connection pin which
(µPC1853-01) absorbs shock noise of D/A converter
CC
V
15 kΩ
4 kΩ
4 kΩ
VCC
500 Ω
V
CC
4 kΩ
audio processor and so on.
Pin voltage: approx. 6.0 V
for volume control.
Pin voltage: approx. 6.0 V
µ
PC1853
15 kΩ
500 Ω
500 Ω
4 kΩ
V
CC
4 kΩ
4 kΩ
for L-channel volume control.
Pin voltage: approx. 6.0 V
for balance control.
Pin voltage: approx. 4.8 V
for R-channel volume control.
Pin voltage: approx. 4.8 V
bus).
Pin voltage: approx. 0.0 V
18
µ
20
+
µ
F3.3
CC
V
19
+
F3.3
4 kΩ
LVC Capacitor connection pin which
(µPC1853-02) absorbs shock noise of D/A converter
19 BAL-C Capacitor connection pin which
(µPC1853-01) absorbs shock noise of D/A converter
RVC Capacitor connection pin which
(µPC1853-02) absorbs shock noise of D/A converter
20 SCL Serial clock line pin (clock input for I2C
12
Page 13
µ
Table 1-1 Explanation of Pins (6/8)
Pin Number Pin Name Equivalent Circuit Description
21 SDA Serial data line pin (data input for I2C
bus).
Pin voltage: approx. 0.0 V
21
4 k
150 Ω
Ω
CC
V
1 kΩ 1 kΩ
V
CC
PC1853
25
kΩ
125 kΩ
22 ADS Slave address selection pin.
Pin voltage: approx. 0.0 V
22
23 DGND Ground for I2C bus signal.
4 kΩ
1
Pin voltage: approx. 0.0 V
23
24 1
2 voltage.
VCC
V
CC
CC
V
V
CC
Filter pin for middle point of supply
Pin voltage: approx. 6.0 V
10 kΩ5 kΩ
V
CC
24
+
µ
F22
20 kΩ
10 kΩ
5 kΩ
13
20 kΩ
Page 14
Table 1-1 Explanation of Pins (7/8)
Pin Number Pin Name Equivalent Circuit Description
25 OFC Capacitor connection pin which
VCC
10 kΩ
10 kΩ
VCC
25
absorbs offset voltage generated by
phase shifter.
Pin voltage: approx. 6.0 V
+
µ
F22
µ
PC1853
26 Lin L-channel signal input pin.
27 Rin R-channel signal input pin.
signal input
28 LF1 Low-pass filter.
26
+
µ
F22
L-channel
signal input
V
27
+
µ
F22
R-channel
18 kΩ
1 kΩ
VCC
V
CC
60 kΩ
CC
60 kΩ
Input impedance: 60 kΩ
Pin voltage: approx. 6.0 V
Input impedance: 60 kΩ
Pin voltage: approx. 6.0 V
Pin voltage: approx. 6.0 V
14
28
680 pF
Page 15
µ
PC1853
Table 1-1 Explanation of Pins (8/8)
Pin Number Pin Name Equivalent Circuit Description
29 MFO High-pass filter output pin for surround
function (Simulated mode)
18 kΩ1 kΩ
V
CC
(see 4.3 Surround Function).
Pin voltage: approx. 6.0 V
30 MFI High-pass filter input pin for surround
820 kΩ
29
0.082 F
µ
30
V
CC
15 kΩ
47 kΩ
function (Simulated mode)
(see 4.3 Surround Function).
Pin voltage: approx. 6.0 V
15
Page 16
2. ATTENTIONS
<1> Attention on Pop Noise Reduction
When changing the surround mode and switching power, use the mute function (approx. 200 ms) for pop noise
reduction (see 4.4.1(2) Mute for the µPC1853-01 or 4.4.2(1) Mute for the µPC1853-02).
<2> Attention on Supply Voltage
2
Drive data on the I
C bus after supply voltage of total application system becomes stable.
µ
PC1853
16
Page 17
µ
PC1853
3. I2C BUS INTERFACE
The µPC1853 has serial bus function. This serial bus (I2C bus) is a double wired bus developed by Philips. It is
composed of 2 wires: serial clock line (SCL) and serial data line (SDA).
The µPC1853 has built-in I2C bus interface circuit, 9 rewritable registers (8 bits).
SCL (Serial Clock Line)
µ
The master CPU outputs serial clock to synchronize with the data. According to this clock, the
in the serial data.
Input level is compatible with CMOS.
Clock frequency is 0 to 100 kHz.
SDA (Serial Data Line)
µ
The master CPU outputs the data which is synchronized with serial clock. The
PC1853 takes in this data according
to the clock.
Input level is compatible with CMOS.
Fig. 3-1 Internal Equivalent Circuits of Interface Pin
PC1853 takes
SCL
SDA
R
PC1853
µ
P
R
P
3.1 Data Transfer
3.1.1 Start condition
Start condition is made by falling of SDA from “High” to “Low” during SCL is “High” as shown in Fig. 3-2.
When this start condition is received, the
µ
PC1853 takes in the data synchronizing with the clock after that.
17
Page 18
3.1.2 Stop condition
Stop condition is made by rising of SDA from “Low” to “High” during SCL is “High” as shown in Fig. 3-2.
When this stop condition is received, the
µ
PC1853 stops to take in or output the data.
Fig. 3-2 Start/Stop Condition of Data Transfer
3.5 V
SDA
1.5 V
MIN.
3.5 V
µ
s4.0
MIN.
µ
s4.7
µ
PC1853
SCL
START
1.5 V
STOP
3.1.3 Data transfer
In the case of data transfer, data changing should be executed while SCL is “Low” like Fig. 3-3. When SCL is “High”,
be sure not to change the data.
Fig. 3-3 Data Transfer
SDA
Note 1 Note 2
SCL
Note 1. Data hold time for I2C device: 300 ns MIN., Data hold time for CPU: 5 µs MIN.
2. Data set-up time: 250 ns MIN.
Remark Clock frequency: 0 to 100 kHz
3.2 Data Transfer Format
Fig. 3-4 is an example of data transfer in write mode.
18
Page 19
Fig. 3-4 Example of Data Transfer in Write Mode
µ
PC1853
SDA
SCL
Slave address
D6 D5 D4 D3 D2 D1 D0 W
D7 D6 D5 D4 D3 D2 D1 D0D7
ACK
Subaddress
D6 D5 D4 D3 D2 D1 D0
ACK
Data
ACK
Remark W: Write mode, ACK: Acknowledge bit
Data is composed of 8 bits. Acknowledge bit is always added after this 8 bits data. Data should be transferred
from MSB first.
The 1 byte immediately after start condition specifies the slave address (chip address). This slave address is
composed of 7 bits.
µ
Table 3-1 is the slave address of the
PC1853. This slave address is registered by Phillips.
Table 3-1 Slave Address of µPC1853
Bias Voltage of ADS (Pin 22)
5V 1000110
GND 1000100
D6 D5 D4 D3 D2 D1 D0
Slave address
User can set bit D1 freely.
0: Bias voltage of ADS (pin 22) is GND.
1: Bias voltage of ADS (pin 22) is 5 V.
The remaining 1 bit is the read/write bit which specifies the direction of the data transferred after that. Set “0”
µ
because the
PC1853 has write mode only.
The byte following the slave address is subaddress byte of the µPC1853.
µ
PC1853 has 9 subaddresses from SA0 to SA8, and each of them is composed of 8 bits. The data to be set
The
to the subaddress follows this subaddress byte.
µ
PC1853 has automatic increment function. This function increments subaddress automatically in write mode.
The
By using automatic increment function, once slave address and subaddress are set, data can be transferred
continuously to the next subaddress. Use this function for initializing and so on. In the case of changing the data
continuously of one subaddress (adjustment and so on), set the automatic increment function OFF (see 4.4.1(8)
Automatic increment function).
3.2.1 1 byte data transfer
The following is the format in the case of transferring 1 byte data.
S
T
A
SLAVE
ADDRESS
A
C
K
SUB
ADDRESS
W
A
DATA
C
K
A
S
C
T
K
P
Remark STA: Start, W: Write mode, ACK: Acknowledge bit, STP: Stop
19
Page 20
3.2.2 Serial data transfer
The following is the format in the case of transferring 8 bytes data at one time by using automatic increment function
(the data of subaddress 01H to 08H, bit D6 is “1”).
µ
PC1853
S
T
A
SLAVE
ADDRESS
A
C
K
SUB
ADDRESS
W
A
C
DATA1 DATA2 DATA9
K
A
C
K
A
C
K
A
S
C
T
K
P
Remark STA: Start, W: Write mode, ACK: Acknowledge, STP: Stop
The master CPU transfers “00H” as subaddress SA
0 after start and slave address like above figure. It transfers
the data of SA0 after subaddress, and then transfers the data of SA1, SA2..., SA8 continuously without transferring
stop condition. Finally, it transfers stop condition and terminates.
µ
The increments of the subaddress of the
PC1853 stops automatically when the subaddress comes to “08H” inside
of it.
3.2.3 Acknowledge
2
On I
C bus, acknowledge bit is added to the 9th bit after the data in order to judge whether data transfer has been
succeeded or not. The master CPU judges it from “High” and “Low” of acknowledge condition.
When this acknowledge period is “Low”, it means success. And when the condition is “High”, it means failure of
transfer or forced release of bus as NAK state.
The condition of being NAK state is when wrong slave address is transferred to slave IC or data transfer from slave
side is finished in read state.
20
Page 21
(1) µPC1853-01
4. EXPLANATION OF EACH COMMAND
4.1 Subaddress List
21
Bit
Subaddress
00H Rear output Low boost Low boost gain Rear output L+R signal Audio output Main output Audio output
01H 0 Automatic increment Main output volume control
02H 0 Automatic increment Balance control
03H 0 Automatic increment Bass control
04H 0 Automatic increment Treble control
05H 0 Automatic increment L+R signal output volume control
06H 0 Automatic increment Audio output volume control
07H 0 Automatic increment Rear output volume control
08H Surround Automatic increment Units of phase
MSB LSB
D7
selection 0: OFF 0: 6 dB mute output mute mute mute control link
0:
φ
(L-R) 1: ON 1: 3 dB 0: OFF 0: OFF 0: OFF 0: OFF 0: OFF
1: L-R 1: ON 1: ON 1: ON 1: ON 1: ON
0: OFF Attenuation volume : Flat to Low
1: ON Data : 111111 to 000000
0: OFF L-channel attenuation volume : Low to Flat to Flat
1: ON R-channel attenuation volume : Flat to Flat to Low
0: OFF Gain : Boost to 0 dB to Cut
1: ON Data : 111111 to 100000 to 000000
0: OFF Gain : Boost to 0 dB to Cut
1: ON Data : 111111 to 100000 to 000000
0: OFF Attenuation volume : Flat to Low
1: ON Data : 111111 to 000000
0: OFF Attenuation volume : Flat to Low
1: ON Data : 111111 to 000000
0: OFF Attenuation volume : Flat to Low
1: ON Data : 111111 to 000000
ON/OFF 0: OFF shifters selection Effect : Large to Normal to Small
OFF 1: ON 0: 4 units 0: Stereo Data : 1111 to 1000 to 0000
0:
1: ON 1: 1 unit 1: Monaural
D6 D5 D4 D3 D2 D1
Data : 111111 to 100000 to 000000
Monaural/Stereo
Effect control
D0
µ
PC1853
Caution Be sure to write data “0” in the subaddress 01H to 07H, bit D7.
Page 22
22
(2)
µ
PC1853-02
Bit
Subaddress
00H Rear output 0 0 Rear output L+R signal Audio output 0 0
01H 0 Automatic increment R-channel signal output (R1 OUT pin) volume control
02H 0 Automatic increment L-channel signal output (L1 OUT pin) volume control
03H 0 Automatic increment Bass control
04H 0 Automatic increment Treble control
05H 0 Automatic increment L+R signal output volume control
06H 0 Automatic increment Audio output volume control
07H 0 Automatic increment Rear output volume control
08H Surround Automatic increment Units of phase
MSB LSB
D7
selection mute output mute mute
0:
φ
(L-R) 0: OFF 0: OFF 0: OFF
1: L-R 1: ON 1: ON 1: ON
0: OFF Attenuation volume : Flat to Low
1: ON Data : 111111 to 000000
0: OFF Attenuation volume : Flat to Low
1: ON Data : 111111 to 000000
0: OFF Gain : Boost to 0 dB to Cut
1: ON Data : 111111 to 100000 to 000000
0: OFF Gain : Boost to 0 dB to Cut
1: ON Data : 111111 to 100000 to 000000
0: OFF Attenuation volume : Flat to Low
1: ON Data : 111111 to 000000
0: OFF Attenuation volume : Flat to Low
1: ON Data : 111111 to 000000
0: OFF Attenuation volume : Flat to Low
1: ON Data : 111111 to 000000
ON/OFF 0: OFF shifters selection Effect : Large to Normal to Small
OFF 1: ON 0: 4 units 0: Stereo Data : 1111 to 1000 to 0000
0:
1: ON 1: 1 unit 1: Monaural
D6 D5 D4 D3 D2 D1
Monaural/Stereo
Effect control
D0
µ
PC1853
Caution Be sure to fix data of the subaddress 00H, bit D6, D5, D1, D0 and subaddress 01H to 07H, bit D7 to “0”.
Page 23
4.2 Initialization
After power-on, be sure to initialize the subaddress data to table below.
Table 4-1 Initial Data of µPC1853-01
Bit MSB LSB
Subaddress D7 D6 D5 D4 D3 D2 D1 D0
00H 10000000
01H 01111111
02H 01100000
03H 01100000
04H 01100000
05H 01111111
06H 01111111
07H 01111111
08H 01001000
µ
PC1853
Table 4-2 Initial Data of µPC1853-02
Bit MSB LSB
Subaddress D7 D6 D5 D4 D3 D2 D1 D0
00H 10000000
01H 01111111
02H 01111111
03H 01100000
04H 01100000
05H 01111111
06H 01111111
07H 01111111
08H 01001000
Caution Until initializing completely, mute by the external units.
23
Page 24
4.3 Surround Function
About the setting of surround mode, see table below.
Table 4-3 Setting of Surround Mode
Setting Subaddress: 08H Description
Surround
mode ON/OFF phase shifter selection
OFF 0 – – OFF – –
Movie 1 0 0 4 units
Music 1 1 0 ON 1 unit
Simulated 1 0 1 4 units Monaural
–: Don’t care.
Caution When changing the surround mode, use the mute function (approx. 200 ms) for pop noise
reduction (see 4.4.1(2) Mute for the
D7 D5 D4
µ
Surround Units of Monaural/Stereo
Stereo
PC1853-01 or 4.4.2(1) Mute for the µPC1853-02).
µ
PC1853
24
Page 25
µ
PC1853
4.4 Explanation of Each Command
4.4.1 µPC1853-01
(1) Audio Output Control Link
By the data of subaddress 00H, bit D0, audio output volume link can be controlled (linked with main output control
or not).
Fig. 4-1 Audio Output Control Link
Subaddress
00H
D7 D6 D5 D4 D3 D2 D1 D0
Rear
output
selection
Low
boost
Low
boost
gain
Rear
output
mute
L+R
signal
output
mute
Audio
output
mute
Main
output
mute
Audio output control link
0 Audio output volume controlled independently.
Main output volume control (Subaddress: 01H, Bit: D5 to D0)
Audio output volume control (Subaddress: 06H, Bit: D5 to D0)
1 Audio output volume control can be linked with main output volume control.
Main output volume and audio output volume control (Subaddress: 01H, Bit: D5 to D0)
(2) Mute
By the data of subaddress 00H, bit D1 to D4, ON/OFF of mute function can be controlled.
Audio
output
control
link
Audio output
control link
25
Page 26
Fig. 4-2 Mute (µPC1853-01)
µ
PC1853
Subaddress
00H
D7 D6 D5 D4 D3 D2 D1 D0
Rear
output
selection
Low
boost
Low
boost
gain
Rear
output
mute
L+R
signal
output
mute
Audio
output
mute
Main
output
mute
Audio
output
control
link
Main output mute
01Main output not muted
Main output muted
Audio output mute
01Audio output not muted
Audio output muted
L+R signal output mute
01L+R output not muted
L+R output muted
Rear output mute
01Rear output not muted
Rear output muted
Caution Use the mute function (approx. 200 ms) for pop noise reduction when changing the surround
mode and switching power.
(3) Low boost function
By the data of subaddress 00H, bit D5, the low boost gain can be selected (3 dB or 6 dB). And, by the data of
subaddress 00H, bit D6 ON/OFF of the low boost can be controlled.
Fig. 4-3 Low Boost Function
Subaddress
00H
D7 D6 D5 D4 D3 D2 D1 D0
Rear
output
selection
Low
boost
Low
boost
gain
Rear
output
mute
Low boost gain
01Low boost gain: 6 dB
Low boost ON/OFF
01Low boost: OFF
L+R
signal
output
mute
Low boost gain: 3 dB
Low boost: ON
Audio
output
mute
Main
output
mute
Audio
output
control
link
26
Page 27
µ
PC1853
(4) Rear output selection
By the data of subaddress 00H, bit D7, output signal of the rear output pin can be selected (φ (L-R) signal or
(L-R) signal).
µ
Fig. 4-4 Rear Output Selection (
PC1853-01)
Subaddress
00H
D7 D6 D5 D4 D3 D2 D1 D0
Rear
output
selection
Low
boost
Rear output selection
01(L-R) signal: Phase-shifted
Low
boost
gain
φ
(L-R) signal: Not phase-shifted
Rear
output
mute
L+R
signal
output
mute
Audio
output
mute
Main
output
mute
Audio
output
control
link
(5) Volume control
By the data of subaddress 01H, 05H, 06H and 07H, bit D5 to D0, the volume control can be adjusted in 64 levels.
µ
Fig. 4-5 Volume Control (
PC1853-01) (1/2)
• Main output volume control
Subaddress
01H
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
Main output volume control
Main output volume control
Data
D5 ··· D0
111111
Attenuation volume
Flat
• L+R signal output volume control
Subaddress
05H
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
000000
L+R signal output volume control
L+R signal output volume control
Data
D5 ··· D0
111111
000000
Low
Attenuation volume
Flat
Low
27
Page 28
Fig. 4-5 Volume Control (µPC1853-01) (2/2)
µ
PC1853
• Audio output volume control
Subaddress
06H
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
Note
Audio output volume control
Audio output volume control
Data
D5 ··· D0
111111
000000
Attenuation volume
Flat
Low
Note When selecting the mode linking main output volume control to audio output volume control, the audio
output volume can be controlled by the data of main output volume control (see (1) Audio Output
Control Link). In that case, fix the audio output volume control data to “111111”.
• Rear output volume control
Subaddress
07H
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
Rear output volume control
Rear output volume control
Data
D5 ··· D0
111111
000000
Attenuation volume
Flat
Low
(6) Balance control
By the data of subaddress 02H, bit D5 to D0, the balance level of L1 OUT and R1 OUT pin can be adjusted in
64 levels.
Fig. 4-6 Balance Control
Subaddress
02H
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
Balance control
Balance control
Data
D5 ··· D0
111111
100000
000000
L-channel
attenuation
volume
Low
Flat
Flat
R-channel
attenuation
volume
Flat
Flat
Low
28
Page 29
µ
PC1853
(7) Bass and treble control
By the data of subaddress 03H and 04H, bit D5 to D0, the bass and treble tone for main output (L1 OUT and R1
OUT pin) can be adjusted in 64 levels.
Fig. 4-7 Bass and Treble Control
• Bass control
Subaddress
03H
• Treble control
Subaddress
04H
D7 D6 D5 D4 D3 D2 D1 D0
0
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
Automatic
increment
Bass control
Treble control
Bass control
Data
D5 ··· D0
111111
100000
000000
Treble control
Data
D5 ··· D0
111111
100000
000000
Gain
Boost
0 dB
Cut
Gain
Boost
0 dB
Cut
(8) Automatic increment function
By the data of subaddress 01H to 08H, bit D6, ON/OFF of the automatic increment function can be controlled.
Fig. 4-8 Automatic Increment Function
Subaddress
01H to 08H
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
Automatic increment function
Automatic increment function: OFF
0
Automatic increment function: ON
1
Main output volume control
29
Page 30
µ
PC1853
Caution After power-on, be sure to initialize the subaddress data (see 4.2 Initialization).
The automatic increment function increments subaddress automatically.
Automatic increment function is ON : Subaddress is incremented automatically.
If once slave address and subaddress are set, without setting the next
subaddress, data of the next subaddress can be transferred.
Automatic increment function is OFF: Subaddress is fixed.
Data of the fixed subaddress can be set repeatedly.
The automatic increment ON/OFF bit is in the subaddress 01H to 08H. The increment of subaddress is controlled
individually by each automatic increment ON/OFF bit. As for 00H, subaddress is not incremented automatically (see
4.1 Subaddress List).
For example, when the automatic increment function of subaddress 01H is ON and that of 02H is OFF, subaddress
is incremented from 01H to 02H automatically and is fixed on 02H.
In case of the automatic increment function of 08H is ON, subaddress is not incremented. If next data is transferred
after setting data of 08H (acknowledge bit: L), the acknowledge condition is changed into NAK state (acknowledge
bit: H). And the data transfer from the master CPU is stopped.
(9) Effect control
By the data of subaddress 08H, bit D3 to D0, the level of indirect sound signal (surround signal) added to the
original signal can be adjusted in 16 levels.
Fig. 4-9 Effect Control
Subaddress
08H
D7 D6 D5 D4 D3 D2 D1 D0
Surround
ON/OFF
Automatic
increment
Units of
phase
shifters
Monaural/
stereo
selection
Effect control
Effect control
Data
D3 ··· D0
1111
1000
0000
Effect
Large
Normal
Small
(10) Monaural/Stereo selection
By the data of subaddress 08H, bit D4, the surround mode can be selected (stereo mode or simulated mode).
Stereo mode : Surround signal processing for stereo source.
The phase of the difference between L-channel and R-channel signals is shifted and
added to the original signal.
Simulated mode : Stereo sound simulation for monaural source.
The phase of the difference between the signal through HPF and the signal through LPF
is shifted, and the signals are added to the original signal. When the output frequency
characteristics of L-channel and R-channel signals become the form of comb, stereo
sound simulation can be realized.
30
Page 31
Fig. 4-10 Monaural/Stereo Selection
µ
PC1853
Subaddress
08H
D7 D6 D5 D4 D3 D2 D1 D0
Surround
ON/OFF
Automatic
increment
Units of
phase
shifters
Monaural/
stereo
selection
Effect control
Monaural/stereo selection
0
Stereo mode
1
Simulated mode
(11) Units of phase shifters
By the data of subaddress 08H, bit D5, the number of phase shifter’s units (1 or 4 units) can be selected for the
indirect sound signal (surround signal).
Fig. 4-11 Units of Phase Shifters
Subaddress
08H
D7 D6 D5 D4 D3 D2 D1 D0
Surround
ON/OFF
Automatic
increment
Units of
phase
shifters
Monaural/
stereo
selection
Effect control
Units of phase shifers
Phase shifter: 4 units
0
Phase shifter: 1 unit
1
(12) Surround ON/OFF
By the data of subaddress 08H, bit D7, ON/OFF of surround (indirect sound signal) mode can be selected.
Surround OFF : Original signal is taken out directly (OFF mode).
Surround ON : The signal passed through the phase shifter (indirect sound) is added to the original signal
(Movie, Music and Simulated mode).
Fig. 4-12 Surround ON/OFF
Subaddress
08H
D7 D6 D5 D4 D3 D2 D1 D0
Surround
ON/OFF
Automatic
increment
Surround ON/OFF
Surround: OFF
0
1
Surround: ON
Units of
phase
shifters
Monaural/
stereo
selection
Effect control
31
Page 32
4.4.2 µPC1853-02
(1) Mute
By the data of subaddress 00H, bit D2 to D4, ON/OFF of mute function can be controlled.
Fig. 4-13 Mute (µPC1853-02)
µ
PC1853
Subaddress
00H
D7 D6 D5 D4 D3 D2 D1 D0
Rear
output
selection
00 0 0
Rear
output
mute
L+R
signal
output
mute
Audio
output
mute
Audio output mute
Audio output not muted
0
1
Audio output muted
L+R signal output mute
01L+R output not muted
L+R output muted
Rear output mute
01Rear output not muted
Rear output muted
Caution Use the mute function (approx. 200 ms) for pop noise reduction when changing the surround
mode and switching power.
(2) Rear output selection
By the data of subaddress 00H, bit D7, output signal of the rear output pin can be selected (
(L-R) signal).
φ
(L-R) signal or
32
Subaddress
00H
µ
Fig. 4-14 Rear Output Selection (
D7 D6 D5 D4 D3 D2 D1 D0
Rear
output
selection
00 0 0
Rear output selection
0
(L-R) signal: Phase-shifted
φ
1
(L-R) signal: Not phase-shifted
Rear
output
mute
PC1853-02)
L+R
signal
output
mute
Audio
output
mute
Page 33
µ
PC1853
(3) Volume control
By the data of subaddress 01H, 02H, 05H, 06H and 07H, bit D5 to D0, the volume control can be adjusted in 64
levels.
µ
Fig. 4-15 Volume Control (
PC1853-02) (1/2)
• R-channel output volume control
Subaddress
01H
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
• L-channel output volume control
Subaddress
02H
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
R-channel output volume control
R-channel output volume control
Data
D5 ··· D0
111111
000000
L-channel output volume control
L-channel output volume control
Data
D5 ··· D0
111111
R-channel attenuation
volume
Flat
Low
L-channel attenuation
volume
Flat
• L+R signal output volume control
Subaddress
05H
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
000000
L+R signal output volume control
L+R signal output volume control
Data
D5 ··· D0
111111
000000
Low
Attenuation volume
Flat
Low
33
Page 34
Fig. 4-15 Volume Control (µPC1853-02) (2/2)
• Audio output volume control
µ
PC1853
Subaddress
06H
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
• Rear output volume control
Subaddress
07H
D7 D6 D5 D4 D3 D2 D1 D0
0
Automatic
increment
Audio output volume control
Audio output volume control
Data
D5 ··· D0
111111
000000
Rear output volume control
Rear output volume control
Data
D5 ··· D0
111111
Attenuation volume
Flat
Low
Attenuation volume
Flat
(4) Bass and treble control
See 4.4.1 (7) Bass and treble control.
(5) Automatic increment function
See 4.4.1 (8) Automatic increment function.
(6) Effect control
See 4.4.1 (9) Effect control.
(7) Monaural/Stereo selection
See 4.4.1 (10) Monaural/Stereo selection.
(8) Units of phase shifters
See 4.4.1 (11) Units of phase shifters.
(9) Surround ON/OFF
See 4.4.1 (12) Surround ON/OFF.
000000
Low
34
Page 35
µ
PC1853
5. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (Unless otherwise specified, TA = 25 ˚C)
Parameter Symbol Test conditions Ratings Unit
Supply voltage VCC No signal 14.0 V
Input signal voltage VIN VCC V
I2C bus input pin voltage Vcont VCC + 0.2 V
Power dissipation PD TA = 75 ˚C 500 mW
Operating temperature TA VCC = 12 V –20 to +75 ˚ C
Storage temperature Tstg –40 to +125 ˚C
Recommended Operating Conditions (Unless otherwise specified, TA = 25 ˚C)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Supply voltage VCC 10.8 12.0 13.2 V
Input signal voltage VIN VCC = 12 V, 0.0 1.4 7.9 Vp-p
Gain of input-output: 0 dB
I2C bus input pin voltage (H) VcontH Pins SDA and SCL 3.5 5.0 6.0 V
I2C bus input pin voltage (L) VcontL 0.0 0.0 1.5 V
35
Page 36
36
Electrical Characteristics
(V
CC = 12 V, TA = 25 ˚C, RH ≤ 70 %, f = 1 kHz, V
General (1/1)
IN
= 0.5 Vrms, No load impedance, unless otherwise specified)
Parameter Symbol Test conditions
Switch mode
Note
Subaddress data
MIN. TYP. MAX. Unit
S1 S2 S3 00 01 02 03 04 05 06 07 08
Supply current I
Maximum input voltage 1 VOM1 Lin, Rin ≥ 2.8 V
CC No signal b b – 80 7F 60 60 60 7F 7F 7F 48 16 24 32 mA
rms, a a – 80 7F 60 60 60 7F 7F 7F 48 7.9 8.8 9.3 V
THD = 1 %,
L1 OUT, R1 OUT,
L2 OUT, R2 OUT,
L+R OUT
Maximum input voltage 2 VOM2 Lin ≥ 2.8 V
rms, Rin = GND, a b – 2.5 2.8 3.3 V
THD = 1 %,
Rear OUT
Distortion rate (L-ch) THDL f = 1 kHz, a b – 80 7F 60 60 60 7F 7F 7F 48 – 0.1 0.5 %
Lin = 0.5 V
rms,
Rin = GND,
L1 OUT, L2 OUT
Distortion rate (R-ch) THDR f = 1 kHz, b a – – 0.1 0.5 %
Lin = GND,
p-p
p-p
Rin = 0.5 V
rms,
R1 OUT, R2 OUT
–: Don’t care.
Note See 7. MEASURING CIRCUIT.
Remark The values are common to both the µPC1853CT-01 and
µ
PC1853CT-02.
µ
PC1853
Page 37
(1) µPC1853CT-01 Volume control, tone control block (1/3)
Parameter Symbol Test conditions
Volume attenuation 1 (1) ATT
Volume attenuation 1 (2) ATT
Volume attenuation 1 (3) ATT
Volume attenuation 2 (1) ATT
Volume attenuation 2 (2) ATT
Volume attenuation 2 (3) ATT
L+R volume attenuation 1 ATT
L+R volume attenuation 2 ATT
L+R volume attenuation 3 ATT
Rear volume attenuation 1 ATT
Rear volume attenuation 2 ATT
Balance attenuation (L-ch) 1 (1) ATT
Balance attenuation (L-ch) 1 (2) ATT
Balance attenuation (L-ch) 1 (3) ATT
Balance attenuation (R-ch) 1 (1) ATT
Balance attenuation (R-ch) 1 (2) ATT
Balance attenuation (R-ch) 1 (3) ATT
Low-band boost control V
Low-band flat control V
Low-band cut control V
Low-band boost control (6 dB) 1 V
Low-band boost control (6 dB) 2 V
Low-band boost control (6 dB) 3 V
BB
BF
BC
B6dB1
B6dB2
B6dB3
Switch mode
S1 S2 S3 00 01 02 03 04 05 06 07 08
VL11
Lin = 0.5 Vrms, Rin = GND, a b – 80 7F 60 60 60 7F 7F 7F 48 –1.5 0.0 +1.5 dB
VL12
L1 OUT 60 –25.0 –19.0 –13.0 dB
VL13
VL21
Lin = 0.5 Vrms, Rin = GND, a b – 80 7F 60 60 60 7F 7F 7F 48 –1.5 0.0 +1.5 dB
VL22
L2 OUT 60 –25.0 –19.0 –13.0 dB
VL23
VLR1
Lin = 0.5 Vrms, Rin = 0.5 V
VLR2
L+R OUT 60 –25.0 –19.0 –13.0 dB
VLR3
VRE1
Lin = 0.5 Vrms, Rin = GND, a b – 80 7F 60 60 60 7F 7F 7F 48 8.5 10.0 11.5 dB
VRE2
Rear OUT 60 –15.0 –9.0 –3.0 dB
BL11
Lin = 0.5 Vrms, Rin = GND, a b – 80 7F 41 60 60 7F 7F 7F 48 –1.5 0.0 +1.5 dB
BL12
L1 OUT 60 –1.5 0.0 +1.5 dB
BL13
BR11
Lin = GND, Rin = 0.5 V
BR12
R1 OUT 60 –1.5 0.0 +1.5 dB
BR13
f = 100 Hz, Lin = 0.5 V
rms, a a – 80 7F 60 60 60 7F 7F 7F 48 –1.5 0.0 +1.5 dB
rms, b a – 80 7F 41 60 60 7F 7F 7F 48 –80.0 – – dB
rms, a b – 80 7F 60 7F 60 7F 7F 7F 48 7.0 10.0 13.0 dB
Note
Subaddress data
MIN. TYP. MAX. Unit
40 –80.0 – – dB
40 –80.0 – – dB
40 –80.0 – – dB
7F –80.0 – – dB
7F –1.5 0.0 +1.5 dB
Rin = GND, L1 OUT 60 –3.0 0.0 +3.0 dB
41 –13.0 –10.0 –7.0 dB
f = 100 Hz, Lin = 0.5 V
rms, a b – 80 7F 60 60 60 7F 7F 7F 48 2.0 3.0 4.0 dB
Rin = GND, L1 OUT ↓ 60 3.0 4.0 5.0 dB
C0 50 4.0 6.0 8.0 dB
µ
PC1853
37
–: Don’t care.
Note See 7. MEASURING CIRCUIT.
Page 38
38
(1)
µ
PC1853CT-01 Volume control, tone control block (2/3)
Parameter Symbol Test conditions
Low-band boost control (3 dB) 1 V
Low-band boost control (3 dB) 2 V
Low-band boost control (3 dB) 3 V
High-band boost control V
High-band flat control V
High-band cut control V
L, R in-phase gain difference 1 (1) DG
L, R in-phase gain difference 1 (2) DG
L, R in-phase gain difference 2 (1) DG
L, R in-phase gain difference 2 (2) DG
L, R in-phase gain difference 3 (1) DG
L, R in-phase gain difference 3 (2) DG
L, R in-phase gain difference 3 (3) DG
L, R in-phase gain difference 4 (1) DG
L, R in-phase gain difference 4 (2) DG
L, R in-phase gain difference 4 (3) DG
L, R in-phase gain difference 5 (1) DG
L, R in-phase gain difference 5 (2) DG
L, R in-phase gain difference 5 (3) DG
L, R in-phase gain difference 6 (1) DG
L, R in-phase gain difference 6 (2) DG
L, R in-phase gain difference 6 (3) DG
Switch mode
S1 S2 S3 00 01 02 03 04 05 06 07 08
B3dB1 f = 100 Hz, Lin = 0.5 V
B3dB2 Rin = GND, L1 OUT ↓ 60 1.0 2.0 3.0 dB
B3dB3
TB f = 10 kHz, Lin = 0.5 V
TF Rin = GND, L1 OUT 60 –3.0 0.0 +3.0 dB
TC
11 Lin = GND, Rin = 0.5 V
12 L1 OUT, R1 OUT 60 –1.0 0.0 +1.0 dB
21 Lin = GND, Rin = 0.5 V
22 L2 OUT, R2 OUT 60 –1.0 0.0 +1.0 dB
31 f = 100 Hz, Lin = 0.5 V
32 Rin = 0.5 V
33 L1 OUT, R1 OUT 41 –1.0 0.0 +1.0 dB
41 f = 10 kHz, Lin = 0.5 V
42 Rin = 0.5 V
43 L1 OUT, R1 OUT 41 –1.0 0.0 +1.0 dB
51 f = 100 Hz, Lin = 0.5 V
52 Rin = 0.5 V
53 L1 OUT, R1 OUT C0 48 –1.0 0.0 +1.0 dB
61 f = 100 Hz, Lin = 0.5 V
62 Rin = 0.5 V
63 L1 OUT, R1 OUT E0 48 –1.0 0.0 +1.0 dB
rms, 60 –1.0 0.0 +1.0 dB
rms, 60 –1.0 0.0 +1.0 dB
rms, ↓ 60 –1.0 0.0 +1.0 dB
rms, ↓ 60 –1.0 0.0 +1.0 dB
rms, a b – A0 7F 60 60 60 7F 7F 7F 48 0.5 1.5 2.5 dB
rms, a b – 80 7F 60 60 7F 7F 7F 7F 48 7.0 10.0 13.0 dB
rms, b a – 80 7F 60 60 60 7F 7F 7F 48 –1.0 0.0 +1.0 dB
rms, b a – 80 7F 60 60 60 7F 7F 7F 48 –1.0 0.0 +1.0 dB
rms, a a – 80 7F 60 7F 60 7F 7F 7F 48 –1.0 0.0 +1.0 dB
rms, a a – 80 7F 60 60 7F 7F 7F 7F 48 –1.0 0.0 +1.0 dB
rms, a a – 80 7F 60 60 60 7F 7F 7F 48 –1.0 0.0 +1.0 dB
rms, a a – A0 7F 60 60 60 7F 7F 7F 48 –1.0 0.0 +1.0 dB
Note
Subaddress data
MIN. TYP. MAX. Unit
E0 50 2.0 3.0 4.0 dB
41 –13.0 –10.0 –7.0 dB
–: Don’t care.
Note See 7. MEASURING CIRCUIT.
µ
PC1853
Page 39
(1)
µ
PC1853CT-01 Volume control, tone control block (3/3)
Note
Subaddress data
MIN. TYP. MAX. Unit
Parameter Symbol Test conditions
Muting attenuation 1 Mute 1 Lin = 0.5 V
Switch mode
S1 S2 S3 00 01 02 03 04 05 06 07 08
rms, a b – 82 7F 60 60 60 7F 7F 7F 48 –80.0 – – dB
Rin = GND, L1 OUT
Muting attenuation 2 Mute 2 Lin = GND, b a – –80.0 – – dB
Rin = 0.5 V
rms, R1 OUT
Muting attenuation 3 Mute 3 Lin = 0.5 Vrms, a b – 84 –80.0 – – dB
Rin = GND, L2 OUT
Muting attenuation 4 Mute 4 Lin = GND, b a – –80.0 – – dB
Rin = 0.5 V
rms, R2 OUT
Muting attenuation 5 Mute 5 Lin = 0.5 Vrms, a a – 88 –80.0 – – dB
Rin = 0.5 V
rms, L+R OUT
Muting attenuation 6 Mute 6 Lin = 0.5 Vrms, a b – 90 –70.0 – – dB
(Rear) Rin = GND, Rear OUT
DC offset at muting mode VOS1 No signal b b – 80 7F 60 60 60 7F 7F 7F 48 –50 0 +50 mV
(L1 OUT, R1 OUT) 82
DC offset at muting mode V
OS2
(L2 OUT, R2 OUT) 84
DC offset at muting mode V
OS3
(L+R OUT) 88
DC offset at muting mode V
OS4
(Rear OUT) 90
↓
80 –50 0 +50 mV
↓
80 –50 0 +50 mV
↓
80 –50 0 +50 mV
↓
39
–: Don’t care.
Note See 7. MEASURING CIRCUIT.
µ
PC1853
Page 40
40
(2)
µ
PC1853CT-02 Volume control, tone control block (1/2)
Parameter Symbol Test conditions
Volume attenuation 1 (1) L-ch ATT
Volume attenuation 1 (2) L-ch ATT
Volume attenuation 1 (3) L-ch ATT
Volume attenuation 1 (4) R-ch ATT
Volume attenuation 1 (5) R-ch ATT
Volume attenuation 1 (6) R-ch ATT
Volume attenuation 2 (1) ATT
Volume attenuation 2 (2) ATT
Volume attenuation 2 (3) ATT
L+R volume attenuation 1 ATT
L+R volume attenuation 2 ATT
L+R volume attenuation 3 ATT
Rear volume attenuation 1 ATT
Rear volume attenuation 2 ATT
Low-band boost control V
Low-band flat control V
Low-band cut control V
High-band boost control V
High-band flat control V
High-band cut control V
BB f = 100 Hz, Lin = 0.5 V
BF Rin = GND, L1 OUT 60 –3.0 0.0 +3.0 dB
BC
TB f = 100 kHz, Lin = 0.5 V
TF Rin = GND, L1 OUT 60 –3.0 0.0 +3.0 dB
TC
L, R in-phase gain difference 1 (1) DG
L, R in-phase gain difference 1 (2) DG
L, R in-phase gain difference 2 (1) DG
L, R in-phase gain difference 2 (2) DG
Switch mode
S1 S2 S3 00 01 02 03 04 05 06 07 08
VL11 Lin = 0.5 V
VL12 Rin = GND, 60 –25.0 –19.0 –13.0 dB
VL13 L1 OUT 40 –80.0 – – dB
VR14 Lin = GND, a b – 80 7F 7F 60 60 7F 7F 7F 48 –1.5 0.0 +1.5 dB
VR15 Rin = 0.5 V
VR16
VL21 Lin = 0.5 V
VL22 L2 OUT 60 –25.0 –19.0 –13.0 dB
VL23
VLR1 Lin = 0.5 V
VLR2 L+R OUT 60 –25.0 –19.5 –13.0 dB
VLR3
VRE1 Lin = 0.5 V
VRE2 Rear OUT 60 –15.0 –9.0 –3.0 dB
rms, a b – 80 7F 7F 60 60 7F 7F 7F 48 –1.5 0.0 +1.5 dB
rms, R1 OUT 60 –25.0 –19.0 –13.0 dB
rms, Rin = GND, a b – 80 7F 7F 60 60 7F 7F 7F 48 –1.5 0.0 +1.5 dB
rms, Rin = 0.5 V
rms, Rin = GND, a b – 80 7F 7F 60 60 7F 7F 7F 48 8.5 10.0 11.5 dB
rms, a a – 80 7F 7F 60 60 7F 7F 7F 48 –1.5 0.0 +1.5 dB
rms, a b – 80 7F 7F 7F 60 7F 7F 7F 48 7.0 10.0 13.0 dB
Note
Subaddress data
MIN. TYP. MAX. Unit
40 –80.0 – – dB
40 –80.0 – – dB
40 –80.0 – – dB
41 –13.0 –10.0 –7.0 dB
rms
, a b – 80 7F 7F 60 7F 7F 7F 7F 48 7.0 10.0 13.0 dB
41 –13.0 –10.0 –7.0 dB
11 Lin = GND, Rin = 0.5 V
12 L1 OUT, R1 OUT 60 60 –1.5 0.0 +1.5 dB
21 Lin = GND, Rin = 0.5 V
22 L2 OUT, R2 OUT 60 –1.0 0.0 +1.0 dB
rms, b a – 80 7F 7F 60 60 7F 7F 7F 48 –1.0 0.0 +1.0 dB
rms
, b a – 80 7F 7F 60 60 7F 7F 7F 48 –1.0 0.0 +1.0 dB
µ
PC1853
–: Don’t care.
Note See 7. MEASURING CIRCUIT.
Page 41
(2) µPC1853CT-02 Volume control, tone control block (2/2)
Note
Subaddress data
MIN. TYP. MAX. Unit
Parameter Symbol Test conditions
L, R in-phase gain difference 3 (1) DG
L, R in-phase gain difference 3 (2) DG
L, R in-phase gain difference 3 (3) DG
L, R in-phase gain difference 4 (1) DG
L, R in-phase gain difference 4 (2) DG
L, R in-phase gain difference 4 (3) DG
Switch mode
S1 S2 S3 00 01 02 03 04 05 06 07 08
31
f = 100 Hz, Lin = 0.5 V
32
Rin = 0.5 Vrms, 60 –1.0 0.0 +1.0 dB
33
L1 OUT, R1 OUT 41 –1.0 0.0 +1.0 dB
41
f = 10 kHz, Lin = 0.5 V
42
Rin = 0.5 Vrms, 60 –1.0 0.0 +1.0 dB
43
L1 OUT, R1 OUT 41 –1.0 0.0 +1.0 dB
rms, a a – 80 7F 7F 7F 60 7F 7F 7F 48 –1.0 0.0 +1.0 dB
rms, a a – 80 7F 7F 60 7F 7F 7F 7F 48 –1.0 0.0 +1.0 dB
Muting attenuation 1 Mute 1 Lin = 0.5 Vrms, a b – 84 7F 7F 60 60 7F 7F 7F 48 –80.0 – – dB
Rin = GND, L2 OUT
Muting attenuation 2 Mute 2 Lin = GND, b a – –80.0 – – dB
Rin = 0.5 Vrms, R2 OUT
Muting attenuation 3 Mute 3 Lin = 0.5 Vrms, a a – 88 –80.0 – – dB
Rin = 0.5 Vrms, L+R OUT
Muting attenuation 4 Mute 4 Lin = 0.5 Vrms, a b – 90 –70.0 – – dB
(Rear) Rin = GND, Rear OUT
DC offset at muting mode VOS1
(L1 OUT, R1 OUT) 82
DC offset at muting mode V
OS2
(L2 OUT, R2 OUT) 84
DC offset at muting mode V
OS3
(L+R OUT) 88
DC offset at muting mode V
OS4
(Rear OUT) 90
No signal b b – 80 7F 7F 60 60 7F 7F 7F 48 –50 0 +50 mV
↓
80 –50 0 +50 mV
↓
80 –50 0 +50 mV
↓
80 –50 0 +50 mV
↓
µ
PC1853
41
–: Don’t care.
Note See 7. MEASURING CIRCUIT.
Page 42
42
Matrix surround block (1/2)
Parameter Symbol Test conditions
In-phase gain G
Movie mode 1
Note2
MOV1 f = 1 kHz, Lin = 0.5 V
Rin = GND, L1 OUT
In-phase gain GMOV2 f = 1 kHz, Lin = 0.5 V
Movie mode 2
Note2
Rin = GND, R1 OUT
In-phase gain GMUS1 f = 1 kHz, Lin = 0.5 V
Music mode 1
Note2
Rin = GND, L1 OUT
In-phase gain GMUS2 f = 1 kHz, Lin = 0.5 V
Music mode 2
Note2
Rin = GND, R1 OUT
In-phase gain GSIML1 f = 250 Hz, Lin = 0.5 V
Simulated mode (L-ch) 1
In-phase gain G
Simulated mode (L-ch) 2
In-phase gain G
Simulated mode (L-ch) 3
In-phase gain G
Simulated mode (R-ch) 1
In-phase gain G
Simulated mode (R-ch) 2
In-phase gain G
Simulated mode (R-ch) 3
Note2
Note2
Note2
Note2
Note2
Note2
Rin = 0.5 V
SIML2 f = 1 kHz, Lin = 0.5 V
Rin = 0.5 V
SIML3 f = 4 kHz, Lin = 0.5 V
Rin = 0.5 V
SIMR1 f = 250 Hz, Lin = 0.5 V
Rin = 0.5 V
SIMR2 f = 1 kHz, Lin = 0.5 V
Rin = 0.5 V
SIMR3 f = 4 kHz, Lin = 0.5 V
Rin = 0.5 V
rms, L1 OUT
rms, L1 OUT
rms, L1 OUT
rms, R1 OUT
rms, R1 OUT
rms, R1 OUT
Switch mode
S1 S2 S3 00 01 02 03 04 05 06 07 08
rms
, a b – 80 7F 60 60 60 7F 7F 7F C8 3.0 7.0 11.0 dB
rms
, 0.0 4.0 8.0 dB
rms
, E8 3.5 5.5 7.5 dB
rms
, –2.5 –0.5 +1.5 dB
rms, a a – D8 –0.5 +3.5 +6.5 dB
rms, – –3.0 +4.5 dB
rms
, 2.0 6.0 10.0 dB
rms, D8 – –5.5 –1.0 dB
rms
, 0.0 3.0 6.0 dB
rms, – –7.0 +5.0 dB
Note1
Subaddress data
MIN. TYP. MAX. Unit
–: Don’t care.
Note 1. See 7. MEASURING CIRCUIT.
2. See 4.3 Surround Function about setting of surround mode.
µ
Remark The values are common to both the
PC1853CT-01 and
µ
PC1853CT-02.
µ
PC1853
Page 43
Matrix surround block (2/2)
Parameter Symbol Test conditions
Output noise NO1 Lin = GND, Rin = GND, b b – 80 7F 60 60 60 7F 7F 7F 48 – 25 50
Surround: OFF, DIN-AUDIO filter,
L1 OUT, R1 OUT, L2 OUT,
R2 OUT, L+R OUT, Rear OUT
Crosstalk 1 CT1 Lin = 0.5 V
0 dB: 0.5 V
Crosstalk 2 CT2 Lin = GND, Rin = 0.5 V
0 dB: 0.5 V
Inter-mode offset V
OSM
No signal. b b – 80 7F 60 60 60 7F 7F 7F ×F –50 0 +50 mV
At surround mode switching.
rms, Rin = GND, a b – 80 7F 60 60 60 7F 7F 7F 48 – –80 –70 dB
rms
rms, b a – – –80 –70 dB
rms
Switch mode
S1 S2 S3 00 01 02 03 04 05 06 07 08
Note
Subaddress data
MIN. TYP. MAX. Unit
–: Don’t care.
Note See 7. MEASURING CIRCUIT.
µ
Remark The values are common to both the
PC1853CT-01 and
µ
PC1853CT-02.
µ
Vrms
43
µ
PC1853
Page 44
44
ELECTRICAL CHARACTERISTICS MEASUREMENT LIST
Set subaddress data as shown in 4.2 Initialization unless otherwise specified.
General (1/1)
Parameter Symbol Test conditions Subaddress
Supply current I
Maximum input voltage 1 V
Maximum input voltage 2 V
Distortion rate (L-ch) THD
Distortion rate (R-ch) THD
CC
OM1
OM2
L
R
Remark The methods are common to both the
Current flowing to pin 15.
No signal
Input signal level of pins 13, 14, 16 and 17.
Distortion rate of pins 13, 14, 16 and 17: 1 %
Pins 26 and 27: Input SIN wave (1 kHz, 2.8 V
rms).
Input signal level of pin 11.
Distortion rate of pin 11: 1 %
Pin 26: Input SIN wave (1 kHz, 2.8 V
rms).
Pin 27: No signal
Distortion rate of pins 14 and 17.
Pin 26: Input SIN wave (1 kHz, 0.5 V
rms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Distortion rate of pins 13 and 16.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
µ
PC1853CT-01 and
µ
PC1853CT-02.
rms).
Data
D7 D6 D5 D4 D3 D2 D1 D0
µ
PC1853
Page 45
(1)
µ
PC1853CT-01 Volume control, tone control block (1/9)
Parameter Symbol Test conditions Subaddress
Volume attenuation 1 (1) ATT
VL11
Volume attenuation = 20 log
L input
L1 output 01 01111111
D7 D6 D5 D4 D3 D2 D1 D0
Volume attenuation 1 (2) ATTVL12 L1 output: Output signal level of pin 14. 01100000
L input: Input signal level of pin 26.
Data
Volume attenuation 1 (3) ATTVL13 Pin 26: Input SIN wave (1 kHz, 0.5 V
rms
). 01000000
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Volume attenuation 2 (1) ATTVL21
Volume attenuation = 20 log
L input
L2 output 06 01111111
Volume attenuation 2 (2) ATTVL22 L2 output: Output signal level of pin 17. 01100000
L input: Input signal level of pin 26.
Volume attenuation 2 (3) ATTVL23 Pin 26: Input SIN wave (1 kHz, 0.5 V
rms
). 01000000
Pin 27: No signal (Connect to GND with an input coupling capacitor).
L+R volume attenuation 1 ATTVLR1
L+R volume attenuation = 20 log
L, R input
L+R output 05 01111111
L+R volume attenuation 2 ATTVLR2 L+R output: Output signal level of pin 12. 01100000
L, R input: Input signal level of pin 26 or 27.
L+R volume attenuation 3 ATTVLR3 Pin 26, 27: Input SIN wave (1 kHz, 0.5 V
rms). 01000000
45
Rear volume attenuation 1 ATT
VRE1
Rear volume attenuation = 20 log
L input
Rear output 07 01111111
Rear output: Output signal level of pin 11.
Rear volume attenuation 2 ATTVRE2 L input: Input signal level of pin 26. 01100000
Pin 26: Input SIN wave (1 kHz, 0.5 V
rms
).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
µ
PC1853
Page 46
46
(1) µPC1853CT-01 Volume control, tone control block (2/9)
Parameter Symbol Test conditions Subaddress
Balance attenuation (L-ch) 1 (1) ATT
BL11
Balance attenuation = 20 log
L input
L1 output 02 01000001
D7 D6 D5 D4 D3 D2 D1 D0
Balance attenuation (L-ch) 1 (2) ATTBL12 L1 output: Output signal level of pin 14. 01100000
L input: Input signal level of pin 26.
Data
Balance attenuation (L-ch) 1 (3) ATTBL13 Pin 26: Input SIN wave (1 kHz, 0.5 V
rms). 01111111
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Balance attenuation (R-ch) 1 (1) ATTBR11
Balance attenuation = 20 log
R input
R1 output 02 01000001
Balance attenuation (R-ch) 1 (2) ATTBR12 R1 output: Output signal level of pin 13. 01100000
R input: Input signal level of pin 27.
Balance attenuation (R-ch) 1 (3) ATTBR13 Pin 26: No signal (Connect to GND with an input coupling capacitor). 01111111
Low-band boost control V
Low-band flat control V
Pin 27: Input SIN wave (1 kHz, 0.5 V
BB
BF
Bass response = 20 log
L input
L1 output: Output signal level of pin 14. 01100000
L1 output 03 01111111
rms).
L input: Input signal level of pin 26.
Low-band cut control V
BC
Pin 26: Input SIN wave (100 Hz, 0.5 V
rms). 01000001
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Low-band boost control (6 dB) 1 V
B6dB1
Bass response = 20 log
V
V
BON
BOFF
00 10000000
↓
1
VBON: Output signal level of pin 14 (Low boost: ON). 01 01111111
Low-band boost control (6 dB) 2 V
B6dB2
VBOFF: Output signal level of pin 14 (Low boost: OFF). 00 10000000
Pin 26: Input SIN wave (100 Hz, 0.5 V
rms). 1
↓
Pin 27: No signal (Connect to GND with an input coupling capacitor). 01 01100000
µ
PC1853
Page 47
(1) µPC1853CT-01 Volume control, tone control block (3/9)
Parameter Symbol Test conditions Subaddress
Low-band boost control (6 dB) 3 V
Low-band boost control (3 dB) 1 V
Low-band boost control (3 dB) 2 V
Low-band boost control (3 dB) 3 V
High-band boost control V
High-band flat control V
High-band cut control V
B6dB3
B3dB1
B3dB2
B3dB3
TB
TF
TC
Data
D7 D6 D5 D4 D3 D2 D1 D0
V
Bass response = 20 log
V
BON : Output signal level of pin 14 (Low boost: ON).
V
BON
BOFF
00 10000000
↓
1
VBOFF: Output signal level of pin 14 (Low boost: OFF).
Pin 26: Input SIN wave (100 Hz, 0.5 V
rms).
Pin 27: No signal (Connect to GND with an input coupling capacitor). 01 01010000
Bass response = 20 log
V
BON
BOFF
00 10100000
↓
1
V
VBON : Output signal level of pin 14 (Low boost: ON). 01 01111111
VBOFF: Output signal level of pin 14 (Low boost: OFF). 00 10100000
Pin 26: Input SIN wave (100 Hz, 0.5 V
rms). 1
↓
Pin 27: No signal (Connect to GND with an input coupling capacitor). 01 01100000
00 10100000
↓
1
01 01010000
L1 output 04 01111111
Treble response = 20 log
L input
L1 output: Output signal level of pin 14. 01100000
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (10 kHz, 0.5 V
rms). 01000001
Pin 27: No signal (Connect to GND with an input coupling capacitor).
47
µ
PC1853
Page 48
48
(1)
µ
PC1853CT-01 Volume control, tone control block (4/9)
Parameter Symbol Test conditions Subaddress
L, R in-phase gain difference 1 (1) DG
L, R in-phase gain difference 1 (2) DG
L, R in-phase gain difference 2 (1) DG
L, R in-phase gain difference 2 (2) DG
11
Channel to channel error = 20 log
R input
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
VL11
: Gain of the Volume attenuation 1 (1).
ATT
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
12
Channel to channel error = 20 log
R input
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
VL12
: Gain of the Volume attenuation 1 (2).
ATT
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
21
Channel to channel error = 20 log
R input
R2 output: Output signal level of pin 16.
R input: Input signal level of pin 27.
VL21
: Gain of the Volume attenuation 2 (1).
ATT
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
22
Channel to channel error = 20 log
R input
R2 output: Output signal level of pin 16.
R input: Input signal level of pin 27.
VL22
: Gain of the Volume attenuation 2 (2).
ATT
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
R1 output
rms
).
R1 output
rms
).
R2 output
rms
).
R2 output
rms
).
– ATT
– ATT
– ATT
– ATT
Data
D7 D6 D5 D4 D3 D2 D1 D0
01 01111111
VL11
01100000
VL12
06 01111111
VL21
01100000
VL22
µ
PC1853
Page 49
(1) µPC1853CT-01 Volume control, tone control block (5/9)
49
Parameter Symbol Test conditions Subaddress
L, R in-phase gain difference 3 (1) DG
L, R in-phase gain difference 3 (2) DG
L, R in-phase gain difference 3 (3) DG
L, R in-phase gain difference 4 (1) DG
Data
D7 D6 D5 D4 D3 D2 D1 D0
31
Channel to channel error = 20 log
R input
R1 output
– V
BB
03 01111111
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
BB: Gain of the Low-band boost control.
V
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 V
32
Channel to channel error = 20 log
R input
R1 output
rms).
– V
BF
01100000
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
BF: Gain of the Low-band flat control.
V
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 V
33
Channel to channel error = 20 log
R input
R1 output
rms).
– V
BC
01000001
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
BC: Gain of the Low-band cut control.
V
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 V
41
Channel to channel error = 20 log
R input
R1 output
R1 output: Output signal level of pin 13.
rms).
– V
TB
05 01111111
µ
PC1853
R input: Input signal level of pin 27.
TB: Gain of the High-band boost control.
V
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (10 kHz, 0.5 V
rms).
Page 50
50
(1)
µ
PC1853CT-01 Volume control, tone control block (6/9)
Parameter Symbol Test conditions Subaddress
L, R in-phase gain difference 4 (2) DG
L, R in-phase gain difference 4 (3) DG
L, R in-phase gain difference 5 (1) DG
L, R in-phase gain difference 5 (2) DG
Data
D7 D6 D5 D4 D3 D2 D1 D0
42
Channel to channel error = 20 log
R input
R1 output
– V
TF
05 01100000
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
TF: Gain of the High-band flat control.
V
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (10 kHz, 0.5 V
43
Channel to channel error = 20 log
R input
R1 output
rms).
– V
TC
01000001
R1 output: Output signal level of pin 13.
R input: Input signal level of pin 27.
TC: Gain of the High-band cut control.
V
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (10 kHz, 0.5 V
51
Channel to channel error = 20 log
V
BON : Output signal level of pin 13 (Low boost: ON). 1
V
VBOFF
: Output signal level of pin 13 (Low boost: OFF).
B6dB1
V
: Gain of the Low-band boost control (6 dB) 1.
V
BON
BOFF
rms).
– V
B6dB1
00 10000000
↓
Pin 26: No signal (Connect to GND with an input coupling capacitor). 01 01111111
Pin 27: Input SIN wave (100 Hz, 0.5 V
52
Channel to channel error = 20 log
V
BON : Output signal level of pin 13 (Low boost: ON). 1
V
VBOFF
: Output signal level of pin 13 (Low boost: OFF).
B6dB2
V
: Gain of the Low-band boost control (6 dB) 2.
V
BON
BOFF
rms).
– V
B6dB2
00 10000000
↓
µ
PC1853
Pin 26: No signal (Connect to GND with an input coupling capacitor). 01 01100000
Pin 27: Input SIN wave (100 Hz, 0.5 V
rms).
Page 51
(1) µPC1853CT-01 Volume control, tone control block (7/9)
51
Parameter Symbol Test conditions Subaddress
L, R in-phase gain difference 5 (3) DG
L, R in-phase gain difference 6 (1) DG
L, R in-phase gain difference 6 (2) DG
L, R in-phase gain difference 6 (3) DG
Data
D7 D6 D5 D4 D3 D2 D1 D0
53
Channel to channel error = 20 log
V
BON : Output signal level of pin 13 (Low boost: ON). 1
V
V
BON
BOFF
– VB6dB3
00 10000000
↓
VBOFF : Output signal level of pin 13 (Low boost: OFF).
VB6dB3: Gain of the Low-band boost control (6 dB) 3.
Pin 26: No signal (Connect to GND with an input coupling capacitor). 01 01001000
Pin 27: Input SIN wave (100 Hz, 0.5 V
61
Channel to channel error = 20 log
V
BON : Output signal level of pin 13 (Low boost: ON). 1
V
V
BON
BOFF
rms).
– VB3dB1
00 10100000
↓
VBOFF: Output signal level of pin 13 (Low boost: OFF).
VB3dB1: Gain of the Low-band boost control (3 dB) 1.
Pin 26: No signal (Connect to GND with an input coupling capacitor). 01 01111111
Pin 27: Input SIN wave (100 Hz, 0.5 V
62
Channel to channel error = 20 log
V
BON : Output signal level of pin 13 (Low boost: ON). 1
V
V
BON
BOFF
rms).
– VB3dB2
00 10100000
↓
VBOFF: Output signal level of pin 13 (Low boost: OFF).
VB3dB2: Gain of the Low-band boost control (3 dB) 2.
Pin 26: No signal (Connect to GND with an input coupling capacitor). 01 01100000
Pin 27: Input SIN wave (100 Hz, 0.5 V
63
Channel to channel error = 20 log
V
BON : Output signal level of pin 13 (Low boost: ON). 1
V
V
BON
BOFF
rms).
– VB3dB3
00 10100000
↓
µ
PC1853
VBOFF : Output signal level of pin 13 (Low boost: OFF).
VB3dB3: Gain of the Low-band boost control (3 dB) 3.
Pin 26: No signal (Connect to GND with an input coupling capacitor). 01 01001000
Pin 27: Input SIN wave (100 Hz, 0.5 V
rms).
Page 52
52
(1) µPC1853CT-01 Volume control, tone control block (8/9)
Parameter Symbol Test conditions Subaddress
Muting attenuation 1 Mute 1
Muting attenuation 2 Mute 2
Muting attenuation 3 Mute 3
Muting attenuation 4 Mute 4
Mute 1 = 20 log
L input
L1 output
: Output signal level of pin 14.
L input: Input signal level of pin 26.
L1 output 00 10000010
Pin 26: Input SIN wave (1 kHz, 0.5 V
rms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
R1 output
Mute 2 = 20 log
R input
R1 output
: Output signal level of pin 13.
R input: Input signal level of pin 27.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
rms).
L2 output 10000100
Mute 3 = 20 log
L input
L2 output
: Output signal level of pin 17.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 V
rms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
R2 output
Mute 4 = 20 log
R input
R2 output
: Output signal level of pin 16.
R input: Input signal level of pin 27.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
rms).
Data
D7 D6 D5 D4 D3 D2 D1 D0
µ
PC1853
Page 53
(1) µPC1853CT-01 Volume control, tone control block (9/9)
53
Parameter Symbol Test conditions Subaddress
Muting attenuation 5 Mute 5
Muting attenuation 6 Mute 6
(Rear) L input
DC offset at muting mode V
OS1
(L1 OUT, R1 OUT) V
DC offset at muting mode V
OS2
(L2 OUT, R2 OUT) V
DC offset at muting mode V
OS3
(L+R OUT) V
DC offset at muting mode V
OS4
(Rear OUT) V
Data
D7 D6 D5 D4 D3 D2 D1 D0
L+R output 00 10001000
Mute 5 = 20 log
L, R input
L+R output
: Output signal level of pin 12.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (1 kHz, 0.5 V
rms).
Rear output 10010000
Mute 6 = 20 log
Rear output
: Output signal level of pin 11.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 V
rms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
VOS1 = V1 - V0
1: DC voltage of pin 14 or 13 (Main output mute: ON). ↓
00 10000000
V0: DC voltage of pin 14 or 13 (Main output mute: OFF). 1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
VOS2 = V1 - V0
1: DC voltage of pin 17 or 16 (Audio output mute: ON). ↓
10000000
V0: DC voltage of pin 17 or 16 (Audio output mute: OFF). 1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
VOS3 = V1 - V0
1: DC voltage of pin 12 (L+R output mute: ON). ↓
10000000
V0: DC voltage of pin 12 (L+R output mute: OFF). 1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
VOS4 = V1 - V0
1: DC voltage of pin 11 (Rear output mute: ON). ↓
10000000
V0: DC voltage of pin 11 (Rear output mute: OFF). 1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
µ
PC1853
Page 54
54
(2) µPC1853CT-02 Volume control, tone control block (1/6)
Parameter Symbol Test conditions Subaddress
Volume attenuation 1 (1) L-ch ATT
Volume attenuation 1 (2) L-ch ATT
Volume attenuation 1 (3) L-ch ATT
Volume attenuation 1 (4) R-ch ATT
Volume attenuation 1 (5) R-ch ATT
Volume attenuation 1 (6) R-ch ATT
Volume attenuation 2 (1) ATT
Volume attenuation 2 (2) ATT
Volume attenuation 2 (3) ATT
L+R volume attenuation 1 ATT
L+R volume attenuation 2 ATT
L+R volume attenuation 3 ATT
Data
D7 D6 D5 D4 D3 D2 D1 D0
VL11
Volume attenuation = 20 log
L input
VL12
L1 output: Output signal level of pin 14. 01100000
L1 output 02 01111111
L input: Input signal level of pin 26.
VL13
Pin 26: Input SIN wave (1 kHz, 0.5 V
rms). 01000000
Pin 27: No signal (Connect to GND with an input coupling capacitor).
VR14
Volume attenuation = 20 log
R input
VR15
R1 output: Output signal level of pin 13. 01100000
R1 output 01 01111111
R input: Input signal level of pin 27.
VR16
VL21
VL22
Pin 26: No signal (Connect to GND with an input coupling capacitor). 01000000
Pin 27: Input SIN wave (1 kHz, 0.5 V
rms).
L2 output 06 01111111
Volume attenuation = 20 log
L input
L2 output: Output signal level of pin 17. 01100000
L input: Input signal level of pin 26.
VL23
Pin 26: Input SIN wave (1 kHz, 0.5 V
rms). 01000000
Pin 27: No signal (Connect to GND with an input coupling capacitor).
VLR1
L+R volume attenuation = 20 log
L, R input
VLR2
L+R output: Output signal level of pin 12. 01100000
L+R output 05 01111111
L, R input: Input signal level of pin 26 or 27.
VLR3
Pin 26, 27: Input SIN wave (1 kHz, 0.5 V
rms). 01000000
µ
PC1853
Page 55
(2) µPC1853CT-02 Volume control, tone control block (2/6)
55
Parameter Symbol Test conditions Subaddress
Rear volume attenuation 1 ATT
Rear volume attenuation 2 ATT
Low-band boost control V
Low-band flat control V
Low-band cut control V
High-band boost control V
High-band flat control V
High-band cut control V
BB
BF
BC
TB
TF
TC
L, R in-phase gain difference 1 (1) DG
11
Data
D7 D6 D5 D4 D3 D2 D1 D0
VRE1
Rear volume attenuation = 20 log
L input
Rear output 07 01111111
Rear output: Output signal level of pin 11.
VRE2
L input: Input signal level of pin 26. 01100000
Pin 26: Input SIN wave (1 kHz, 0.5 V
rms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
L1 output 03 01111111
Bass response = 20 log
L input
L1 output: Output signal level of pin 14. 01100000
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (100 Hz, 0.5 V
rms). 01000001
Pin 27: No signal (Connect to GND with an input coupling capacitor).
L1 output 04 01111111
Treble response = 20 log
L input
L1 output: Output signal level of pin 14. 01100000
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (10 kHz, 0.5 V
rms). 01000001
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Channel to channel error = 20 log
R input 02
R1 output
: Output signal level of pin 13.
– ATT
VL11
R1 output
01 01111111
R input: Input signal level of pin 27.
ATTVL11: Gain of the Volume attenuation 1 (1).
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
rms).
Same method about L-ch input/output signal
µ
PC1853
Page 56
56
(2) µPC1853CT-02 Volume control, tone control block (3/6)
Parameter Symbol Test conditions Subaddress
L, R in-phase gain difference 1 (2) DG
L, R in-phase gain difference 2 (1) DG21
L, R in-phase gain difference 2 (2) DG
L, R in-phase gain difference 3 (1) DG
Data
D7 D6 D5 D4 D3 D2 D1 D0
12
Channel to channel error = 20 log
R input 02
R1 output
: Output signal level of pin 13.
R1 output
– ATT
VL12
01 01100000
R input: Input signal level of pin 27.
VL12: Gain of the Volume attenuation 1 (2).
ATT
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
rms).
Same method about L-ch input/output signal
Channel to channel error = 20 log
R2 output
R input
R2 output
: Output signal level of pin 16.
– ATT
VL21
06 01111111
R input: Input signal level of pin 27.
VL21: Gain of the Volume attenuation 2 (1).
ATT
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
22
Channel to channel error = 20 log
R input
R2 output
: Output signal level of pin 16.
rms).
R2 output
– ATT
VL22
01100000
R input: Input signal level of pin 27.
VL22: Gain of the Volume attenuation 2 (2).
ATT
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
31
Channel to channel error = 20 log
R input
R1 output
: Output signal level of pin 13.
R input: Input signal level of pin 27.
BB: Gain of the Low-band boost control.
V
rms).
R1 output
– V
BB
03 01111111
µ
PC1853
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 V
rms).
Page 57
(2) µPC1853CT-02 Volume control, tone control block (4/6)
57
Parameter Symbol Test conditions Subaddress
L, R in-phase gain difference 3 (2) DG
L, R in-phase gain difference 3 (3) DG
L, R in-phase gain difference 4 (1) DG
L, R in-phase gain difference 4 (2) DG
Data
D7 D6 D5 D4 D3 D2 D1 D0
32
Channel to channel error = 20 log
R input
R1 output
: Output signal level of pin 13.
R1 output
– V
BF
03 01100000
R input: Input signal level of pin 27.
VBF: Gain of the Low-band flat control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 V
33
Channel to channel error = 20 log
R input
R1 output
: Output signal level of pin 13.
R1 output
rms).
– V
BC
01000001
R input: Input signal level of pin 27.
VBC: Gain of the Low-band cut control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (100 Hz, 0.5 V
41
Channel to channel error = 20 log
R input
R1 output
: Output signal level of pin 13.
R1 output
rms).
– V
TB
05 01111111
R input: Input signal level of pin 27.
VTB: Gain of the High-band boost control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (10 kHz, 0.5 V
42
Channel to channel error = 20 log
R input
R1 output
: Output signal level of pin 13.
rms).
R1 output
– V
TF
01100000
µ
PC1853
R input: Input signal level of pin 27.
VTF: Gain of the High-band flat control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (10 kHz, 0.5 V
rms).
Page 58
58
(2) µPC1853CT-02 Volume control, tone control block (5/6)
Parameter Symbol Test conditions Subaddress
L, R in-phase gain difference 4 (3) DG
43
Muting attenuation 1 Mute 1
Muting attenuation 2 Mute 2
Muting attenuation 3 Mute 3
Channel to channel error = 20 log
R input
R1 output
: Output signal level of pin 13.
– V
TC
R input: Input signal level of pin 27.
VTC: Gain of the High-band cut control.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
R1 output
Pin 27: Input SIN wave (10 kHz, 0.5 V
rms).
L2 output 00 10000100
Mute 1 = 20 log
L input
L2 output
: Output signal level of pin 17.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 V
rms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
R2 output
Mute 2 = 20 log
R input
R2 output
: Output signal level of pin 16.
R input: Input signal level of pin 27.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz, 0.5 V
rms).
L+R output 10001000
Mute 3 = 20 log
L, R input
L+R output
: Output signal level of pin 12.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (1 kHz, 0.5 V
rms).
Data
D7 D6 D5 D4 D3 D2 D1 D0
05 01000001
µ
PC1853
Page 59
(2) µPC1853CT-02 Volume control, tone control block (6/6)
Parameter Symbol Test conditions Subaddress
Muting attenuation 4 Mute 4
(Rear) L input
DC offset at muting mode V
OS1
(L1OUT, R1 OUT) V
DC offset at muting mode V
OS2
(L2 OUT, R2 OUT) V
DC offset at muting mode V
OS3
(L+R OUT) V
DC offset at muting mode V
OS4
(Rear OUT) V
Data
D7 D6 D5 D4 D3 D2 D1 D0
Rear output 00 10010000
Mute 4 = 20 log
Rear output
: Output signal level of pin 11.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz, 0.5 V
rms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
VOS1 = V1 - V0
1: DC voltage of pin 14 or 13 (Main output mute: ON). ↓
00 10000000
V0: DC voltage of pin 14 or 13 (Main output mute: OFF). 1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
VOS2 = V1 - V0
1: DC voltage of pin 17 or 16 (Audio output mute: ON). ↓
10000000
V0: DC voltage of pin 17 or 16 (Audio output mute: OFF). 1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
VOS3 = V1 - V0
1: DC voltage of pin 12 (L+R output mute: ON). ↓
10000000
V0: DC voltage of pin 12 (L+R output mute: OFF). 1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
VOS4 = V1 - V0
1: DC voltage of pin 11 (Rear output mute: ON). ↓
10000000
V0: DC voltage of pin 11 (Rear output mute: OFF). 1
Pins 26 and 27: Connect to GND with an input coupling capacitor.
µ
PC1853
59
Page 60
60
Matrix surround block (1/3)
Parameter Symbol Test conditions Subaddress
In-phase gain G
Movie mode 1 L input
MOV1
Response = 20 log
L1, R1 output 08 11001000
L1, R1 output: Output signal level of pin 14 or 13.
In-phase gain GMOV2 L input: Input signal level of pin 26.
Movie mode 2 Pin 26: Input SIN wave (1 kHz, 0.5 V
Pin 27: No signal (Connect to GND with an input coupling capacitor).
In-phase gain GMUS1
Music mode 1 L input
Response = 20 log
L1, R1 output 08 11101000
L1, R1 output: Output signal level of pin 14 or 13.
In-phase gain GMUS2 L input: Input signal level of pin 26.
Music mode 2 Pin 26: Input SIN wave (1 kHz, 0.5 V
Pin 27: No signal (Connect to GND with an input coupling capacitor).
In-phase gain GSIML1
Simulated mode L, R input
(L-ch) 1 L1 output
Response = 20 log
: Output signal level of pin 14.
L1 output 08 11011000
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (250 Hz, 0.5 V
In-phase gain G
Simulated mode L, R input
(L-ch) 2 L1 output
SIML2
Response = 20 log
: Output signal level of pin 14.
L1 output
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (1 kHz, 0.5 V
In-phase gain G
Simulated mode L, R input
(L-ch) 3 L1 output
SIML3
Response = 20 log
: Output signal level of pin 14.
L1 output
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (4 kHz, 0.5 V
Data
D7 D6 D5 D4 D3 D2 D1 D0
rms).
rms).
rms).
rms).
µ
PC1853
rms).
Remark The methods are common to both the
µ
PC1853CT-01 and
µ
PC1853CT-02.
Page 61
Matrix surround block (2/3)
Parameter Symbol Test conditions Subaddress
In-phase gain G
Simulated mode L, R input
SIMR1
Response = 20 log
R1 output 08 11011000
(R-ch) 1 R1 output: Output signal level of pin 13.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (250 Hz, 0.5 V
In-phase gain G
Simulated mode L, R input
SIMR2
Response = 20 log
R1 output
rms).
(R-ch) 2 R1 output: Output signal level of pin 13.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (1 kHz, 0.5 V
In-phase gain G
Simulated mode L, R input
SIMR3
Response = 20 log
R1 output
rms).
(R-ch) 3 R1 output : Output signal level of pin 13.
L, R input: Input signal level of pin 26 or 27.
Pins 26 and 27: Input SIN wave (4 kHz, 0.5 V
rms).
Output noise NO1 NO1: Output noise voltage of pins 11, 12, 13, 14, 16 and 17.
Pins 26 and 27: Connect to GND with an input coupling capacitor.
Filter of noise meter: DIN-AUDIO filter
Crosstalk 1 CT1
Crosstalk = 20 log
L input
R output
R output: Output signal level of pin 13 or 16.
L input: Input signal level of pin 26.
Pin 26: Input SIN wave (1 kHz. 0.5 V
rms).
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Data
D7 D6 D5 D4 D3 D2 D1 D0
µ
PC1853
61
Remark The methods are common to both the
µ
PC1853CT-01 and
µ
PC1853CT-02.
Page 62
62
Matrix surround block (3/3)
Parameter Symbol Test conditions Subaddress
Crosstalk 2 CT2
Inter-mode offset V
OSM No signal. 08 × 1 ××1111
Note See 4.3 Surround Function.
Remark The methods are common to both the
Crosstalk = 20 log
R input
: Output signal level of pin 14 or 17.
L output
R input: Input signal level of pin 27.
Pin 26: No signal (Connect to GND with an input coupling capacitor).
Pin 27: Input SIN wave (1 kHz. 0.5 V
At surround mode switching.
µ
PC1853CT-01 and
L output
µ
PC1853CT-02.
rms).
Note
Data
D7 D6 D5 D4 D3 D2 D1 D0
µ
PC1853
Page 63
6. CHARACTERISTIC CURVES
q
)
About surround mode, see 4.3 Surround Function.
6.1 Frequency Response Characteristics in Each Mode
(1) OFF mode (L-channel, R-channel)
8
6
4
2
VCC = 12 V
V
IN
= 1.4 V
p-p
(= 0 dB)
µ
PC1853
0
Gain G (dB)
–2
–4
–6
100 1 k 10 k
Fre
uency f (Hz
63
Page 64
(2) Movie Mode
µ
PC1853
10
5
0
–5
–10
–15
Gain G (dB)
–20
–25
–30
–35
100 1 k 10 k
Frequency f (Hz)
VCC = 12 V
Lin: V
IN
= 1.4 V
Rin: GND
L1 OUT
R1 OUT
p-p
(= 0 dB)
(3) Music Mode
12
8
4
0
–4
–8
Gain G (dB)
–12
–16
–18
–20
100 1 k 10 k
Frequency f (Hz)
VCC = 12 V
IN
= 1.4 V
Lin: V
Rin: GND
L1 OUT
R1 OUT
p-p
(= 0 dB)
64
Page 65
(4) Simulated Mode
µ
PC1853
12
8
4
0
–4
–8
Gain G (dB)
–12
–16
–20
100 1 k 10 k
Frequency f (Hz)
VCC = 12 V
Lin, Rin: V
L1 OUT
R1 OUT
IN
= 1.4 V
p-p
(= 0 dB)
65
Page 66
6.2 Characteristics of Phase Shifter and Rear Output
)
(1) Movie Mode
0
–10
Gain G (dB)
+100
φ
0
Phase (deg.)
µ
PC1853
VCC = 12 V
IN
= 1.4 V
Lin: V
Rin: GND
Rear OUT pin
Characteristics of
Phase Shifter
Characteristics of
Rear Output
p-p
(=0 dB)
–20
10 30 50 70 100 300 500 700 1 k 3 k 5 k 7 k 10 k 20 k
Frequency f (Hz
(2) Music Mode
0
–10
Gain G (dB)
–100
+100
φ
0
Phase (deg.)
VCC = 12 V
IN
= 1.4 V
Lin: V
Rin: GND
Rear OUT pin
Characteristics of
Phase Shifter
Characteristics of
Rear Output
p-p
(=0 dB)
–20
10 30 50 70 100 300 500700 1 k 3 k 5 k 7 k 10 k 20 k
Frequency f (Hz)
66
–100
Page 67
(3) Simulated Mode
10 30 50 70 100 300 500700 1 k 3 k 5 k 7 k 10 k 20 k
0
–10
–20
Gain G (dB)
Frequency f (Hz)
+100
0
–100
Phase (deg.)
φ
VCC = 12 V
Lin, Rin: V
IN
= 1.4 V
p-p
(=0 dB)
Rear OUT pin
Characteristics of
Phase Shifter
Characteristics of
Rear Output
µ
PC1853
67
Page 68
6.3 Control Characteristics
(
)
(
)
(1) Volume Control Characteristics
0
–20
–40
–60
Attenuation (dB)
–80
–100
OFF mode
f = 1 kHz
Lin or Rin: V
Lin or Rin: GND
IN
= 1.4 V
p-p
(=0 dB)
µ
PC1853
000000 001000 010000 011000 100000 101000 110000 111000 111111
Data of Subaddress: 01H
D5······D0
(2) Balance Control Characteristics
0
–20
–40
–60
Attenuation (dB)
–80
–100
Lch flat
Rch ATT
Lch ATT
Rch flat
OFF mode
f = 1 kHz
L1 OUT
IN = 1.4 Vp-p (=0 dB)
Lin: V
Rin: GND
R1 OUT
Lin: GND
IN = 1.4 Vp-p (=0 dB)
Rin: V
68
000000 001000 010000 011000 100000 101000 110000 111000 111111
Data of Subaddress: 02H
D5······D0
Page 69
(3) Tone Control Characteristics (Bass)
(
)
(
)
10
5
0
–5
Attenuation (dB)
–10
µ
OFF mode
Bass: f = 100 Hz
IN
= 1.4 V
Lin: V
Rin: GND
L1 OUT
PC1853
p-p
(=0 dB)
000000 001000 010000 011000 100000 101000 110000 111000 111111
Data of Subaddress: 03H
(4) Tone Control Characteristics (Treble)
10
5
0
–5
Attenuation (dB)
–10
D5······D0
OFF mode
Treble: f = 10 kHz
IN
= 1.4 V
Lin: V
Rin: GND
L1 OUT
p-p
(=0 dB)
000000 001000 010000 011000 100000 101000 110000 111000 111111
Data of Subaddress: 04H
D5······D0
69
Page 70
(5) Tone Frequency Characteristics
q
)
(
)
µ
PC1853
20
A
10
B
C
0
Gain G (dB)
D
–10
E
–20
10 100 1 k 10 k 100 k
uency f (Hz
Fre
OFF mode
Lin: V
IN
= 1.4 V
p-p
Rin: GND
F
G
H
J
L1 OUT
Curve Subaddress Data (D5 ·····D0)
A 111111
B 110000
C 03H 100000
D 010000
E 000001
F 111111
I
G 110000
H 04H 100000
I 010000
J 000001
(=0 dB)
(6) Low Boost Control Characteristics
10
5
0
Attenuation (dB)
–5
–10
000000 001000 010000 011000 100000 101000 110000 111000 111111
Data of Subaddress: 01H
D5·····D0
OFF mode
f = 100 Hz
Lin: V
IN = 1.4 Vp-p (= 0 dB)
Rin : GND
L1 OUT
Low Boost 1 (6 dB)
Low Boost 2 (3 dB)
70
Page 71
(7) Low Boost 1 (6 dB)
µ
PC1853
20
A
0
B
–20
Gain G (dB)
C
–40
–60
10 100 1 k 10 k 100 k
Frequency f (Hz)
VCC = 12 V
Lin: V
IN
= 1.4 V
p-p
Rin: GND
L1 OUT
(= 0 dB)
Curve Subaddress Data (D5 ·····D0)
A 111111
B 01H 100000
C 010000
(8) Low Boost 2 (3 dB)
20
A
0
B
–20
Gain G (dB)
C
–40
–60
10 100 1 k 10 k 100 k
Frequency f (Hz)
VCC = 12 V
Lin: V
IN
= 1.4 V
p-p
Rin: GND
L1 OUT
(= 0 dB)
Curve Subaddress Data (D5 ·····D0)
A 111111
B 01H 100000
C 010000
71
Page 72
(9) Effect Control Characteristics
(
)
µ
PC1853
10
0
–10
–20
Attenuation (dB)
–30
–40
0000 0100 1000 1100 1111
Data of Subaddress: 08H
D3······D0
f = 1 kHz
IN = 1.4 Vp-p (= 0 dB)
Lin: V
Rin: GND
Rear OUT pin
0 dB : Subaddress: 08 H, Data “1000”
Movie Mode
Music Mode
Simulated Mode
72
Page 73
6.4 Input/Output Characteristics, Distortion Rate
5.0
)
1.0
rms
5.0
1.0
µ
PC1853
f = 1 kHz
Lin or Rin: V
Lin or Rin: GND
µ
PC1853-01
Subaddress: 01H, Data “111111”
Subaddress: 02H, Data “100000”
µ
PC1853-02
Subaddress: 01H, 02H,
Data “111111”
Output Signal Voltage
Distortion Rate
IN
= 1.4 V
p-p
(= 0 dB)
0.5
0.1
Output Signal Voltage (V
0.05
0.01
0.05 0.1 0.5 1.0 5.0
Input Signal Voltage (V
rms
0.5
Distortion Rate (%)
0.1
0.05
)
73
Page 74
7. MEASURING CIRCUIT
µ
PC1853
0.082
DV
DD
L, R channel
signal input
a
Switch 2
820 kΩ
Note
Note
F
µ
MFI
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
123456789101112131415
AGND
Note
680 pF
MFO LF1 Rin Lin
FC1 FC2 FC3 FC4 LF2 RTC RBC LTC LBC
Note
Note Note Note Note Note Note Note Note
F
µ
0.1
2200 pF
b
µ
F
F
µ
a
Switch 1
µ
22
0.022
b
++
22
0.022
+
F
µ
DGND
+
Fµ22
F
µ
22
1/2 V
OFC
F
1000 pF 6800 pF 6800 pF
CC
PC1853CT
µ
(+5 V)
ab
Switch 3
DGND
0.1 F
ADS SDA SCL
F
µ
2
C bus
I
DGND SDA SCL
+ +
Rear OUT
µ
0.1
µ
F
0.01
R channel
signal 2 output
+
L channel
signal 2
output
µ
3.3
3.3
F
BAL-C
VOL-C
(RVC) L2 OUT
(LVC)
L+R OUT
R1 OUT L1 OUT
F
µ
R2 OUT
V
CC
AGND
Note Recommended external parts.
Carbon-film resistor : ±1 %
Film capacitor : ±1 %
Ceramic capacitor : ±1 %
Use external parts as follows unless otherwise
specified.
Carbon-film resistor : ±5 %
Film capacitor : ±20 %
Electrolytic capacitor: ±20 %
F
µ
47
Rear
L+R
R-
output
signal
output
channel
signal1
output
Lchannel
signal1
output
AV
CC
(+12 V)
Attention on Printed Wiring
1. AGND: Wide area grounding.
2. Connect terminating resistors as near pins 26 and 27
as possible.
2
3. Make the wiring of I
C bus block distant from the
wiring of analog block.
4. Connect by-pass capacitor near pin 15 (VCC pin).
74
Page 75
8. PACKAGE DIMENSIONS
30PIN PLASTIC SHRINK DIP (400 mil)
30 16
115
µ
PC1853
A
I
J
H
G
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
2) ltem "K" to center of leads when formed parallel.
F
DN
M
C
B
K
L
M
ITEM MILLIMETERS INCHES
A 28.46 MAX. 1.121 MAX.
B 1.78 MAX. 0.070 MAX.
C 1.778 (T.P.) 0.070 (T.P.)
D 0.50±0.10 0.020
F 0.85 MIN. 0.033 MIN.
G 3.2±0.3 0.126±0.012
H 0.51 MIN. 0.020 MIN.
I 4.31 MAX. 0.170 MAX.
J 5.08 MAX. 0.200 MAX.
K 10.16 (T.P.) 0.400 (T.P.)
L 8.6 0.339
M 0.25 0.010
N 0.17 0.007
R 0~15° 0~15°
+0.10
–0.05
R
+0.004
–0.005
+0.004
–0.003
S30C-70-400B-1
75
Page 76
µ
PC1853
[MEMO]
Caution: Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
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