Page 1
1GROUND
CLOCK CLK
SERIAL
DATA IN
STROBE
OUT
OUT
OUT
OUT
2
3
4
5
1
6
2
7
3
8
4
ST
SHIFT
REGISTER
LATCHES
Data Sheet
5890
AND
26182.12C
5891
BIMOS II 8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
Frequently applied in non-impact printer systems, the UCN5890A,
SERIAL
16
DATA OUT
V
OE
V
LOGIC
15
DD
SUPPLY
OUTPUT
14
ENABLE
LOAD
13
BB
SUPPLY
12
OUT
8
11
OUT
7
OUT
10
6
OUT
9
5
UCN5890LW, UCN5891A, and UCN5891LW are BiMOS II serial-input,
latched source (high-side) drivers. The octal, high-current smart-power ICs
merge an 8-bit CMOS shift register, associated CMOS latches, and CMOS
control logic (strobe and output enable) with sourcing power Darlington
outputs. Typical applications include multiplexed LED and incandescent
displays, relays, solenoids, and similar peripheral loads to a maximum of
-500 mA per output.
Except for output voltage ratings, these smart high-side driver ICs are
equivalent. The UCN5890A/LW are rated for operation with load supply
voltages of 20 V to 80 V and a minimum output sustaining voltage of 50 V.
The UCN5891A/LW are optimized for operation with supply voltages of 5 V
to 50 V (35 V sustaining).
Dwg. PP-026-2A
Note the suffix ‘A’ devices (DIP) and the suffix
‘LW’ devices (SOIC) are electrically identical and
share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Output Voltage, V
(UCN5890A & UCN5890LW) .........80 V
(UCN5891A & UCN5891LW) .........50 V
Logic Supply Voltage Range,
VDD....................................4.5 V to 15 V
Driver Supply Voltage Range, V
(UCN5890A/LW)................ 20 V to 80 V
(UCN5891A/LW)............... 5.0 V to 50 V
Input Voltage Range,
V
........................ -0.3 V to VDD + 0.3 V
IN
Continuous Output Current,
I
........................................... -500 mA
OUT
Allowable Package Power Dissipation,
P
......................................... See Graph
D
Operating Temperature Range,
T
.................................. -20°C to +85°C
A
Storage Temperature Range,
T
................................ -55°C to +150°C
S
Caution: CMOS devices have input static
protection, but are susceptible to damage when
exposed to extremely high static electrical
charges.
OUT
BB
BiMOS II devices have higher data-input rates than the original BiMOS
circuits. With a 5 V supply, they will operate to at least 3.3 MHz. At 12 V,
higher speeds are possible. The CMOS inputs are compatible with standard
CMOS and NMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors to ensure a proper input-logic high. A CMOS serial data
output, allows cascading these devices in multiple drive-line applications
required by many dot matrix, alphanumeric, and bar graph displays.
Suffix ‘A’ devices are supplied in a standard dual in-line plastic package
with copper lead frame for enhanced package power dissipation characteristics. Suffix ‘LW’ devices are supplied in a standard wide-body SOIC package
for surface-mount applications. Similar driver, featuring reduced output
saturation voltage, are the UCN5895A and A5895SLW. Complementary,
8-bit serial-input, latched sink drivers are the Series UCN5820A.
FEATURES
■ 50 V or 80 V Source Outputs
■ Output Current to -500 mA
■ Output Transient-Suppression Diodes
■ To 3.3 MHz Data-lnput Rate
■ Low-Power CMOS Logic and Latches
Always order by complete part number, e.g., UCN5891LW .
Page 2
5890
AND
5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
2.5
2.0
1.5
1.0
0.5
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
SUFFIX 'A', R = 60°C/W
SUFFIX 'LW', R = 80°C/W
0
25
50 75 100 125 150
AMBIENT TEMPERATURE IN °C
θJA
θJA
Dwg. GP-018B
TYPICAL INPUT CIRCUIT
V
DD
IN
FUNCTIONAL BLOCK DIAGRAM
CLOCK
SERIAL
DATA IN
STROBE
GROUND
MOS
BIPOLAR
Number of UCN5890/91A Max. Allowable Duty Cycle
Outputs On at at T
= -200 mA 50°C60°C70°C
I
OUT
8 53% 47% 41%
7 60% 54% 48%
6 70% 64% 56%
5 83% 75% 67%
4 100% 94% 84%
3 100% 100% 100%
2 100% 100% 100%
1 100% 100% 100%
8-BIT SERIAL-PARALLEL SHIFT REGISTER
LATCHES
OUT1OUT2OUT3OUT4OUT5OUT6OUT7OUT
of
A
8
Dwg. No. A-12,654
SERIAL
DATA OUT
V
DD
OUTPUT
ENABLE
V
BB
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
V
BB
OUT
Dwg. No. A-12,648
Number of UCN5890/91LW Max. Allowable Duty Cycle
Outputs On at at T
= -200 mA 50°C60°C70°C
I
OUT
of
A
8 40% 35% 31%
7 45% 41% 36%
6 53% 48% 42%
5 62% 56% 50%
4 80% 71% 62%
3 100% 96% 84%
2 100% 100% 100%
1 100% 100% 100%
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2000 Allegro MicroSystems, Inc.
Page 3
5890
AND
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 80 V (UCN5890A/LW) or 50 V
(UCN5891A/LW), VDD = 5 V and 12 V (unless otherwise noted).
Limits
Characteristic Symbol V
Output Leakage Current I
Output Saturation Voltage V
Output Sustaining Voltage V
Input Voltage V
Input Current I
Input lmpedance Z
Max. Clock Frequency f
Serial Data Output R
Resistance
Turn-On Delay t
Turn-Off Delay t
Supply Current I
Diode Leakage Current I
Diode Forward Voltage V
CE(SAT)
CE(sus)
V
CEX
IN(1)
IN(0)
IN(1)
IN
c
OUT
PLH
PHL
BB
l
DD
R
F
Max. TA = +25°C — -50 µA
50 V I
Max. I
50 V VDD = 5.0 V 3.5 5.3 V
50 V VDD = 5 V to 12 V -0.3 +0.8 V
50 V VDD = VIN = 5.0 V — 50 µA
50 V VDD = 5.0 V 100 — kΩ
50 V 3.3* — MHz
50 V VDD = 5.0 V — 20 kΩ
50 V Output Enable to Output, I
50 V Output Enable to Output, I
50 V All outputs on, All outputs open — 10 mA
50 V VDD = 5 V, All outputs off, Inputs = 0 V — 100 µA
Max. TA = +25°C — 50 µA
Open IF = 350 mA — 2.0 V
BB
Test Conditions Min. Max. Units
TA = +70°C — -100 µA
= -100 mA — 1.8 V
OUT
I
= -225 mA — 1.9 V
OUT
I
= -350 mA — 2.0 V
OUT
= -350 mA, L = 2 mH, UCN5891A/LW 35 — V
OUT
I
= -350 mA, L = 2 mH, UCN5890A/LW 50 — V
OUT
VDD = 12 V 10.5 12.3 V
VDD = VIN = 12 V — 240 µA
VDD = 12 V 50 — kΩ
= 12 V — 6.0 kΩ
V
DD
= -350 mA — 2.0 µs
OUT
= -350 mA — 10 µs
OUT
All outputs off — 200 µA
VDD = 12 V, All outputs off, Inputs = 0 V — 200 µA
VDD = 5 V, One output on, All Inputs = 0 V — 1.0 mA
VDD = 12 V, One output on, All Inputs = 0 V — 3.0 mA
TA = +70°C — 100 µA
5891
NOTES: Turn-off delay is influenced by load conditions. Systems applications well below the specified output loading may require
timing considerations for some designs, i.e., multiplexed displays or when used in combination with sink drivers in a totem
pole configuration.
Positive (negative) current is defined as going into (coming out of) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
Page 4
5890
AND
5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
CLOCK
A D
B
DATA IN
E F
C
STROBE
BLANKING
G
OUT
N
Dwg. No. A-12,649A
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion ......................................................................... 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is transferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the OUTPUT ENABLE input be high
during serial data entry.
When the OUTPUT ENABLE input is high,
all of the output buffers are disabled (off) without
affecting the information stored in the latches or
shift register. With the OUTPUT ENABLE input
low, the outputs are controlled by the state of
their respective latches.
TRUTH TABLE
Serial Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Strobe Output
Input Input I
HHR
LLR
XR
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
1I2I3
1R2R3
XXX...X X X L R1R2R3... R
P1P2P3... P
1R2
1R2
... I
... R
... R
... R
N-1IN
N-2RN-1
N-2RN-1
N-1RN
N-1PN
Output Input I1I2I3... I
R
N-1
R
N-1
R
N
P
N
X X X ... X X H L L L ... L L
HP1P2P3... P
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
N-1IN
N-1 RN
N-1 PN
Enable I1I2I3... I
LP1P2P3... P
N-1
N-1
I
P
N
N
Page 5
LATCHED SOURCE DRIVERS
TYPICAL APPLICATION
SOLENOID OR RELAY DRIVER
+5V +48V
UCN5890A
5890
AND
5891
8-BIT SERIAL-INPUT,
CLOCK
DATA IN
STROBE
1
2
3
4
5
6
7
8
SHIFT
REGISTER
LATCHES
16
15
V
DD
14
OE
13
V
BB
12
11
10
9
DATA OUT
OUTPUT ENABLE
(ACTIVE LOW)
Dwg. No. A-12,548
www.allegromicro.com
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
Page 6
5890
AND
5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
UCN5890A and UCN5891A
(controlling dimensions)
16
0.280
0.240
Dimensions in Inches
9
0.014
0.008
0.430
MAX
0.300
BSC
0.210
MAX
7.11
6.10
0.015
MIN
1
0.070
0.045
16
1
1.77
1.15
0.022
0.014
0.100
0.775
0.735
BSC
Dimensions in Millimeters
(for reference only)
2.54
19.68
18.67
BSC
8
0.005
MIN
0.150
0.115
Dwg. MA-001-16A in
0.355
9
8
0.13
MIN
0.204
10.92
MAX
7.62
BSC
5.33
MAX
0.39
MIN
0.558
0.356
3.81
2.93
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 25 devices.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Dwg. MA-001-16A mm
Page 7
UCN5890LW and UCN5891LW
Dimensions in Inches
(for reference only)
16 9
5890
AND
5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
0.0125
0.0091
0.2992
0.2914
0.020
0.013
0.0926
0.1043
7.60
7.40
1 2
0.0040
MIN.
3
0.4133
0.3977
Dimensions in Millimeters
(controlling dimensions)
916
0.050
BSC
0.419
0.394
0.050
0.016
0° TO 8°
Dwg. MA-008-16A in
0.32
0.23
10.65
10.00
0.51
0.33
2.65
2.35
1 2
0.10
3
10.50
10.10
MIN.
1.27
BSC
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 47 devices or add “TR” to part number for tape and reel.
www.allegromicro.com
1.27
0.40
0° TO 8°
Dwg. MA-008-16A mm
Page 8
5890
AND
5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
POWER
INTERFACE DRIVERS
Function Output Ratings* Part Number
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers) -120 mA 50 V‡ 5895
8-Bit 350 mA 50 V 5821
8-Bit 350 mA 80 V 5822
8-Bit 350 mA 50 V‡ 5841
8-Bit 350 mA 80 V‡ 5842
8-Bit (constant-current LED driver) 75 mA 17 V 6275
8-Bit (DMOS drivers) 250 mA 50 V 6595
8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595
8-Bit (DMOS drivers) 100 mA 50 V 6B595
10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10
12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811
16-Bit (constant-current LED driver) 75 mA 17 V 6276
20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812
32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818
32-Bit 100 mA 30 V 5833
32-Bit (saturated drivers) 100 mA 40 V 5832
PARALLEL-INPUT LATCHED DRIVERS
4-Bit 350 mA 50 V‡ 5800
†
8-Bit -25 mA 60 V 5815
8-Bit 350 mA 50 V‡ 5801
8-Bit (DMOS drivers) 100 mA 50 V 6B273
8-Bit (DMOS drivers) 250 mA 50 V 6273
SPECIAL-PURPOSE DEVICES
Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804
Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259
Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259
Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259
Addressable 28-Line Decoder/Driver 450 mA 30 V 6817
* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
† Complete part number includes additional characters to indicate operating temperature range and package style.
‡ Internal transient-suppression diodes included for inductive-load protection.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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