Datasheet UCN5833EP, UCN5833A Datasheet (Allegro)

UCN5833EP

32

SERIAL DATA OUT

OUTPUT ENABLENCOUT

41

42

OE

LATCHES

19

20

OUT18OUT

OUT

Dwg. No. A-13,049

40

39

38

37

36

35

34

33

32

31

30

29

28

NC

43

REGISTER

252627

17

. . . . . . . 7.0 V

+ 0.3 V

DD

D

OUT

31

30

29

28

27

26

25

24

23

22

21

OUT

OUTNCSTROBE1POWER GROUND

6

2

7

3

8

4

9

5

10

6

11

7

12

13

8

14

9

15

10

11

16

17

12

18

NC

5

SERIAL DATA IN

2

3

4

ST

LATCHES

REGISTER

1920212223

15

13

14

16

OUT

LOGIC

SUPPLY

CLOCK

1

44

DD

V

CLK

SUB

24

OUT

LOGIC GROUND

ABSOLUTE MAXIMUM RATINGS

at +25°C Free-Air Temperature

Output Voltage, V Logic Supply Voltage, V Input Voltage Range,

. . . . . . . . . -0.3 V to V

V

IN

Continuous Output Current,

(each output) . . . . . . . . . . 125 mA

l

OUT

Package Power Dissipation, P

(UCN5833A) . . . . . . . . . . . . . . . 3.5 W*

(UCN5833EP) . . . . . . . . . . . . . . 2.5 W*

Operating Temperature Range,

. . . . . . . . . . . . . . - 20°C to +85°C

T

A

Storage Temperature Range,

. . . . . . . . . . . . . -55°C to +150°C

T

S

* Derate linearly to 0 W at +150°C.

Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges.

. . . . . . . . . . . 30 V

OUT

DD

5833

BiMOS II 32-BIT SERIAL-INPUT,

LATCHED DRIVER

Designed to reduce logic supply current, chip size, and system cost, the UCN5833A/EP integrated circuits offer high-speed operation for thermal printers. These devices can also be used to drive multiplexed LED displays or incandescent lamps within their 125 mA peak output current rating. The combination of bipolar and MOS technologies gives BiMOS II smart power ICs an interface flexibility beyond the reach of standard buffers and power driver circuits.

These 32-bit drivers have bipolar open-collector npn Darlington outputs, a CMOS data latch for each of the drivers, a 32-bit CMOS shift register, and CMOS control circuitry. The high-speed CMOS shift registers and latches allow operation with most microprocessor-based systems at data input rates above 3.3 MHz. Use of these drivers with TTL may require input pull-up resistors to ensure an input logic high.

The UCN5833A is supplied in a 40-pin dual in-line plastic package with 0.600" (15.24 mm) row spacing. At an ambient temperature of +75°C, all outputs of the DlP-packaged device will sustain 50 mA continuously. For high-density applications, the UCN5833EP is available. This 44-lead plastic chip carrier (quad pack) is intended for surface-mounting on solder lands with 0.050" (1.27 mm) centers. CMOS serial data outputs permit cascading for applications requiring additional drive lines.

FEATURES

■ To 3.3 MHz Data Input Rate

■ 30 V Minimum Output Breakdown

■ Darlington Current-Sink Outputs

■ Low-Power CMOS Logic and Latches

Always order by complete part number:

Part Number Package

UCN5833A 40-Pin DIP

UCN5833EP 44-Lead PLCC

26185.16A*

Data Sheet

5833

BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER

UCN5833A

LOGIC SUPPLY

SERIAL DATA I N

POWER GROUND

STROBE

OUT

1

V

DD

2

3

4

ST

5

1

6

2

7

3

8

4

9

5

10

6

11

7

12

8

12

9

14

10

15

11

16

12

17

13

18

14

19

15

20

16

LATCHES

REGISTER

CLK

OE

LATCHES

SUB

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

LOGIC

CLOCK

SUPPLY

SERIAL DATA O U T

OUTPUT ENABLE

OUT

32

OUT

31

OUT

30

OUT

29

OUT

28

OUT

27

OUT

26

OUT

25

OUT

24

OUT

23

OUT

22

OUT

21

OUT

20

OUT

19

OUT

18

OUT

17

LOGIC GROUND

CLOCK

SERIAL DATA I N

STROBE

OUTPUT ENABLE

FUNCTIONAL BLOCK DIAGRAM

32-BIT SHIFT REGISTER

LATCHES

OUT

1

3

2

POWER GROUND

OUT

OUT OUT

30

32

31

TYPICAL INPUT CIRCUIT

V

DD

IN

V

DD

SERIAL DATA

OUT

LOGIC GROUND

SUB

MOS

BIPOLAR

Dwg. No. A-13,057

Dwg. No. A-13,048

SUB

TYPICAL OUTPUT DRIVER

115 Northeast Cutoff, Box 15036 115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 Worcester, Massachusetts 01615-0036 (508) 853-5000

Dwg. No. A-13,050

OUT

Dwg. No. A-13,051

5833

BiMOS II 32-BIT

SERIAL-INPUT,

LATCHED DRIVER

ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).

Limits

Characteristic Symbol Test Conditions Min. Max. Units

Output Leakage Current I

Collector-Emitter V Saturation Voltage

Input Voltage V

Input Current l

Serial Output Voltage V

V

Supply Current l

CEX

CE(SAT)

IN(1)

V

IN(0)

IN(1)

l

IN(0)

OUT(1)

OUT(0)

DD

V

= 30 V, TA = 70°C—10µA

OUT

l

= 50 mA — 1.2 V

OUT

l

= 100 mA — 1.7 V

OUT

3.5 5.3 V

-0.3 +0.8 V

VIN = 5.0 V — 1.0 µA

VIN = 0 V — -1.0 µA

I

= -200 µA 4.5 — V

OUT

I

= 200 µA — 0.3 V

OUT

One output ON, l

= 100 mA — 1.0 mA

OUT

All outputs OFF — 50 µA

Output Rise Time t

Output Fall Time t

NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin.

r

f

l

= 100 mA, 10% to 90% — 500 ns

OUT

l

= 100 mA, 90% to 10% — 500 ns

OUT

TRUTH TABLE

Serial Shift Register Contents Serial Latch Contents Output Output Contents Data Clock Data Strobe Enable Input Input I

1I2I3

HHR

LLR

XR

1R2R3

XXX...X X X L R1R2R3... R

P1P2P3... P

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

1R2

... I

... R

N-1IN

N-2RN-1

N-1RN

N-1PN

Output Input I1I2I3... I

R

N-1

R

N-1

R

N

P

N

HP1P2P3... P

X X X ... X X L H H H ... H H

N-1IN

N-1 RN

N-1 PN

Input I1I2I3... I

HP1P2P3... P

N-1

I

P

N

5833

BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER

CLOCK

A D

B

DATA IN

E F

STROBE

C

OUTPUT ENABLE

G

OUT

N

Dwg. No. A-12,276A

TIMING CONDITIONS

(VDD = 5.0 V, Logic Levels are VDD and Ground)

A. Minimum Data Active Time Before Clock Pulse

(Data Set-Up Time) .......................................................................... 75 ns

B. Minimum Data Active Time After Clock Pulse

(Data Hold Time) ............................................................................. 75 ns

C. Minimum Data Pulse Width ................................................................ 150 ns

D. Minimum Clock Pulse Width ............................................................... 150 ns

E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns

F. Minimum Strobe Pulse Width ............................................................. 100 ns

G. Typical Time Between Strobe Activation and

Output Transition ........................................................................... 500 ns

Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.

Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be low during serial data entry.

When the OUTPUT ENABLE input is low, all of the output buffers are disabled (OFF) without affecting the information stored in the latches or shift register. With the OUTPUT ENABLE input high, the outputs are controlled by the state of the latches.

115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

0.580

0.485

5833

BiMOS II 32-BIT

SERIAL-INPUT,

LATCHED DRIVER

UCN5833A

Dimensions in Inches

(controlling dimensions)

0.015

40

21

0.008

0.600

BSC

0.700

MAX

0.250

MAX

14.73

12.32

6.35

MAX

0.015

MIN

1 2

0.022

0.014

40

1 2

1.77

0.77

0.070

0.030

3

4

2.095

1.980

0.100

BSC

20

0.005

MIN

0.200

0.115

Dwg. MA-003-40 in

Dimensions in Millimeters

(for reference only)

0.381

21

3

4

53.2

50.3

2.54

BSC

20

0.13

MIN

0.204

15.24

BSC

17.78

MAX

0.39

MIN

0.558

0.356

5.08

2.93

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Lead thickness is measured at seating plane or below.

Dwg. MA-003-40 mm

5833

BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER

UCN5833EP

Dimensions in Inches

(controlling dimensions)

28

18

0.319

0.291

0.319

0.291

8.10

7.39

8.10

7.39

0.021

0.013

0.050

BSC

0.533

0.331

1.27

BSC

0.020

MIN

0.180

0.165

29

0.032

0.026

0.695

0.685

0.656

0.650

39

40

Dimensions in Millimeters

(for reference only)

28

29

0.812

0.661

17.65

17.40

16.662

16.510

0.656

0.650

144

0.695

0.685

INDEX AREA

2

INDEX AREA

17

7

6

Dwg. MA-005-44A in

18

17

39

144

16.662

16.510

17.65

17.40

0.51

MIN

4.57

4.20

40

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

7

2

6

Dwg. MA-005-44A mm

5833

BiMOS II 32-BIT

SERIAL-INPUT,

LATCHED DRIVER

The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.

Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.

5833

BiMOS II 32-BIT SERIAL-INPUT, LATCHED DRIVER

POWER

INTERFACE DRIVERS

Function Output Ratings* Part Number

SERIAL-INPUT LATCHED DRIVERS

8-Bit (saturated drivers) -120 mA 50 V‡ 5895 8-Bit 350 mA 50 V 5821 8-Bit 350 mA 80 V 5822 8-Bit 350 mA 50 V‡ 5841 8-Bit 350 mA 80 V‡ 5842 8-Bit (constant-current LED driver) 75 mA 17 V 6275 8-Bit (DMOS drivers) 250 mA 50 V 6595 8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595 8-Bit (DMOS drivers) 100 mA 50 V 6B595

10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10

12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811

16-Bit (constant-current LED driver) 75 mA 17 V 6276

20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812

32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818 32-Bit 100 mA 30 V 5833 32-Bit (saturated drivers) 100 mA 40 V 5832

PARALLEL-INPUT LATCHED DRIVERS

4-Bit 350 mA 50 V‡ 5800

†

8-Bit -25 mA 60 V 5815 8-Bit 350 mA 50 V‡ 5801 8-Bit (DMOS drivers) 100 mA 50 V 6B273 8-Bit (DMOS drivers) 250 mA 50 V 6273

SPECIAL-PURPOSE DEVICES

Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804 Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259 Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259 Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259 Addressable 28-Line Decoder/Driver 450 mA 30 V 6817

* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.

Negative current is defined as coming out of (sourcing) the output.

† Complete part number includes additional characters to indicate operating temperature range and package style.

‡ Internal transient-suppression diodes included for inductive-load protection.

115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000