Datasheet UC3844BNG Datasheet

Page 1
UC3844B, UC3845B, UC2844B, UC2845B
High Performance Current Mode Controllers
Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cyclebycycle current limiting, a latch for single pulse metering, and a flip−flop which blanks the output off every other oscillator cycle, allowing output deadtimes to be programmed from 50% to 70%.
These devices are available in an 8pin dual−in−line and surface mount (SOIC8) plastic package as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14 package has separate power and ground pins for the totem pole output stage.
The UCX844B has UVLO thresholds of 16V (on) and 10V (off), ideally suited for off−line converters. The UCX845B is tailored for lower voltage applications having UVLO thresholds of 8.5V (on) and 7.6V (off).
Features
Trimmed Oscillator for Precise Frequency Control
Oscillator Frequency Guaranteed at 250 kHz
Current Mode Operation to 500 kHz Output Switching Frequency
Output Deadtime Adjustable from 50% to 70%
Automatic Feed Forward Compensation
Latching PWM for CycleByCycle Current Limiting
Internally Trimmed Reference with Undervoltage Lockout
High Current Totem Pole Output
Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
These Devices are PbFree and are RoHS Compliant
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100 Qualified and PPAP Capable
V
ref
RT/C
Voltage
Feedback
Input
Output/
Compensation
8(14)
T
4(7)
2(3)
1(1)
R
Undervoltage
R
Lockout
Oscillator
Error
Amplifier
Pin numbers in parenthesis are for the D suffix SOIC-14 package.
GND
Figure 1. Simplified Block Diagram
5.0V
Reference
V
ref
Latching
PWM
5(9)
V
7(12)
CC
V
CC
Undervoltage
Lockout
V
C
7(11)
Output
6(10)
Power Ground
5(8)
Current Sense Input
3(5)
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PDIP8
N SUFFIX
8
CASE 626
1
SOIC14
14
1
D SUFFIX
CASE 751A
SOIC8
8
1
D1 SUFFIX
CASE 751
PIN CONNECTIONS
(Top View)
(Top View)
8
V
ref
7
V
CC
6
Output
5
GN D
14
V
ref
13
NC
12
V
CC
11
V
C
10
Output
9
GND
8
Power Ground
Compensation
Voltage Feedback
Current Sense
RT/C
Compensation
NC
Voltage Feedback
NC
Current Sense
NC
R
T/CT
1
2
3
4
T
1
2
3
4
5
6
7
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
August, 2013 Rev. 11
1 Publication Order Number:
UC3844B/D
Page 2
UC3844B, UC3845B, UC2844B, UC2845B
MAXIMUM RATINGS
Rating Symbol Value Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) (Note 1) VCC, V
C
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink (Note 2) I
O
Output Energy (Capacitive Load per Cycle) W 5.0
Current Sense and Voltage Feedback Inputs V
Error Amp Output Sink Current I
in
O
Power Dissipation and Thermal Characteristics D Suffix, Plastic Package, SOIC−14 Case 751A
Maximum Power Dissipation @ T
= 25°C
A
Thermal Resistance, JunctiontoAir
P
D
R
q
JA
D1 Suffix, Plastic Package, SOIC8 Case 751
Maximum Power Dissipation @ T Thermal Resistance, JunctiontoAir
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ T Thermal Resistance, JunctiontoAir
Operating Junction Temperature T
Operating Ambient Temperature UC3844B, UC3845B
= 25°C
A
= 25°C
A
P
D
R
q
JA
P
D
R
q
JA
J
T
A
UC2844B, UC2845B
UC3844BV, UC3845BV
Storage Temperature Range T
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
1. The voltage is clamped by a zener diode (see page 9 Under Voltage Lockout section). Therefore this voltage may be exceeded as long as
the total power supply and zener current is not exceeded.
2. Maximum package power dissipation limits must be observed.
3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC Standard
JESD22-A114B, Machine Model Method 200 V per JEDEC Standard JESD22-A115-A
4. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78
ELECTRICAL CHARACTERISTICS (V
is the operating ambient temperature range that applies [Note 6], unless otherwise noted.)
T
A
= 15 V [Note 5], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
CC
UC284xB UC384xB, xBV, NCV384xBV
Characteristic Symbol Min Ty p Max Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (I
= 1.0 mA, TJ = 25°C) V
O
Line Regulation (VCC = 12 V to 25 V) Reg
Load Regulation (IO = 1.0 mA to 20 mA) Reg
Temperature Stability T
Total Output Variation over Line, Load, & Temperature V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) V
ref
S
ref
n
4.95 5.0 5.05 4.9 5.0 5.1 V
line
load
2.0 20 2.0 20 mV
3.0 25 3.0 25 mV
0.2 0.2 mV/°C
4.9 5.1 4.82 5.18 V
50 50
Long Term Stability (TA = 125°C for 1000 Hours) S 5.0 5.0 mV
Output Short Circuit Current I
SC
30 85 180 30 85 180 mA
OSCILLATOR SECTION
A
= T
low
= 25°C
J
to T
high
Frequency T
T
TJ = 25°C (RT = 6.2 k, CT = 1.0 nF)
Frequency Change with Voltage (VCC = 12 V to 25 V)
Frequency Change w/ Temperature (TA = T
low
to T
high
Oscillator Voltage Swing (PeaktoPeak) V
f
OSC
Df
OSC
)
Df
OSC
OSC
/DV
/DT
49 48
225
52
250
55 56
275
49 48
225
0.2 1.0 0.2 1.0 %
1.0 0.5 %
1.6 1.6 V
5. Adjust VCC above the Startup threshold before setting to 15 V.
6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
=0°C for UC3844B, UC3845B T
T
low
= 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B
=+70°C for UC3844B, UC3845B
high
= 40°C for UC384xBV, NCV384xBV =+105°C for UC3844BV, UC3845BV
= +125°C for NCV384xBV
36 V
1.0 A
0.3 to + 5.5 V
10 mA
862 145
°C/W
702 178
°C/W
1.25 100
°C/W
+150 °C
0 to +70
25 to +85
40 to +105
65 to +150 °C
52
250
55 56
275
mJ
mW
mW
W
°C
mV
kHz
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UC3844B, UC3845B, UC2844B, UC2845B
ELECTRICAL CHARACTERISTICS (V
is the operating ambient temperature range that applies [Note 8], unless otherwise noted.)
T
A
= 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
CC
UC284xB UC384xB, xBV,
NCV384xBV
Characteristic Symbol Min Typ Max Min Typ Max Unit
OSCILLATOR SECTION
Discharge Current (V
= 2.0 V) TJ = 25°C
OSC
= T
T
to T
A
low
(UC284XB, UC384XB)
high
(UC384XBV)
I
dischg
7.8
7.5
8.3
8.8
7.8
8.3
8.8
7.6
7.2
8.8
8.8
8.8
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V) V
Input Bias Current (VFB = 5.0 V) I
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) A
FB
IB
VOL
2.45 2.5 2.55 2.42 2.5 2.58 V
0.1 1.0 0.1 2.0
65 90 65 90 dB
Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 0.7 1.0 MHz
Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 60 70 dB
Output Current Sink (VO = 1.1 V, VFB = 2.7 V)
Output Current Source (V
= 5.0 V, VFB = 2.3 V)
O
I
Sink
I
Source
2.0
0.512−1.0−−
2.0
0.512−1.0−−
Output Voltage Swing
High State (R Low State (R
= 15 k to ground, VFB = 2.3 V)
L
= 15 k to V
L
(UC284XB, UC384XB) (UC384XBV)
, VFB = 2.7 V)
ref
V
OH
V
OL
5.0
6.2
0.8
5.0
6.2
1.1
0.8
0.8
1.1
1.2
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 9 & 10)
(UC284XB, UC384XB) (UC384XBV)
Maximum Current Sense Input Threshold (Note 9)
(UC284XB, UC384XB) (UC384XBV)
A
V
2.85−3.0−3.15−2.85
2.85
V
th
0.9−1.0−1.1−0.9
0.85
3.0
3.0
1.0
1.0
3.15
3.25
1.1
1.1
Power Supply Rejection Ratio (VCC = 12 V to 25 V) (Note 9) PSRR 70 70 dB
Input Bias Current I
Propagation Delay (Current Sense Input to Output) t
PLH(In/Out)
IB
2.0 10 2.0 10
150 300 150 300 ns
OUTPUT SECTION
Output Voltage
Low State (I
High State (I
Output Voltage with UVLO Activated (VCC = 6.0 V, I
= 20 mA)
Sink
= 200 mA, UC284XB, UC384XB)
(I
Sink
= 200 mA, UC384XBV)
(I
Sink
= 20 mA, UC284XB, UC384XB)
Source
= 20 mA, UC384XBV)
(I
Source
= 200 mA)
(I
Source
= 1.0 mA) V
Sink
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) t
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) t
V
OL
V
OH
OL(UVLO)
r
f
13
12
0.1
1.6
13.5
13.4
0.4
2.2
13
12.9 12
0.1
1.6
1.6
13.5
13.4
0.4
2.2
2.3
0.1 1.1 0.1 1.1 V
50 150 50 150 ns
50 150 50 150 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold UCX844B, BV
UCX845B, BV
Minimum Operating Voltage After TurnOn UCX844B, BV
UCX845B, BV
V
V
CC(min)
th
15
7.8168.4179.0
9.0
7.0107.6118.2
14.5
7.8168.4
8.5
7.0107.6
17.5
9.0
11.5
8.2
7. Adjust VCC above the Startup threshold before setting to 15 V.
8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. =0°C for UC3844B, UC3845B T
T
low
= 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B
=+70°C for UC3844B, UC3845B
high
= 40°C for UC384xBV, NCV384xBV = +105°C for UC3844BV, UC3845BV
= +125°C for NCV384xBV
9. This parameter is measured at the latch trip point with V
DV Output/Compensation
10.Comparator gain is defined as: A
=
V
DV Current Sense Input
FB
= 0 V.
mA
mA
mA
V
V/V
V
mA
V
V
V
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UC3844B, UC3845B, UC2844B, UC2845B
ELECTRICAL CHARACTERISTICS (V
values T
is the operating ambient temperature range that applies [Note 12], unless otherwise noted.)
A
= 15 V [Note 11], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max
CC
UC284xB UC384xB, xBV, NCV384xBV
Characteristic Symbol Min Typ Max Min Typ Max Unit
PWM SECTION
Duty Cycle
Maximum (UC284XB, UC384XB)
Maximum (UC384XBV)
Minimum
DC
DC
(max)
(min)
47
48
50
0
47 46
48 48
TOTAL DEVICE
Power Supply Current
Startup (V
Startup (V
= 6.5 V for UCX845B,
CC
= 14 V for UCX844B, BV)
CC
Operating (Note 11)
Power Supply Zener Voltage (ICC = 25 mA) V
I
CC
Z
0.3120.5
17
0.3
12
30 36 30 36 V
11.Adjust VCC above the Startup threshold before setting to 15 V.
12.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. =0°C for UC3844B, UC3845B T
T
low
= 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B
=+70°C for UC3844B, UC3845B
high
= 40°C for UC384xBV, NCV384xBV = +105°C for UC3844BV, UC3845BV
=+125°C for NCV384xBV
80
50
Ω
20
8.0
5.0
, TIMING RESISTOR (k )
T
R
2.0 NOTE: Output switches at 1/2 the oscillator frequency
0.8
, OSCILLATOR FREQUENCY (kHz)
f
OSC
For RTu 5KfX
1.72
R
TCT
Figure 2. Timing Resistor
versus Oscillator Frequency
VCC = 15 V T
= 25°C
A
1.0 M500 k200 k100 k50 k20 k10 k
75
1.CT = 10 nF
2.C
70
3.C
4.C
5.C
65
6.C
7.CT = 100 pF
60
55
% DT, PERCENT OUTPUT DEADTIME
50
= 5.0 nF
T
= 2.0 nF
T
= 1.0 nF
T
= 500 pF
T
= 200 pF
T
20 k 50 k 200 k 500 k
, OSCILLATOR FREQUENCY (kHz)
f
OSC
Figure 3. Output Deadtime
versus Oscillator Frequency
50
%
50
0
mA
0.5
17
3
2
4
1
7
5
6
1.0 M100 k10 k
2.55 V
2.5 V
2.45 V
VCC = 15 V A
= -1.0
V
TA = 25°C
0.5 ms/DIV
Figure 4. Error Amp Small Signal
Transient Response
3.0 V
2.5 V
20 mV/DIV
2.0 V
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VCC = 15 V A T
A
1.0 ms/DIV
Figure 5. Error Amp Large Signal
Transient Response
= -1.0
V
= 25°C
200 mV/DIV
Page 5
100
)
80
60
40
20
, OPEN LOOP VOLTAGE GAIN (dB)
0
VOL
A
-20
Figure 6. Error Amp Open Loop Gain and
UC3844B, UC3845B, UC2844B, UC2845B
VCC = 15 V V
= 2.0 V to 4.0 V
O
R
= 100 k
Gain
100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz)
Phase versus Frequency
L
T
A
= 25°C
Phase
0
1.2 VCC = 15 V
30
60
1.0
0.8
TA = 25°C
90
120
0.6
0.4
TA = 125°C
TA = -55°C
, EXCESS PHASE (DEGREES)
150
180
10 M10
0.2
φ
, CURRENT SENSE INPUT THRESHOLD (V
th
0
V
0
2.0 4.0 6.0 8.0 , ERROR AMP OUTPUT VOLTAGE (VO)
V
O
Figure 7. Current Sense Input Threshold
versus Error Amp Output Voltage
0
-4.0
-8.0
-12
-16
-20
, REFERENCE VOLTAGE CHANGE (mV)
ref
V
Δ
-24 0
Figure 8. Reference Voltage Change
VCC = 15 V
TA = -55°C
TA = 125°C
TA = 25°C
20 40 60 80 100 120
I
, REFERENCE SOURCE CURRENT (mA)
ref
versus Source Current
VCC = 15 V I
= 1.0 mA to 20 mA
O
T
= 25°C
A
110
, REFERENCE SHORT CIRCUIT CURRENT (mA)
SC
I
90
70
50
-55
-25 0 25 50 75 100 125 , AMBIENT TEMPERATURE (°C)
T
A
Figure 9. Reference Short Circuit Current
versus Temperature
VCC = 15 V
0.1 W
R
L
VCC = 12 V to 25 V T
= 25°C
A
O
V Δ , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
Figure 10. Reference Load Regulation Figure 11. Reference Line Regulation
2.0 ms/DIV
O
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V Δ , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
2.0 ms/DIV
Page 6
O
S
O
O
G
(
V
)
E
LTA
N V
ATURATI
UTPUT ,
sat
V
-1.0
-2.0
3.0
2.0
1.0
UC3844B, UC3845B, UC2844B, UC2845B
0
V
CC
TA = 25°C
TA = -55°C
0
200 400 600
Source Saturation
(Load to Ground)
TA = -55°C
Sink Saturation
(Load to V
, OUTPUT LOAD CURRENT (mA)
I
O
)
CC
VCC = 15 V 80 ms Pulsed Load 120 Hz Rate
TA = 25°C
GND
VCC = 15 V C
= 1.0 nF
90
%
L
T
= 25°C
A
10
%
8000
50 ns/DIV
Figure 12. Output Saturation Voltage
Figure 13. Output Waveform
versus Load Current
25
20
15
10
, SUPPLY CURRENT (mA)
CC
I
RT = 10 k CT = 3.3 nF V
5
0
0
UCX845B
UCX844B
10 20 30 40
V
, SUPPLY VOLTAGE (V)
CC
I
Sense
T
A
FB
= 0 V
= 0 V
= 25°C
, OUTPUT VOLTAGEV
O
, SUPPLY CURRENT
CC
I
100 ns/DIV
VCC = 30 V C
= 15 pF
L
T
= 25°C
A
100 mA/DIV 20 V/DIV
Figure 14. Output Cross Conduction Figure 15. Supply Current versus Supply Voltage
PIN FUNCTION DESCRIPTION
Pin
8Pin 14Pin
1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation.
2 3 Voltage
3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this
4 7 RT/C
5 GND This pin is the combined control circuitry and power ground.
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
7 12 V
8 14 V
8 Power
11 V
9 GND This pin is the control circuitry ground return and is connected back to the powersource ground.
2,4,6,13 NC No connection. These pins are not internally connected.
Function Description
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
Feedback
supply output through a resistor divider.
information to terminate the output switch conduction.
T
The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to V
and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible.
ref
and sunk by this pin. The output switches at onehalf the oscillator frequency.
CC
ref
This pin is the positive supply of the control IC.
This is the reference output. It provides charging current for capacitor CT through resistor RT.
This pin is a separate power ground return that is connected back to the power source. It is used
Ground
C
to reduce the effects of switching transient noise on the control circuitry.
The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry.
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UC3844B, UC3845B, UC2844B, UC2845B
OPERATING DESCRIPTION
The UC3844B, UC3845B series are high performance, fixed frequency, current mode controllers. They are specifically designed for OffLine and DCDC converter applications offering the designer a costeffective solution with minimal external components. A representative block diagram is shown in Figure 16.
Oscillator
The oscillator frequency is programmed by the values selected for the timing components R
and CT. Capacitor C
T
is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of C
, the oscillator
T
generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. An internal flipflop has been incorporated in the UCX844/5B which blanks the output off every other clock cycle by holding one of the inputs of the NOR gate high. This in combination with the C
discharge period yields output
T
deadtimes programmable from 50% to 70%. Figure 2 shows R
versus Oscillator Frequency and Figure 3, Output
T
Deadtime versus Frequency, both for given values of C Note that many values of R
and CT will give the same
T
oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated to within ±6% at 50 kHz. Also, because of industry trends moving the UC384X into higher and higher frequency applications, the UC384XB is guaranteed to within ±10% at 250 kHz.
In many noisesensitive applications it may be desirable to frequencylock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 18. For reliable locking, the freerunning oscillator frequency should be set about 10% less than the clock frequency. A method for multi−unit synchronization is shown in Figure 19. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved to realize output deadtimes of greater than 70%.
Error Amplifier
A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 6). The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is −2.0 mA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 29). The output voltage is offset by two diode drops (1.4 V) and divided by three before it connects to the inverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (V
OL
). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft−start interval (Figures 21, 22). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (V
) to reach the
OH
comparator’s 1.0 V clamp level:
R
T
Current Sense Comparator and PWM Latch
f(min)
3.0 (1.0 V) + 1.4 V
0.5 mA
= 8800 W
The UC3844B, UC3845B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cyclebycycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The
T
groundreferenced sense resistor R
in series with the
S
inductor current is converted to a voltage by inserting the
.
source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 1 where:
V
1.4 V
Ipk =
(Pin 1)
3 R
S
Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is:
I
pk(max)
1.0 V
=
R
S
When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of R
to a reasonable level. A
S
simple method to adjust this voltage is shown in Figure 20. The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the I
pk(max)
clamp voltage.
A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability (refer to Figure 24).
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7
Page 8
UC3844B, UC3845B, UC2844B, UC2845B
V
ref
8(14)
R
T
2.5V
R
Internal
Bias
R
3.6V
Oscillator
4(7)
C
T
Voltage
+
1.0mA
2R
Feedback
Input
Output/
Compensation
2(3)
1(1)
Error
Amplifier
GND
R
1.0V
5(9)
Pin numbers adjacent to terminals are for the 8-pin dual-in-line package. Pin numbers in parenthesis are for the D suffix SOIC-14 package.
Reference
Regulator
+
V
ref
­UVLO
Current Sense
Comparator
T
S
R
V
CC
UVLO
Q
PWM Latch
V
CC
V
CC
7(12)
V
in
36V
(See
+
Text)
-
V
C
7(11)
Output
Q1
6(10)
Power Ground
5(8)
Current Sense Input
3(5)
R
S
= Sink Only Positive True Logic
Capacitor C
Latch “Set" Input
Output/ Compensation
Current Sense Input
Latch “Reset" Input
Output
Figure 16. Representative Block Diagram
T
Large R
/Small C
T
T
Figure 17. Timing Diagram
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8
Small RT/Large C
T
Page 9
UC3844B, UC3845B, UC2844B, UC2845B
Undervoltage Lockout
Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (V
) and the reference output (V
CC
ref
) are each monitored by separate comparators. Each has built−in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The V
comparator
CC
upper and lower thresholds are 16 V/10 V for the UCX844B, and 8.4 V/7.6 V for the UCX845B. The V
comparator
ref
upper and lower thresholds are 3.6 V/3.4 V. The large hysteresis and low startup current of the UCX844B makes it ideally suited in offline converter applications where efficient bootstrap startup techniques are required (Figure 30). The UCX845B is intended for lower voltage dcdc converter applications. A 36 V Zener is connected as a shunt regulator from V
to ground. Its purpose is to
CC
protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for the UCX844B is 11 V and 8.2 V for the UCX845B.
Output
These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to ±1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pulldown resistor.
The SOIC−14 surface mount package provides separate pins for V
(output supply) and Power Ground. Proper
C
implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the I
pk(max)
clamp level. The separate VC supply input allows the
designer added flexibility in tailoring the drive voltage independent of VCC. A Zener clamp is typically connected to this input when driving power MOSFETs in systems where V
is greater than 20 V. Figure 23 shows proper
CC
power and control ground connections in a currentsensing power MOSFET application.
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at T
= 25°C on the UC284XB, and ±2.0% on the
J
UC384XB. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has shortcircuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on
wirewrap or plugin prototype boards. High frequency
circuit layout techniques are imperative to prevent pulsewidth jitter. This is usually caused by excessive noise pickup imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with lowcurrent signal and highcurrent switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 mF) connected directly to V and V
may be required depending upon circuit layout.
ref
CC
, VC,
This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise−generating components.
V
ref
8(14)
R
T
4(7)
C
T
0.01
External
Sync Input
The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of C
2(3)
47
1(1)
to go more than 300 mV below ground.
T
R
Bias
R
Osc
+
2R
EA
R
5(9)
R
A
8 4
R
B
6
5
2
C
f +
(RA )2RB)C
5.0k
5.0k
5.0k
1
1.44
R
S
MC1455
3
Q
D
(max)
7
+
8(14)
4(7)
2(3)
1(1)
To Additional UCX84XBs
R
A
RA )2R
B
Figure 18. External Clock Synchronization Figure 19. External Duty Cycle Clamp and
MultiUnit Synchronization
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9
R
Bias
R
Osc
+
2R
EA
R
5(9)
Page 10
UC3844B, UC3845B, UC2844B, UC2845B
R
R
V
2
1
Clamp
8(14)
4(7)
2(3)
1(1)
V
CC
7(12)
R
Bias
R
Osc
+
1.0 mA
) 1
+ 0.33x10
Ǔ
2R
EA
1.67
R
2
ǒ
R
1
5.0V Ref
+
-
[
7(11)
6(10)
5(8)
3(5)
Clamp
V
Clamp
+
-
Comp/Latch
R1R
R1) R
T
S
R
2
Ǔ
2
Q
Where: 0 ≤ V
I
pk(max)
V
Clamp
R
1.0V
5(9)
-3
ǒ
1.0 V
R
S
V
in
8(14)
Q1
R
S
4(7)
2(3)
1.0M
1(1)
C
t
Soft-Start
R
Bias
R
Osc
+
1.0mA
EA
3600C in mF
Figure 20. Adjustable Reduction of Clamp Level Figure 21. SoftStart Circuit
5.0V Ref
+
-
T
S
Q
2R
R
1.0V
5(9)
R
+
-
V
Clamp
R
1.0V
5(9)
Where: 0 ≤ V
V
C
ƫ
C
5.0V Ref
Clamp
R1R
R1) R
T
S
Q
R
Comp/Latch
1.0 V
2
2
t
R
R
Soft
2
1
V
8(14)
4(7)
2(3)
1(1)
Clamp
Start
MPSA63
+*In
R
Bias
R
Osc
+
1.0 mA
EA
2R
1.67
R
2
ǒ
Ǔ
) 1
R
1
ƪ
1 *
3V
Clamp
Figure 22. Adjustable Buffered Reduction of
Clamp Level with SoftStart
+
-
I
pk(max)
7(12)
V
CC
[
7(11)
6(10)
5(8)
3(5)
V
Clamp
G
R
1/4 W
V
in
V
Pin5
If: SENSEFET = MTP10N10M
Then : V
D
SENSEFET
S
K
M
Power Ground:
To Input Source
S
Return
[
Pin5
RSIpkr
r
DM(on)
R
S
DS(on)
 )R
= 200
[0.075I
S
pk
V
V
in
5.0V Ref
+
-
Q1
T
S
Q
R
Comp/Latch
R
S
Control Circuitry Ground:
To Pin (9)
CC
(12)
+
-
(11)
(10)
(8)
(5)
Virtually lossless current sensing can be achieved with the implementation of a SENSEFETt power switch. For proper operation during over-current conditions, a reduction of the I Refer to Figures 20 and 22.
R
S
clamp level must be implemented.
pk(max)
Figure 23. Current Sensing Power MOSFET
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10
Page 11
UC3844B, UC3845B, UC2844B, UC2845B
V
CC
7(12)
5.0V Ref
+
-
+
-
T
S
Q
R
Comp/Latch
7(11)
6(10)
5(8)
3(5)
V
in
The addition of the RC filter will eliminate
Q1
R
C
R
instability caused by the leading edge spike on the current waveform.
S
Figure 24. Current Waveform Spike Suppression
V
CC
7(12)
5.0V Ref
+
-
+
-
T
S
Q
R
Comp/Latch
7(11)
R
6(10)
5(8)
3(5)
V
in
g
Q1
R
S
I
B
+
0
-
Base Charge
Removal
6(10)
5(8)
3(5)
V
in
C1
Q1
R
S
Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit.
The totem pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C
.
1
Figure 25. MOSFET Parasitic Oscillations Figure 26. Bipolar Transistor Drive
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11
Page 12
UC3844B, UC3845B, UC2844B, UC2845B
V
CC
7(12)
5.0V Ref
+
-
+
-
T
S
Q
R
Comp/Latch
7(11)
6(10)
5(8)
3(5)
C
Isolation
Boundary
R
R
S
V
in
VGS Waveforms
+
Q1
0
­50% DC 25% DC
Ipk =
N
S
N
P
V
(Pin1)
+
0
-
3 R
- 1.4
S
N
S
ǒ
Ǔ
N
p
Figure 27. Isolated MOSFET Drive
8(14)
R
Bias
R
From V
R
i
R
d
O
C
f
Rf 8.8k
4(7)
2(3)
1(1)
MCR
101
2N
3905
2N
3903
The MCR101 SCR must be selected for a holding of < 0.5 mA @ T simple two transistor circuit can be used in place of the SCR as shown. All
Osc
+
1.0 mA 2R
EA
R
5(9)
. The
A(min)
resistors are 10 k.
Figure 28. Latched Shutdown
R
1(1)
2(3)
2.5V +
1.0mA 2R
f
EA
R
5(9)
2.5V
2(3)
R
f
1(1)
+
1.0mA 2R
EA
R
5(9)
From V
R
C
p
O
p
R
i
C
f
R
d
Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current.
Figure 29. Error Amplifier Compensation
http://onsemi.com
Error Amp compensation circuit for stabilizing current mode boost and flyback topologies operating with continuous inductor current.
12
Page 13
UC3844B, UC3845B, UC2844B, UC2845B
18k
4.7k
115 Vac
100
0.01
pF
8(14)
33k
4(7)
1.0nF
2(3)
150k
1(1)
Primary: 45 Turns #26 AWG
T1 -
4.7W
EA
MDA
202
R
Bias
R
Osc
+
-
+
5(9)
Secondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar Wound Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar Wound Core: Ferroxcube EC35-3C8 Bobbin: Ferroxcube EC35PCB1 Gap: 0.10" for a primary inductance of 1.0 mH
+
5.0V Ref
250
T
S
Q
R
Comp/Latch
MBR1635
+
3300
pF
T1
2200
MUR110
1000
47
1000
MUR110
680pF
2.7k
MTP
4N50
0.5
4.7k
56k
1N4935 1N4935
7(11)
6(10)
5(8)
3(5)
68
+
100
1N4937
22
1N5819
1.0k
470pF
L1
- 15 mH at 5.0 A, Coilcraft Z7156
L2, L3
- 25 mH at 5.0 A, Coilcraft Z7157
7(12)
+
-
L1
++
1000
L2
++
++
L3
1N4937
5.0V/4.0A
5.0V RTN
12V/0.3A
10
±12V RTN
10
-12V/0.3A
Figure 30. 7 W Off−Line Flyback Regulator
Test Conditions Results
Line Regulation: 5.0 V
±12 V
Load Regulation: 5.0 V
±12 V
Output Ripple: 5.0 V
±12 V
Efficiency Vin = 115 Vac 70%
All outputs are at nominal load currents unless otherwise noted.
Vin = 95 Vac to 130 Vac
D = 50 mV or ±0.5% D = 24 mV or ±0.1%
Vin = 115 Vac, I
= 115 Vac, I
V
in
= 1.0 A to 4.0 A
out
= 100 mA to 300 mA
out
D = 300 mV or ±3.0% D = 60 mV or ±0.25%
Vin = 115 Vac 40 mV
80 mV
pp
pp
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13
Page 14
UC3844B, UC3845B, UC2844B, UC2845B
= 15V
V
in
V
CC
PWM Latch
7(12)
34V
+
-
7(11)
6(10)
5(8)
3(5)
VO = 2.5
+
15 10
Connect to Pin 2 for closed loop operation.
ǒ
1.0nF
10k
8(14)
4(7)
2(3)
1(1)
2.5V
R
R
Error
Amplifier
+
Osc
Internal
Bias
0.5mA
UC3845B
Reference
Regulator
UVLO
+
V
-
1.0V
Current Sense
Comparator
5(9)
UVLO
ref
T
S
Q
R
3.6V
2R
R
The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. The converter's output can provide excellent line and load regulation by connecting the R2/R1 resistor divider as shown.
Figure 31. Step−Up Charge Pump Converter
47
1N5819
R2
) 1
R1
Output Load Regulation
(Open Loop Configuration)
IO (mA) VO (V)
0 2
9 18 36
1N5819
+
+
R2
R1
Ǔ
29.9
28.8
28.3
27.4
24.4
VO 2 (Vin)
47
V
UVLO
CC
PWM Latch
7(12)
+
-
1.0nF
10k
8(14)
4(7)
2(3)
1(1)
2.5V
R
R
Error
Amplifier
+
Internal
Osc
0.5mA
Bias
2R
3.6V
R
UC3845B
+
-
1.0V
Current Sense
5(9)
Reference
Regulator
V
ref
UVLO
Comparator
T
S
Q
R
The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors.
Figure 32. Voltage−Inverting Charge Pump Converter
34V
V
in
7(11)
6(10)
5(8)
3(5)
= 15V
+
15 10
Output Load Regulation
(mA) VO (V)
I
47
O
0 2
9 18 32
1N5819
1N5819
14.4
13.2
12.5
11.7
10.6
V
-V
O
in
+
47
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14
Page 15
UC3844B, UC3845B, UC2844B, UC2845B
ORDERING INFORMATION
Device Operating Temperature Range Package Shipping
UC384xBDG
SOIC14
55 Units/Rail
(PbFree)
UC384xBDR2G SOIC14
2500 Tape & Reel
(PbFree)
UC384xBD1G SOIC8
T
= 0° to +70°C
A
(PbFree)
UC384xBD1R2G SOIC8
98 Units/Rail
2500 Tape & Reel
(PbFree)
UC384xBNG PDIP8
50 Units/Rail
(PbFree)
UC284xBDG
SOIC14
55 Units/Rail
(PbFree)
UC284xBDR2G SOIC14
2500 Tape & Reel
(PbFree)
UC284xBD1G SOIC8
T
= 25° to +85°C
A
(PbFree)
UC284xBD1R2G SOIC8
98 Units/Rail
2500 Tape & Reel
(PbFree)
UC284xBNG PDIP8
50 Units/Rail
(PbFree)
UC384xBVDG
SOIC14
55 Units/Rail
(PbFree)
UC384xBVDR2G SOIC14
2500 Tape & Reel
(PbFree)
UC384xBVD1G SOIC8
T
= 40° to +105°C
A
(PbFree)
UC384xBVD1R2G SOIC8
98 Units/Rail
2500 Tape & Reel
(PbFree)
UC384xBVNG PDIP8
50 Units/Rail
(PbFree)
NCV3845BVD1R2G*
T
= 40° to +125°C
A
SOIC8
(PbFree)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D. x indicates either a 4 or 5 to define specific device part numbers. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ100 Qualified and PPAP
Capable.
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Page 16
UC3844B, UC3845B, UC2844B, UC2845B
MARKING DIAGRAMS
PDIP8
N SUFFIX
CASE 626
14
1
8
UC384xBN
AWL
YYWWG
1
UC384xBDG
AWLYWW
8
UC384xBVN
1
D SUFFIX
CASE 751A
14
UC384xBVDG
1
D1 SUFFIX
CASE 751
AWL
YYWWG
SOIC14
AWLYWW
SOIC8
8
UC284xBN
AWL
YYWWG
1
14
UC284xBDG
AWLYWW
1
8
384xB ALYW
G
1
x = 4 or 5 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = PbFree Package
8
1
384xB
ALYWV
G
8
284xB
ALYW
G
1
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16
Page 17
UC3844B, UC3845B, UC2844B, UC2845B
PACKAGE DIMENSIONS
PDIP8
N SUFFIX
CASE 62605
ISSUE N
NOTE 8
A1
D1
D
A
58
E1
14
b2
B
TOP VIEW
e/2
A2
A
L
e
8X
b
SIDE VIEW
0.010 CA
NOTE 3
SEATING PLANE
C
M
H
E
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
M
eB
END VIEW
MBM
NOTE 6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK­AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED.
c
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS).
INCHES
DIM MIN MAX
A −−−− 0.210 A1 0.015 −−−− A2 0.115 0.195 2.92 4.95
b 0.014 0.022 b2
0.060 TYP 1.52 TYP
C 0.008 0.014
D 0.355 0.400 D1 0.005 −−−−
E 0.300 0.325 E1 0.240 0.280 6.10 7.11
e 0.100 BSC
eB −−−− 0.430 −−− 10.92
L 0.115 0.150 2.92 3.81
M −−−− 10
MILLIMETERS
MIN MAX
−−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
9.02 10.16
0.13 −−−
7.62 8.26
2.54 BSC
−−− 10
°°
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Page 18
Y
Z
UC3844B, UC3845B, UC2844B, UC2845B
PACKAGE DIMENSIONS
SOIC8 NB
CASE 75107
ISSUE AK
X
B
H
A
58
1
4
G
D
0.25 (0.010) Z
M
S
0.25 (0.010)
M
M
Y
K
Y
C
SXS
SEATING PLANE
0.10 (0.004)
N
X 45
_
M
J
SOLDERING FOOTPRINT*
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW STANDARD IS 75107.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050
M 0 8 0 8
____
N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244
INCHES
1.52
0.060
7.0
0.275
0.6
0.024
4.0
0.155
1.270
0.050
SCALE 6:1
ǒ
inches
mm
Ǔ
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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18
Page 19
T
SEATING PLANE
UC3844B, UC3845B, UC2844B, UC2845B
PACKAGE DIMENSIONS
SOIC14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
A
14
1
8
B
7
P
7 PL
0.25 (0.010) B
M
M
G
F
J
D 14 PL
0.25 (0.010) A
M
X 45
R
C
K
S
B
T
S
_
M
SOLDERING FOOTPRINT
7X
7.04
1
14X
0.58
14X
1.52
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
__ __
P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019
INCHESMILLIMETERS
1.27 PITCH
DIMENSIONS: MILLIMETERS
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UC3844B/D
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