Datasheet UBA1707TS-C2, UBA1707TS-C1, UBA1707T-C2, UBA1707T-C1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1998 Jun 11
File under Integrated Circuits, IC03

1999 Feb 17

INTEGRATED CIRCUITS

UBA1707

Cordless telephone, answering
machine line interface

1999 Feb 17 2

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

FEATURES
Line interface

• Low DC line voltage; operates down to 1.2 V (excluding
polarity guard)

• Voltage regulator with adjustable DC voltage

• DC mask for voltage or current regulation (CTR 21)

• Line current limitation for protection

• Electronic hook switch control input

• Transmit amplifier with:

– Symmetrical inputs
– Fixed gain
– Large signals handling capability.

• Receive amplifier with fixed gain

• Transmit and receive amplifiers AGC for line loss

compensation.

Auxiliary amplifier

• Fixed gain.

Loudspeaker channel

• Dual inputs

• Rail-to-rail output stage for single-ended load drive

• High output current capability

• Dynamic limiter to prevent distortion

• Digital volume control

• Fixed maximum gain.

General purpose switches

• Three switches with open-collector.

3-wires serial bus interface

Allows to control:

• DC mask (voltage or current regulation)

• Receive amplifier mute function

• AGC:

– On/off
– Slope
–I

start

line current.

• Auxiliary amplifier mute function

• Loudspeaker channel:

– Input selection
– Volume setting
– Dynamic limiter inhibition
– Power-down mode.

• General purpose switches state

• Global power-down mode.

Supply

Operates with external supply voltage from 3.0 to 5.5 V.

APPLICATIONS

• Cordless base stations

• Answering machines

• Mains or battery-powered telephone sets.

GENERAL DESCRIPTION

The UBA1707 is a BiCMOS integrated circuit intended for
use in mains-powered telecom terminals. It performs all
speech and line interface functions, DC mask for voltage
or current regulation and electronic hook switch control.
The device includes an auxiliary amplifier, a loudspeaker
channel and general purpose switches.

Most of the characteristics are programmable via a 3-wire
serial bus interface.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

UBA1707T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1
UBA1707TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

1999 Feb 17 3

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

QUICK REFERENCE DATA

I

line

= 15 mA; VCC= 3.3 V; R

SLPE

=10Ω; AGC pin connected to GND; Z

line

= 600 Ω; Z

SET

= 619 Ω; EHI = HIGH;

f = 1 kHz; T

amb

=25°C; bit AGC at logic 1, all other configuration bits at logic 0; measured in test circuit of Fig.17;

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

operating voltage range 3.0 − 5.5 V

I

CC

current consumption from pin V

CC

normal operation; bit PD = 0 − 2.2 3.2 mA
power-down mode; bit PD = 1 − 110 150 µA

I

line

line current operating range normal operation 11 − 140 mA

with reduced performance 3 − 11 mA

V

LN

DC line voltage 2.7 3.0 3.3 V

R

REGC

DC mask slope in current regulation
mode

I

line

> 35 mA (typical);

R

LVI

=1MΩ; R

RGL

= 7.15 kΩ;

bit CRC = 1

− 1.4 − kΩ

G

v(trx)

voltage gain

transmit amplifier from TXI to LN V

TXI

= 50 mV (RMS) 10.6 11.6 12.6 dB

receive amplifier from RXI to RXO V

RXI

= 2 mV (RMS) 36.9 37.9 38.9 dB

∆G

v(trx)

gain control range for transmit and
receive amplifiers with respect to
I

line

=15mA

I

line

=90mA − 6.5 − dB

G

v(AX)

voltage gain from AXI to AXO V

AXI

= 2 mV (RMS) 30.8 31.8 32.8 dB

G

v(LSA)

voltage gain from LSAI1 or LSAI2 to
LSAO for maximum volume

V

LSAI

= 8 mV (RMS);

bits LSA1 = 1 and LSA2 = 1

26.5 28 29.5 dB

∆G

v(LSA)

voltage gain adjustment range for
loudspeaker channel

bits (VOL0, VOL1, VOL2)
from (0, 0, 0) to (1, 1, 1)

− 21 − dB

∆G

v(LSA)s

voltage gain adjustment step for
loudspeaker channel

VOL0 from 0 to 1 − 3 − dB

1999 Feb 17 4

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

BLOCK DIAGRAM

Fig.1 Block diagram.

Bit names are given in italics.

handbook, full pagewidth

MGK705

SERIAL

INTERFACE

EN CLK DATA

13 14 12

19

SUPPLY

PD

GENERAL SWITCHES

SWI1
SWI2
SWI3

21
20

19

2

REG

LSAI1

LSAI2

2V

d

2V

d

LSPD

LSPD

LSPD

SWC1, SWC2,
SWC3

VOL0
TO
VOL2

LSA2

LSA1

0.5V

CC

2V

d

DYNAMIC LIMITER

VOLUME CONTROL

V

CC

DLCI

C

DLC

DLC

LSAO

28

24

27

LSPGND 23

26

LOUDSPEAKER CHANNEL

AXI

2V

d

AXO

16

LVI

4

15

RGL

5

AGC

9

TXI−

17

TXI+

18

RXI

10

AUXILIARY AMPLIFIER

LINE INTERFACE

UBA1707

AXM

CRC

RAGC1

SAGC,
AGC

RAGC2

RXM

EHI

EHI

EHI

SLPE

600 mV

300 mV

AGC

LOW VOLTAGE

PART

CURRENT

LIMITATION

200 nA

V

CC

CST

7

LCC

6

EHI

11

REG

3

SLPE

1

LN

2

RXO

8

GND

22

C

CST

R

LVI

V

CC

TP

DARL

D

TN

SW

TN

ON-HOOK

LN −

LN +

V

CC

25

2V

d

R

SLPE

Z

SET

C

REG

3

3

R

RGL

VI

VI

VI

VI

1999 Feb 17 5

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

PINNING

SYMBOL PIN DESCRIPTION

SLPE 1 connection for slope resistor
LN 2 positive line terminal
REG 3 line voltage regulator decoupling
LVI 4 negative line voltage sense input
RGL 5 reference for current regulation mode
LCC 6 line current control output
CST 7 input for stability capacitor
RXO 8 receive amplifier output
AGC 9 automatic gain control/line loss

compensation adjustment
RXI 10 receiver amplifier input
EHI 11 electronic hook switch control input
DATA 12 serial bus data input
EN 13 programming serial bus enable input
CLK 14 serial bus clock input
AXI 15 auxiliary amplifier input
AXO 16 auxiliary amplifier output
TXI− 17 inverted transmit amplifier input
TXI+ 18 non-inverted transmit amplifier input
SWI3 19 NPN open-collector output 3
SWI2 20 NPN open-collector output 2
SWI1 21 NPN open-collector output 1
GND 22 ground reference
LSPGND 23 ground reference for the loudspeaker

amplifier
LSAO 24 loudspeaker amplifier output
V

CC

25 supply voltage
LSAI1 26 loudspeaker amplifier input 1
LSAI2 27 loudspeaker amplifier input 2
DLC 28 dynamic limiter timing adjustment

Fig.2 Pin configuration.

handbook, halfpage

SLPE

LN

REG

LVI
RGL
LCC
CST

RXO
AGC

RXI
EHI

DATA

EN

CLK

DLC
LSAI2
LSAI1
V

CC

LSPGND
GND

LSAO

SWI1
SWI2
SWI3
TXI+
TXI−
AXO
AXI

1
2
3
4
5
6
7
8

9
10
11
12
13

28
27
26
25
24
23
22
21

20
19
18
17
16
1514

UBA1707

MGK704

1999 Feb 17 6

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

FUNCTIONAL DESCRIPTION

All data given in this chapter are typical values, except
when otherwise specified.

Supply (pins V

CC

and GND; bits PD and LSPD)

The UBA1707 must be supplied with an external stabilized
voltage source between pins V

CC

and GND.
Pins GND and LSPGND must be connected together.
Without any signal, with the loudspeaker channel enabled

at minimum volume and without any general purpose
switch selected, the internal current consumption is

2.2 mA at VCC= 3.3 V. Each selected switch
(pins SWI1, SWI2, or SWI3) increases the current
consumption by 600 µA.

The supply current can be reduced when the loudspeaker
channel is not used by switching it off (bit LSPD at logic 1).
The current consumption is then decreased by
approximately 800 µA at minimum volume.

To drastically reduce current consumption, the UBA1707
is provided with a power-down mode controlled by bit PD.
When bit PD is at logic 1, the current consumption from
VCC becomes 110 µA. In this mode, the serial interface is
the only function which remains active.

Line interface

DC

CHARACTERISTICS (PINS LN, SLPE, REG, CST, LVI,

LCC, RGL

AND GND; BIT CRC)

The IC generates a stabilized reference voltage (V

ref

)
between pins LN and SLPE. This reference voltage is
equal to 2.9 V, is temperature compensated and can be
adjusted by means of an external resistor (RVA). It can be
increased by connecting the RVA resistor between
pins REG and SLPE (see Fig.3).

The voltage at pin REG is used by the internal regulator to
generate the stabilized reference voltage and is decoupled
by a capacitor (C

REG

) which is connected to GND. This
capacitor, converted into an equivalent inductance
(see Section “Set impedance”) realizes the set impedance
conversion from its DC value (R

SLPE

) to its AC value

(Z

SET

in the audio-frequency range). Figure 4 illustrates
the reference voltage supply configuration. As can be seen
from Fig.4, part of the line current flows into the Z

SET

impedance network and is not sensed by the UBA1707.
Therefore using the RVA resistor to change value of the
reference voltage will also modify all parameters related to
the line current such as:

• The automatic gain control

• The DC mask management

• The low voltage area characteristics.

In the same way, changing the value of Z

SET

also affects
the characteristics. The IC has been optimized for
V

ref

= 2.9 V and Z

SET

= 619 Ω.

The IC regulates the line voltage at pin LN which can be
calculated as follows:

Where:

I

line

= line current

I

ZSET

= current flowing through Z

SET

I* = current consumed between LN and GND
(approximately 100 µA).

The preferred value for R

SLPE

is 10 Ω. Changing R

SLPE

will
affect more than the DC characteristics; it also influences
the transmit gain, the gain control characteristics, the
sidetone level and the maximum output swing on the line.
However, for compliance with CTR 21 8.66 Ω is the best
value for R

SLPE

.

Fig.3 Reference voltage adjustment with RVA.

(1) Influence of RVA on V

ref

.

(2) V

ref

without influence of RVA.

handbook, halfpage

8.5

2.5

(1)

(2)

10

5

10

4

10

3

10

6

MGK706

3.5

4.5

6.5

5.5

7.5

V

ref

(V)

RVA (Ω)

V

LN

V

refRSLPEISLPE

×+=

I

SLPEIlineIZSET

I* I

lineIZSET

–≅––=

1999 Feb 17 7

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

Fig.4 Reference voltage supply configuration.

handbook, full pagewidth

MGK707

R

p

V

d

35 kΩ

R

d

4 kΩ

*I

C

REG

4.7 µF

I

SLPE

R

SLPE

10 Ω

REG GNDSLPE

I

ZSET

Z

SET

619 Ω

I

LN

I

line

LN+

UBA1707

LN

Fig.5 Line current settling simplified configuration.

handbook, full pagewidth

MGK708

R

p

V

d

35 kΩ

R

d

4 kΩ

C

REG

4.7 µF

I

SLPE

R

SLPE

10 Ω

REG GND LCC EHISLPE

Z

SET

619 Ω

I

ZSET

R

exch

V

exch

V

EHI

I

LN

V

ref

V

CE

(TNSW)

TN

SW

I

line

V

line

Z

line

LN+

LN−

UBA1707

LN

HOOK SWITCH
MANAGEMENT

1999 Feb 17 8

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

The DC line current flowing into the set is determined by
the exchange supply voltage (V

exch

), the feeding bridge

resistance (R

exch

), the DC resistors of the telephone line

(R

line

) and the set (R

SET

), the reference voltage (V

ref

) and
the voltage introduced by the transistor (TNSW) used as
line interrupter (see Fig.5). With a line current below I

low

(8 mA with Z

SET

= 619 Ω), the internal reference voltage

(V

ref

) is automatically adjusted to a lower value. This
means that more sets can operate in parallel with DC line
voltages (excluding the polarity guard) down to 1.2 V.
At line current below I

low

, the circuit has limited transmit

and receive levels. This is called the low voltage area.
Figure 6 shows in more details how the UBA1707, in

association with some external components, manages the
line interrupter (TNSWexternal transistor).

In on-hook conditions (voltage at pin EHI is LOW), the
voltage at pin LCC is pulled-up to the supply voltage level
(VCC) to turn off the TP

DARL

transistor. As a result, because

of the R

PLD

resistor, the TNSWand TN

ON-HOOK

transistors

are switched off. The TN

ON-HOOK

transistor disconnects

the R

LVI

resistor from the LN− line terminal in order to

guarantee a high on-hook impedance.

In off-hook conditions (voltage at pin EHI is HIGH), an
operational amplifier drives (at pin LCC) the base of
TP

DARL

which forms a current amplifier structure in
association with TNSW. The line current flows through
TNSW transistor. The TN

ON-HOOK

transistor is forced into
deep saturation. A virtual ground is created at pin LVI
because of the operational amplifier. A DC current (I

LVI

) is

sourced from pin LVI into the R

LVI

resistor in order to
generate a voltage source. Thus the voltage between pin
GND and the negative line terminal (LN−) becomes:

VCE (TNSW)=R

LVI

× I

LVI+VCE

(TN

ON-HOOK

) ≅ R

LVI

× I

LVI

The voltage V

line

between the line terminals LN+ and LN−

can be calculated as follows:
V

line

≅ V

ref+RSLPE

× (I

line

− I

ZSET

)+VCE(TNSW)

Where:

I

line

= line current

I

ZSET

= current flowing through Z

SET

.

1999 Feb 17 9

Philips Semiconductors Product specification

Cordless telephone, answering machine

line interface

UBA1707

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a

ndbook, full pagewidth

MGK709

CURRENT

REGULATION

MODE

MANAGEMENT

I

LVIV

200 nA

V

EHI

C

REG

4.7 µF

I

LVI

R

PLU

150 kΩ

V

CC

TP

DARL

CRC

R

RGL

7.15 kΩ

C

LVI

470 pF

TN

ON-HOOK

TN

SW

D

PROT

D

SW

R

PLD

20 kΩ

R

ON-HOOK

100 kΩ

C

CST

22 pF

GNDLVIRGL CST

LCC

SLPE

LN

8.2 V

I

line

LN−

V

d

R

d

4 kΩ

R

p

35 kΩ

REG

EHI

UBA1707

LN+

V

ref

I

LN

I

SLPE

I

line

V

line

I

ZSET

Z

SET

619 Ω

R

SLPE

10 Ω

R

LVI

1 MΩ

CURRENT

LIMITATION

Fig.6 Line interrupter management and DC mask regulation configuration.

Bit names are given in italics.

1999 Feb 17 10

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

The UBA1707 offers the possibility to choose two kinds of
regulations for the DC characteristic between the line
terminals LN+ and LN− (see Fig.7):

• Voltage regulation mode

• Current regulation mode.

The regulation mode is selected by the bit CRC via the
serial interface.

The DC mask regulation is realised by adjusting the DC
voltage V

CE

(TNSW) between pin GND and line terminal

LN− as a function of the line current.

Voltage regulation mode

In voltage regulation mode (bit CRC at logic 0),
VCE(TNSW) voltage is fixed by means of a 200 nA DC
constant current I

LVIV

flowing through R

LVI

.

Fig.7 General form of the DC mask as a function

of regulation mode.

(1) Low voltage area.
(2) Small slope (determined by R

SLPE

).

(3) Small slope (dashed line; determined by R

SLPE

) in voltage

regulation mode.
High slope (full line; determined by R

SLPE

, R

LVI

and R

RGL

) in

current regulation mode.

(4) Current limitation.

handbook, halfpage

MGK710

V

line

I

line

I

prot

(4)

I

knee

I

low

(1) (2) (3)

Therefore VCE(TNSW) ≅ R

LVI

× I

LVIV

= 200 mV in typical

application (see Fig.18).
The slope ∆V

line

/∆I

line

of the V

line

, I

line

characteristic is

R

REGV

≅ R

SLPE.

Current regulation mode

In current regulation mode (bit CRC at logic 1), when the
line current is lower than I

knee

= 35 mA (with

Z

SET

= 619 Ω), VCE(TNSW) is fixed by means of a 200 nA

DC constant current I

LVIV

flowing through R

LVI

. When the
line current is higher than 35 mA, an additional current
(proportional to the line current) flows through R

LVI

. As a

result, TN

SW

works as a DC voltage source increasing with

the line current. V

CE

(TNSW) can be calculated as follows:

Where:

I

line

= line current

R

RGL

= resistor connected at pin RGL.

The slope ∆V

line

/∆I

line

of the V

line

, I

line

characteristic is
determined by the ratio of resistors connected at
pins SLPE, LVI and RGL, and can be calculated as

follows: in
typical application (see Fig.18).

Current limitation

Whatever the selected mode is, the line current is limited
to approximately 145 mA. This current is sensed on SLPE,
for this purpose the external zener diode must be
connected between pins LN and SLPE. The speech
function no longer operates in this condition.

E

LECTRONIC HOOK SWITCH CONTROL (PIN EHI)

The electronic hook switch input (EHI) controls the state of
TP

DARL

transistor. When the voltage applied at pin EHI is

LOW, TP

DARL

transistor is turned off. Voltage at pin LCC is

pulled up to supply voltage (VCC). TNSWand TN

ON-HOOK

transistors are also turned off by means of a pull-down
resistor (R

PLD

). When the voltage applied at pin EHI is

HIGH, TP

DARL

transistor is driven by the operational
amplifier at pin LCC and the regulation mode selected is
operating. An internal 165 kΩ pull-up resistor is connected
between pins LCC and VCC.

V

CETNSW

()R

LVI

R

SLPE

R

RGL

--------------- -

I

lineIknee

–()I

LVIV

+×







×≅

R

REGCRSLPERLVI

R

SLPE

R

RGL

--------------- -

1400 Ω=×+≅

1999 Feb 17 11

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

The EHI input can also be used for pulse dialling or
register recall (timed loop break). During line breaks
(voltage at pin EHI is LOW or open-circuit), the voltage
regulator is switched off and the capacitor at pin REG is
internally disconnected to prevent its discharge. As a
result, the voltage stabilizer will have negligible switch-on
delay after line interruptions. This minimizes the
contribution of the IC to the current waveform during pulse
dialling or register recall.

When the UBA1707 is in power-down mode (bit PD at
logic 1), the TP

DARL

transistor is forced to be turned off

whatever the voltage applied at pin EHI.

S

ET IMPEDANCE

In the audio frequency range, the dynamic impedance
between pins LN and GND (illustrated in Fig.8) is mainly
determined by the Z

SET

impedance.

The impedance introduced by the external TNSW transistor
connected between pin GND and the negative line
terminal (LN−) is negligible.

Fig.8 Equivalent impedance between

LN and GND.

Leq=C

REG

× R

SLPE

× R

P

RP= internal resistance = 35 kΩ.

handbook, halfpage

LN

GND

SLPE

R

SLPE

C

REG

REG

Z

SET

4.7 µF

619 Ω

10 Ω

R

P

V

ref

L

EQ

MGL215

TRANSMIT AMPLIFIER (PINS TXI+ AND TXI−)
The UBA1707 has symmetrical transmit inputs TXI+ and

TXI−. The input impedance between pins TXI+ or TXI− and
GND is 21 kΩ. The voltage gain from pins TXI+ or TXI− to
pin LN is set at 11.6 dB with 600 Ω line load (Z

line

) and
619 Ω set impedance. The inputs are biased at
2 × Vd≅ 1.4 V, with Vd representing the diode voltage.
Automatic gain control is provided on this amplifier for line
loss compensation.

R

ECEIVE AMPLIFIER (PINS RXI AND RXO; BIT RXM)

The receive amplifier (see Fig.9) has one input (RXI) and
one output (RXO). The input impedance between pins
RXI and GND is 21 kΩ. The rail-to-rail output stage is
designed to drive a 500 µA peak current. The output
impedance at pin RXO is approximately 100 Ω.

The voltage gain from pin RXI to pin RXO is set at 37.9 dB.
This gain value compensates typically the attenuation of
the anti-sidetone network (see Fig.10). The output as well
as the input are biased at 2 × Vd≅ 1.4 V. Automatic gain
control is provided on this amplifier for line loss
compensation. This amplifier can be muted by activating
the receive mute function (bit RXM at logic 1).

1999 Feb 17 12

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

Fig.9 Receive amplifier.

handbook, full pagewidth

MGK711

VI

VI

RXM

2V

d

2V

d

from AGC

RXI

RXO

UBA1707

Bit names are given in italics.

SIDETONE SUPPRESSION
The UBA1707 anti-sidetone network comprising

Z

SET

//Z

line

, R

ast1

, R

ast2

, R

ast3

, R

SLPE

and Z

bal

(see Fig.10)
suppresses the transmitted signal in the received signal.
Maximum compensation is obtained when the following
conditions are fulfilled:

R

SLPE

× R

ast1=ZSET

× (R

ast2+Rast3

)

Z

bal

=k×Z

line

The scale factor ‘k’ is chosen to meet the compatibility with
a standard capacitor from the E6 or E12 range for Z

bal

.

In practice, Z

line

varies considerably with the line type and

the line length.

k

R

ast2

R

ast3RSLPE

+()×()

R

ast1RSLPE

×()

--------------------------------------------------------------------

=

Therefore, the value chosen for Z

bal

should be for an
average line length which gives satisfactory sidetone
suppression with short and long lines.

The suppression also depends on the accuracy of the
match between Z

bal

and the impedance of the average

line.
The anti-sidetone network for the UBA1707 (see Fig.18)

attenuates the receiving signal from the line by 38 dB
before it enters the receiving amplifier. The attenuation is
almost constant over the whole audio frequency range.
A Wheatstone bridge configuration (see Fig.11) may also
be used.

More information on the balancing of an anti-sidetone
bridge can be obtained in our publication

“Applications

Handbook for Wired Telecom Systems, IC03b”

.

handbook, full pagewidth

MGL216

I

m

Z

RXI

RXI

R

ast1

R

ast3

R

ast2

SLPE

R

SLPE

GND

Z

line

Z

SET

LN

Z

bal

Fig.10 Equivalent circuit of UBA1707 anti-sidetone bridge.

1999 Feb 17 13

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

Fig.11 Equivalent circuit of an anti-sidetone network in a Wheatstone bridge configuration.

handbook, full pagewidth

MGL217

I

m

Z

RXI

RXI

Z

bal

R

ast1

SLPE

R

SLPE

GND

Z

line

Z

SET

LN

R

A

AUTOMATIC GAIN CONTROL (PIN AGC; BITS RAGC1,
RAGC2, SAGC

AND AGC)

The UBA1707 performs automatic line loss compensation.
The automatic gain control varies the gain of the transmit
amplifier and the gain of the receive amplifier in
accordance with the DC line current. The control range is

6.5 dB (which roughly corresponds to a line length of

5.5 km for a 0.5 mm diameter twisted-pair copper cable
with a DC resistance of 176 Ω/km and an average
attenuation of 1.2 dB/km).

When the line current is greater than I

stop

, the voltage

gains are minimum. When the line current is less than I

start

,
the voltage gains are maximum. When the AGC pin is
connected to pin GND, the start line current (I

start

) can be
chosen between 22.5 and 29.5 mA via bits RAGC1 and
RAGC2 through the serial interface. Two values for the
I

stop/Istart

ratio (slope of the AGC) are possible via the bit
SAGC through the serial interface. When bit SAGC is at
logic 0 then I

stop

= 2.7 × I

start

(optimized for voltage
regulation mode). When SAGC is at logic 1 then
I

stop

= 1.9 × I

start

(optimized for current regulation mode).

An external resistor R

AGC

(connected between pins GND

and AGC) enables the I

start

and I

stop

line currents to be

increased (the ratio between I

start

and I

stop

is not affected
by this external resistor). So internal and external
adjustments of the automatic gain control allow
optimization of the IC for many configurations of exchange
supply voltage and feeding bridge resistance. Part of the
line current flows into the Z

SET

impedance network. The IC

has been optimized for Z

SET

= 619 Ω. Changing this 619 Ω

value slightly modifies I

stop

and I

start

line currents as well as

the value of the two AGC slopes.
The automatic gain control function can be disabled by

setting the AGC bit to logic 0 via the serial interface or
when pin AGC is left open-circuit. In this case both of the
voltage gains are maximum.

1999 Feb 17 14

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

Auxiliary amplifier (pins AXI and AXO; bit AXM)

The auxiliary amplifier (see Fig.12) has one input (AXI) and one output (AXO). The input impedance between pins AXI
and GND is 3.8 kΩ. The rail-to-rail output stage is designed to drive a 500 µA peak current. The output impedance at pin
AXO is approximately 100 Ω.

The output as well as the input are biased at 2 × Vd≅ 1.4 V DC voltage. The voltage gain from pin AXI to pin AXO is set
at 31.8 dB.The amplifier can be muted by setting bit AXM at logic 1 via the serial interface. In this case, the input
impedance between pins AXI and GND is infinite.

Fig.12 Auxiliary amplifier.

handbook, full pagewidth

MGK712

AXM

2V

d

AXI

AXO

UBA1707

Bit names are given in italics.

Loudspeaker channel (see Fig.13)
L

OUDSPEAKER AMPLIFIER (PINS LSAI1, LSAI2, LSAO AND

LSPGND; BITS LSPD, LSA1 AND LSA2)
The loudspeaker amplifier has two symmetrical inputs

LSAI1 and LSAI2 selectable independently by the bits
LSA1 and LSA2 respectively. The input impedance
between pins LSAI1or LSAI2 and GND is typically 21 kΩ.
Each of these two inputs stages can accommodate signals
up to 500 mV (RMS) at room temperature for less than 2%
of Total Harmonic Distortion (THD) at minimum voltage
gain.

The inputs are biased at 2 × Vd≅ 1.4 V DC voltage
(whatever the state of bits LSA1 and LSA2).

The rail-to-rail output stage is designed to power a
loudspeaker connected as a single-ended load (between
pins LSAO and LSPGND). The output LSAO is able to
drive at least a 150 mA peak current.

As a result, it can drive loudspeaker loads down to 8 Ω at
V

CC

= 4.0 V and 16 Ω at VCC= 5.5 V. The output is biased

at

1

⁄2VCC. Its output voltage capability is specified for

continuous wave drive and depends on the value of V

CC

.

In order to avoid crosstalk from the loudspeaker to other
amplifiers, the loudspeaker current flows via pin LSPGND.
This pin must be externally connected to pin GND.

The nominal value of the voltage gain for maximum
volume from pins LSAI1 or LSAI2 to pin LSAO is set at
28 dB.

This amplifier is no longer supplied by setting the LSPD bit
at logic 1 via the serial interface.

1999 Feb 17 15

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

Fig.13 Loudspeaker channel.

Bit names are given in italics.

handbook, full pagewidth

MGK713

LSAI1

LSAI2

2V

d

2V

d

LSPD

LSPD

LSPD

LSA2

LSA1

0.5V

CC

DYNAMIC LIMITER

VOLUME CONTROL

V

CC

UBA1707

DLCI

LSPD

VOL0
TO
VOL2

DLC

LSPGND

LSAO

3

VI

VI

IV

LSP

C

DLC

C

LSAO

DYNAMIC LIMITER (PIN DLC; BIT DLCI)
The dynamic limiter of the UBA1707 prevents clipping of

the loudspeaker output stage and protects the operation of
the circuit when the supply voltage at VCC falls below

2.7 V.
Hard clipping of the loudspeaker output stage is prevented

by rapidly reducing the gain when the output stage starts
to saturate. The time in which gain reduction is effected
(clipping attack time) is approximately a few milliseconds.
The circuit stays in the reduced gain mode until the peaks
of the loudspeaker signals no longer cause saturation.
The gain of the loudspeaker amplifier then returns to its
normal value within the clipping release time (typically
250 ms). Both attack and release times are proportional to
the value of the capacitor C

DLC

. The total harmonic
distortion of the loudspeaker output stage, in reduced gain
mode, stays below 5% up to 10 dB (minimum) of input
voltage overdrive [providing V

LSAI

is below

500 mV (RMS)].

When the supply voltage drops below an internal threshold
voltage of 2.7 V, the gain of the loudspeaker amplifier is
rapidly reduced (approximately 1 ms). When the supply
voltage exceeds 2.7 V, the gain of the loudspeaker
amplifier is increased again.

The hard clipping of the dynamic limiter can be inhibited by
setting the DLCI bit at logic 1, via the serial interface.

The dynamic limiter is no longer supplied by setting the
LSPD bit at logic 1. In this case, the C

DLC

capacitor charge
is maintained to allow the gain of the loudspeaker amplifier
to return to its nominal value as soon as the loudspeaker
channel is supplied again.

V

OLUME CONTROL (BITS VOL0, VOL1 AND VOL2)

The loudspeaker amplifier voltage gain can be reduced in
steps of 3 dB via the serial interface (via bits VOL0, VOL1
and VOL2). These bits provide 7 steps of voltage gain
adjustment. The voltage gain is maximum when all bits are
at logic 1 and is reduced by 21 dB when all bits are at
logic 0.

1999 Feb 17 16

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

General purpose switches (pins SWI1, SWI2 and
SWI3; bits SWC1, SWC2 and SWC3)

The UBA1707 is equipped with 3 general purpose
open-collector switches which short the pins SWI1, SWI2
and SWI3 to ground. They are respectively controlled by
bits SWC1, SWC2 and SWC3 and have an operating
voltage limited to 12 V. The outputs have to be current
biased.

For a bias current between 2 and 20 mA, the AC
impedance is 30 Ω maximum.

Serial interface (pins DATA, CLK and EN)

A simple 3-wire unidirectional serial bus is used to program
the circuit. The 3 wires of the bus are EN, CLK and DATA.
The data sent to the device is loaded in bursts framed by
EN. Programming clock edges (falling edges) and their
appropriate data bits are ignored until EN goes active
HIGH. The programmed information is loaded into the
addressed register when EN returns inactive (LOW) or left
open-circuit.

During normal operation, EN should be kept LOW. Only
the last 8 bits serially clocked into the device are retained
within the programming register. Additional leading bits
are ignored and no check is made on the number of clock
pulses. It can always capture new programming data even
during global power-down (bit PD at logic 1).

Data is entered with the most significant bit first.
The leading 6 bits make up the data field (bits D0 to D5)
while the trailing 2 bits are the address field
(bits ADO and AD1). The first bit entered is D5, the last
bit AD0. This organisation allows to send only the number
of bits of the addressed register.

Figure 16 shows the serial timing diagram. Table 1 gives
the list of registers.

When the supply voltage V

CC

drops below 2.5 V, all
register files are set in the initial state (see Table 1) defined
by the power-up reset. At start-up, the circuit is in
power-down mode.

In the event that the IC is used in a noisy environment, it is
advised to periodically refresh the content of registers.

1999 Feb 17 17

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

Table 1 Register description

Note

1. See Section “Automatic gain control (pin AGC; bits RAGC1, RAGC2, SAGC and AGC)”.

BIT

NAME

FUNCTION POLARITY DATA ADDRESS

STATE AT

POWER-UP

RESET

Register 0: general purpose switches state and DC mask regulation mode

SWC1 SWI1 output connection 0: SWI1 switched off D0 (AD1, AD0) = (0,0) 0

1: SWI1 switched on

SWC2 SWI2 output connection 0: SWI2 switched off D1 0

1: SWI2 switched on

SWC3 SWI3 output connection 0: SWI3 switched off D2 0

1: SWI3 switched on
un unused must be set to logic 0 D3 0
CRC current regulation mode 0: voltage regulation D4 0

1: current regulation

Register 1: automatic gain control

RAGC1 AGC range selection 1 D0 (AD1, AD0) = (0,1) 0
RAGC2 AGC range selection 2 D1 0
SAGC AGC slope selection 0: 2.7 type slope; note 1 D2 0

1: 1.9 type slope; note 1
AGC line loss compensation mode 0: AGC inhibited D3 0

1: AGC enabled

Register 2: loudspeaker channel

LSA1 loudspeaker channel input 1

selection

0: LSAI1 unselected D0 (AD1, AD0) = (1,0) 0

1: LSAI1 selected
LSA2 loudspeaker channel input 2

selection

0: LSAI2 unselected D1 0

1: LSAI2 selected
LSPD loudspeaker channel power-down 0: channel on D2 0

1: channel in power-down
VOL0 volume control (least significant bit) D3 0
VOL1 volume control D4 0
VOL2 volume control (most significant bit) D5 0

Register 3: mute functions and power-down

AXM auxiliary amplifier mute 0: amplifier enabled D0 (AD1, AD0) = (1,1) 0

1: amplifier muted
RXM receive amplifier mute 0: amplifier enabled D1 0

1: amplifier muted
PD reduced consumption mode 0: normal operating mode D2 1

1: power-down mode
DLCI dynamic limiter inhibit 0: limiter enabled D3 0

1: limiter inhibited

1999 Feb 17 18

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

supply voltage on pin V

CC

GND − 0.4 5.5 V

V

LN

positive continuous line voltage on pin LN GND − 0.4 12.0 V
repetitive line voltage during switch-on or

line interruption

GND − 0.4 13.2 V

V

SWIn

voltage on pins SWI1, SWI2, and SWI3 continuous GND − 0.4 12.0 V

during switching GND − 0.4 13.2 V

V

n(max)

maximum voltage on all other pins GND − 0.4 VCC+ 0.4 V

I

LN

current sunk by pin LN see Figs 14 and 15 − 150 mA

I

SWIn

continuous current sunk by
pins SWI1, SWI2, and SWI3

bit SWCn = 1 − 20 mA

P

tot

total power dissipation T

amb

=75°C;

see Figs 14 and 15

UBA1707T − 625 mW
UBA1707TS − 416 mW

T

stg

IC storage temperature −40 +125 °C

T

amb

operating ambient temperature −25 +75 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air

UBA1707T 70 K/W
UBA1707TS 104 K/W

1999 Feb 17 19

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

Fig.14 Safe operating area (UBA1707T).

LINE T

amb

(°C) P

tot

(mW)

(1) 45 1000
(2) 55 875
(3) 65 750
(4) 75 625

When power is delivered to a loudspeaker with RL impedance, the curves must be shifted to the left by:

with maximum power dissipated by the loudspeaker amplifier (dotted line given for V

CC

= 5.5 V, RL=16Ω).∆V

ref

V

CC

2

2 π2RLILN×××

------------------------------------------

=

The line current value can be calculated from ILN value as follows:

where R

SET

is the resistive part of Z

SET

.I

line

ILNR

SETRSLPE

+()V

LNVSLPE

–+×

R

SET

----------------------------------------------------------------------------------------------

=

handbook, full pagewidth

12

150

30

23456 891011

MGK714

7

50

70

90

110

130

V

LN

− V

SLPE

(V)

I

LN

(mA)

(1)(2)(3)(4)

no power delivered to the loudspeaker

with power delivered to the loudspeaker

∆ V

ref

1999 Feb 17 20

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

LINE T

amb

(°C) P

tot

(mW)

(1) 45 666
(2) 55 583
(3) 65 500
(4) 75 416

Fig.15 Safe operating area (UBA1707TS).

When power is delivered to a loudspeaker with RL impedance, the curves must be shifted to the left by:

with maximum power dissipated by the loudspeaker amplifier (dotted line given for V

CC

= 5.5 V, RL=16Ω).∆V

ref

V

CC

2

2 π2RLILN×××

------------------------------------------

=

The line current value can be calculated from ILN value as follows:

where R

SET

is the resistive part of Z

SET

.I

line

ILNR

SETRSLPE

+()V

LNVSLPE

–+×

R

SET

----------------------------------------------------------------------------------------------

=

handbook, full pagewidth

12

140

20

24 8

MGK715

637510119

40

60

80

100

120

V

LN

− V

SLPE

(V)

I

LN

(mA)

(1)(2)(3)

no power delivered to the loudspeaker

with power delivered to the loudspeaker

∆ V

ref

(4)

1999 Feb 17 21

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

CHARACTERISTICS

I

line

= 15 mA; VCC= 3.3 V; R

SLPE

=10Ω; AGC pin connected to GND; Z

line

= 600 Ω; Z

SET

= 619 Ω; EHI = HIGH;

f = 1 kHz; T

amb

=25°C; bit AGC at logic 1, all other configuration bits at logic 0; measured in test circuit of Fig.17;

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply (pins V

CC

and GND; bit PD)

V

CC

operating supply voltage 3.0 − 5.5 V

I

CC

current consumption from
pin V

CC

− 2.2 3.2 mA

I

CC(pd)

current consumption from
pin VCC in power-down mode

bit PD = 1 − 110 150 µA

Line interface (pins LN, SLPE and REG)

DC

CHARACTERISTICS

V

ref

stabilized voltage between
pins LN and SLPE

I

line

= 11 to 140 mA 2.6 2.9 3.2 V

V

LN

DC line voltage between pins
LN and GND

I

line

=2mA − 1.2 − V

I

line

=4mA − 1.8 − V

I

line

= 15 mA 2.7 3.0 3.3 V

I

line

= 140 mA − 4.35 − V

V

LN(Rext)

DC line voltage between pins
LN and GND with an external
resistor R

VA

R

VA(SLPE−REG)

=8kΩ− 4.5 − V

∆V

LN(T)

DC line voltage variation with
temperature referenced to
25 °C

T

amb

= −25 to +75 °C − 8.0 − mV

Masks regulation (pins LCC, LVI, CST and RGL; bit CRC)

DC

CHARACTERISTICS

I

LCC(max)

maximum current sunk by
pin LCC

500 −− µA

R

int(LCC)

internal resistance between
pins VCCand LCC

− 165 − kΩ

Voltage regulation mode

I

LVIV

current sourced from pin LVI bit CRC = 0 − 200 − nA

Current regulation mode

I

knee

start line current for current
regulation mode

bit CRC = 1 − 35 − mA

R

REGC

DC mask slope in current
regulation mode

I

line>Iknee

; R

LVI

=1 MΩ;

R

RGL

= 7.15 kΩ; bit CRC = 1

− 1.4 − kΩ

Current limitation

I

prot

current limitation level − 145 − mA

1999 Feb 17 22

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

Electronic hook-switch control (pin EHI)

V

IH

HIGH-level input voltage 2.3 − VCC+ 0.4 V

V

IL

LOW-level input voltage VCC= 3.0 to 5.5 V GND − 0.4 − 0.3V

CC

V

I

bias

input bias current input level = HIGH 1 2 5 µA

Transmit amplifier (pins TXI+, TXI− and LN)
Z

i

 input impedance between pins TXI+ and GND

or TXI− and GND

− 21 − kΩ

between pins TXI+ and TXI−− 36 − kΩ

G

v(TX)

voltage gain from TXI+/TXI−
to LN

V

TXI

= 50 mV (RMS) 10.6 11.6 12.6 dB

∆G

v(TX)(f)

voltage gain variation with
frequency referenced to 1 kHz

f = 300 to 3400 Hz −±0.3 − dB

∆G

v(TX)(T)

voltage gain variation with
temperature referenced to
25 °C

T

amb

= −25 to +75 °C −±0.3 − dB

CMRR common mode rejection ratio − 65 − dB
PSRR power supply rejection ratio − 36 − dB
V

LN(max)(rms)

maximum sending signal
(RMS value)

I

line

= 15 mA; THD = 2% 1.2 1.4 − V

I

line

= 4 mA; THD = 10% − 0.26 − V

V

iTX(max)(rms)

maximum transmit input
voltage (RMS value) for
2% THD on pin LN

I

line

=15mA − 0.35 − V

I

line

=90mA − 0.75 − V

V

no(LN)

noise output voltage at pin LN pins TXI+ and TXI−

short-circuited through
200 Ω in series with 10 µF;
psophometrically weighted
(P53 curve)

−−74 − dBmp

Receive amplifier (pins RXI and RXO; bit RXM)

Zi input impedance between pins

RXI and GND

− 21 − kΩ

G

v(RX)

voltage gain from RXI to RXO V

RXI

= 2 mV (RMS) 36.9 37.9 38.9 dB

∆G

v(RX)(f)

voltage gain variation with
frequency referenced to 1 kHz

f = 300 to 3400 Hz −±0.2 − dB

∆G

v(RX)(T)

voltage gain variation with
temperature referenced to
25 °C

T

amb

= −25 to +75 °C −±0.3 − dB

PSRR power supply rejection ratio − 68 − dB
THD total harmonic distortion V

RXI

= 2 mV (RMS) − 0.03 − %

V

RXI

= 12.5 mV (RMS) − 2 − %

V

RXI

= 19.5 mV (RMS);

I

line

=90mA

− 2 − %

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Feb 17 23

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

V

no(RXO)(rms)

noise output voltage at
pin RXO (RMS value)

RXI open-circuit;
psophometrically weighted
(P53 curve)

−−81 − dBVp

∆G

v(RX)(m)

voltage gain reduction from
pin RXI to RXO when muted

V

RXI

= 10 mV (RMS);

bit RXM = 1

− 80 − dB

Automatic gain control (pin AGC; bits RAGC1, RAGC2, SAGC and AGC)

∆G

v(trx)

gain control range for transmit
and receive amplifiers with
respect to I

line

=15mA

I

line

=90mA − 6.5 − dB

I

start

highest line current for
maximum gain

bits RAGC1 = 1; RAGC2 = 1 − 22.5 − mA
bits RAGC1 = 1; RAGC2 = 0 − 25 − mA
bits RAGC1 = 0; RAGC2 = 1 − 27 − mA
bits RAGC1 = 0; RAGC2 = 0 − 29.5 − mA

I

stop

lowest line current for
minimum gain when
I

start

=23mA

bits SAGC = 0; RAGC1 = 1;
RAGC2 = 1

− 62 − mA

bits SAGC = 1; RAGC1 = 1;
RAGC2 = 1

− 43 − mA

∆G

v(trxoff)

gain variation for transmit and
receive amplifiers when AGC
is off

bit AGC = 0;
I

line

= 15 to 140 mA

−−±0.2 dB

Amplifiers

A

UXILIARY AMPLIFIER (PINS AXI AND AXO; BIT AXM)

Z

i

 input impedance between pins

AXI and GND

− 3.8 − kΩ

G

v(AX)

voltage gain from pin
AXI to AXO

V

AXI

= 2 mV (RMS) 30.8 31.8 32.8 dB

∆G

v(AX)(f)

voltage gain variation with
frequency referenced to 1 kHz

f = 300 to 3400 Hz −±0.2 − dB

∆G

v(AX)(T)

voltage gain variation with
temperature referenced to
25 °C

T

amb

= −25 to +75 °C −±0.2 − dB

PSRR power supply rejection ratio − 79 − dB
V

no(AXO)(rms)

noise output voltage at
pin AXO (RMS value)

pin AXI connected to pin
GND through 200 Ω in series
with 10 µF;
psophometrically weighted
(P53 curve)

−−83 − dBVp

∆G

v(AX)(m)

voltage gain reduction from
pin AXI to AXO when amplifier
muted

V

AXI

= 10 mV (RMS);

bit AXM = 1

− 80 − dB

SYMBOL P ARAMETER CONDITIONS MIN. TYP . MAX. UNIT

1999 Feb 17 24

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

LOUDSPEAKER CHANNEL (PINS LSAI1, LSAI2, LSAO, DLC AND LSPGND;

BITS LSA1, LSA2, LSPD, VOL0, VOL1, VOL2 AND DLCI)

Loudspeaker amplifier

Zi input impedance between pins

LSAI1 or LSAI2 and GND

bits LSA1 = 1, LSA2 = 1 − 21 − kΩ

G

v(LSA)

voltage gain from LSAI1 or
LSAI2 to LSAO for maximum
volume

V

LSAI

= 8 mV (RMS);

bits LSA1 = 1, LSA2 = 1

26.5 28 29.5 dB

∆G

v(LSA)(f)

voltage gain variation with
frequency referenced to 1 kHz

V

LSAI

= 8 mV (RMS);

f = 300 to 3400 Hz

−±0.3 − dB

∆G

v(LSA)(T)

voltage gain variation with
temperature referenced to
25 °C

T

amb

= −25 to +75 °C −±0.3 − dB

V

LSAI(rms)

maximum input voltage
between pins LSAI1 or
LSAI2 and GND (RMS value)

VCC= 5.0 V; G

v(LSA)

= 7 dB;

for 2% of THD in input stage

− 500 − mV

V

no(LSAO)(rms)

noise output voltage at
pin LSAO (RMS value)

pin LSAI1 (with bits
LSA1 = 1, LSA2 = 0) or pin
LSAI2 (with bits LSA1 = 0,
LSA2 = 1) connected to pin
GND through 200 Ω in series
with 10 µF;
psophometrically weighted
(P53 curve)

−−80 − dBVp

Output capability

V

LSAO(p-p)

output voltage capability at pin
LSAO (peak-to-peak value)

VCC= 5.0 V;
G

v(LSA)

= 28 dB;

V

LSAI

= 100 mV (RMS);

RL=16Ω

3.0 3.6 − V

V

CC

= 3.3 V;

G

v(LSA)

= 28 dB;

V

LSAI

= 100 mV (RMS);

RL=8Ω

− 2.0 − V

I

LSAO(max)

 maximum current capability at

pin LSAO (peak value)

150 −− mA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Feb 17 25

Philips Semiconductors Product specification

Cordless telephone, answering machine
line interface

UBA1707

Dynamic limiter

t

att

attack time VCC= 3 V; G

v(LSA)

=28dB

when V

LSAI

jumps from
20 mV (RMS) to
20 mV (RMS) + 10 dB;
bit DLCI = 0

−−5ms

when V

CC

drops below

2.7 V; bit DLCI = don’t
care

− 1 − ms

t

rel

release time VCC= 3 V; G

v(LSA)

= 28 dB;

when V

LSAI

jumps from
20 mV (RMS) + 10 dB to
20 mV (RMS); bit DLCI = 0

− 250 − ms

THD total harmonic distortion at

V

LSAI

= 20 mV (RMS) + 10 dB

VCC=3V; G

v(LSA)

= 28 dB;

t>t

att

− 0.5 5 %

Volume control

∆G

v(LSA)

voltage gain adjustment range bits (VOL0, VOL1, VOL2)

from (0, 0, 0) to (1, 1, 1)

− 21 − dB

∆G

v(LSA)(s)

voltage gain adjustment step VOL0 from 0 to 1 − 3 − dB

Switches (pins SWI1, SWI2 and SWI3; bits SWC1, SWC2 and SWC3)

Z

i(off)

 AC impedance between pins

SWIn and GND when not
selected

bit SWCn = 0 700 −− kΩ

Z

i(on)

 AC impedance between pins

SWIn and GND when selected

2mA<I

SWIn

< 20 mA;

bit SWCn = 1

−−30 Ω

Serial interface (pins DATA, CLK and EN)

V

IH

HIGH-level input voltage 2.3 − VCC+ 0.4 V

V

IL

LOW-level input voltage VCC= 3 to 5.5 V GND − 0.4 − 0.3V

CC

V

I

bias

input bias current input level = HIGH 1 2 5 µA

C

i

input capacitance at pins
DATA, CLK and EN

− 4 − pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Feb 17 26

Philips Semiconductors Product specification

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SERIAL BUS TIMING CHARACTERISTICS

V

CC

= 3.3 V; T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER MIN. MAX. UNIT

Serial programming clock; pin CLK

f

clk

clock frequency 0 300 kHz

Enable programming; pin EN

t

START

delay to falling clock edge 1 −µs

t

END

delay from last rising clock edge 0.1 −µs

t

W(min)

minimum inactive pulse width 1.5 −µs

t

SU;EN

enable set-up time to next clock edge 0.1 −µs

Serial data; pin DATA

t

SU;DATA

input data to clock set-up time 2 −µs

t

HD;DATA

input data to clock hold time 2 −µs

Fig.16 Serial bus timing diagram.

handbook, full pagewidth

MGK716

t

SU;DATA

1/f

clk

t

SU;EN

t

END

t

W

t

HD;DATA

t

START

CLK

DATA

EN

D5 D4 AD1 AD0

1999 Feb 17 27

Philips Semiconductors Product specification

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UBA1707

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TEST AND APPLICATION INFORMATION

d

book, full pagewidth

MGK717

LN SWI3GND SWI1 EHISWI2

222 2019 21 11

DATA12EN13CLK14RXI10RXO

8

LCC CST REGLVI

674 3

AGC9RGL

5

LSPGND

123

TXI+

18

TXI−

17

V

CC

I

CC

25

AXI

15

DLC

28

AXO

16

LSAI2

27

LSAI1

26

LSAO

24

from

microcontroller

UBA1707

C

RXI

220 nF

V

RXI

C

LVI

470 pF

C

line

100 µF

C

EMC

10 nF

C

REG

4.7 µF

C

LSAO

220 µF

R

LVI

1 MΩ

R

RGL

7.15 kΩ

SLPE

R

SLPE

10 Ω

R

LSAO

16 Ω

Z

SET

619 Ω

Z

line

600 Ω

C

AXI

C

DLC

1 µF

C

LSAI2

220 nF

220 nF

C

CST

22 pF

C

LSAI1

V

AXI

V

LSAI2

V

LSAI1

220 nF

TN

ON-HOOK

MPSA42

TP

DARL

MPSA92

100 kΩ

R

ON-HOOK

D

PROT

1N4148

R

PLD

20 kΩ

D

SW

1N4148

TN

SW

BUX86

V

VCC

V

LN

I

line

V

TXI

C

VCC

10 µF

C

LCC

6.8 pF

Fig.17 Test circuit.

1999 Feb 17 28

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UBA1707

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full pagewidth

MGK718

LN SWI2 SWI1 EHISWI3

2192021 11

DATA12EN13CLK14RXI10RXO

8

LCC CST REGLVI

674 3

AGC9RGL5DLC28LSPGND

23

TXI+

18

TXI−

17

V

CC

I

CC

25

SLPE

1

AXI

15

AXO

16

LSAI2

GND

27

LSAI1

26

LSAO

24

MICROCONTROLLER

UBA1707

C

RXI

100 nF

C

DLC

220 nF

C

LVI

(2)

470 pF

C

VCC

10 µF

C

EMC

(3)

10 nF

C

REG

4.7 µF

C

LSAO

220 µF

C

RXO

R

SLPE

R

ast3

392 Ω

R

LVI

1 MΩ

R

RGL

7.15 kΩ

Z

SET

619 Ω

10 Ω

Z

bal

R

ast2

3.92 kΩ

R

ast1

260 kΩ

BZX79C8V2

C

AXI

100 nF

C

TXIP

100 nF

C

TXIM

100 nF

22

C

LSAI2

100 nF

C

AXO

C

CST

22 pF

C

LSAI1

100 nF

TN

ON-HOOK

MPSA42

TP

DARL

MPSA92

100 kΩ

R

ON-HOOK

D

PROT

1N4148

R

PLD

20 kΩ

D

SW

1N4148

TN

SW

BUX86

(MPSA42

(1)

)

V

VCC

V

LN

BRIDGE

4 × BAS11

a/b

b/a

BOD
BR211-240

LSP
16 Ω

C

LCC

(4)

6.8 pF

Fig.18 Typical application.

(1) In case of low line current in voltage regulation mode.
(2) Only required in current regulation mode.
(3) To improve EMC performance; necessary for stability.
(4) To improve stability only in current regulation mode.

1999 Feb 17 29

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PACKAGE OUTLINES

UNIT

A

max.

A

1

A2A

3

b

p

cD

(1)E(1) (1)

eHELLpQ

Z

ywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

2.65

0.30

0.10

2.45

2.25

0.49

0.36

0.32

0.23

18.1

17.7

7.6

7.4

1.27

10.65

10.00

1.1

1.0

0.9

0.4

8
0

o
o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1

0.4

SOT136-1

X

14

28

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

c

L

v M

A

e

15

1

(A )

3

A

y

0.25

075E06 MS-013AE

pin 1 index

0.10

0.012

0.004

0.096

0.089

0.019

0.014

0.013

0.009

0.71

0.69

0.30

0.29

0.050

1.4

0.055

0.419

0.394

0.043

0.039

0.035

0.016

0.01

0.25

0.01

0.004

0.043

0.016

0.01

0 5 10 mm

scale

SO28: plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

95-01-24
97-05-22

1999 Feb 17 30

Philips Semiconductors Product specification

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UBA1707

UNIT A

1

A2A

3

b

p

cD

(1)E(1) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

10.4

10.0

5.4

5.2

0.65 1.25

7.9

7.6

0.9

0.7

1.1

0.7

8
0

o
o

0.13 0.10.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

1.03

0.63

SOT341-1 MO-150AH

93-09-08
95-02-04

X

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

(A )

3

A

114

28 15

0.25

y

pin 1 index

0 2.5 5 mm

scale

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

SOT341-1

A

max.

2.0

1999 Feb 17 31

Philips Semiconductors Product specification

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UBA1707

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Feb 17 32

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Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO not recommended

(5)

suitable

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1999 Feb 17 33

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NOTES

1999 Feb 17 34

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NOTES

1999 Feb 17 35

Philips Semiconductors Product specification

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UBA1707

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1999 SCA62
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax.[phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax.[phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax.[phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box2108 MCC,MAKATI,
Metro MANILA, Tel. [phone],Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax.[phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax.[phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
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Tel. [phone] Fax.[phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
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Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax.[phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax.[phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax.[phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax.[phone]
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220050 MINSK, Tel. [phone], Fax. [phone]

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51 James Bourchier Blvd., 1407 SOFIA,
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Tel. [phone], Fax.[phone]
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Tel. [phone], Fax.[phone]
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Tel. [phone], Fax.[phone]
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Tel. [phone], Fax.[phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie BesantRoad, Worli, MUMBAI 400025,
Tel. [phone], Fax.[phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext.2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax.[phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax.[phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

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Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
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Printed in The Netherlands 465002/750/03/pp36 Date of release: 1999 Feb 17 Document order number: 9397 750 04964