Datasheet uba1706 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UBA1706

Cordless telephone line interface

Objective specification
Supersedes data of 1999 Mar 08
File under Integrated Circuits, IC17

1999 Jun 04

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

FEATURES
Line interface

• Low DC line voltage; operates down to 1.2 V (excluding
polarity guard)

• Voltage regulator with adjustable DC voltage

• DC mask for voltage or current regulation (CTR21)

• Line current limitation for protection

• Electronic hook switch control input

• Transmit amplifier with:

– Symmetrical inputs
– Fixed gain
– Large signal handling capability.

• Receive amplifier with fixed gain

• Transmit and receive amplifiers Automatic Gain Control

(AGC) for line loss compensation.

General purpose switches

Two switches with open-collector.

3-wire serial bus interface

APPLICATIONS

• Cordless base stations

• Mains or battery-powered telephone sets.

GENERAL DESCRIPTION

The UBA1706 is a BiCMOS integrated circuit intended for
use in mains-powered telecom terminals. It performs all
speech and line interface functions, DC mask for voltage
or current regulation and electronic hook switch control.
The device also includes general purpose switches.

Most of the characteristics are programmable via a 3-wire
serial bus interface.

Allows control of:

• DC mask (voltage or current regulation)

• Receive amplifier mute function

• AGC:

– On/off
– Slope
–I

line current.

start

• The state of the general purpose switches

• Global power-down mode.

Supply

Operates with external supply voltage from 3.0 to 5.5 V.

ORDERING INFORMATION

TYPE

NUMBER

UBA1706TS SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

NAME DESCRIPTION VERSION

PACKAGE

1999 Jun 04 2

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

QUICK REFERENCE DATA

= 15 mA; VCC= 3.3 V; R

I

line

f = 1 kHz; T

=25°C; bit AGC at logic 1, all other configuration bits at logic 0; measured in the test circuit of Fig.14;

amb

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
I

I

V
R

CC

line

CC

LN

REGC

supply voltage 3.0 − 5.5 V
current consumption from pin V

line current operating range normal operation 11 − 140 mA

DC line voltage 2.7 3.0 3.3 V
DC mask slope in current regulation

mode

G

v(trx)

voltage gain

transmit amplifier from TXI to LN V
receive amplifier from RXI to RXO V

∆G

v(trx)

gain control range for transmit and
receive amplifiers with respect to
I

=15mA

line

=10Ω; AGC pin connected to GND; Z

SLPE

normal operation; bit PD = 0 − 2.2 3.2 mA

CC

power-down mode; bit PD = 1 − 110 150 µA

with reduced performance 3 − 11 mA

I

> 35 mA (typical);

line

R

=1MΩ; R

LVI

bit CRC = 1

= 50 mV (RMS) 10.6 11.6 12.6 dB

TXI

= 2 mV (RMS) 36.9 37.9 38.9 dB

RXI

I

=90mA − 6.5 − dB

line

line

= 7.15 kΩ;

RGL

= 600 Ω; Z

= 619 Ω; EHI = HIGH;

SET

− 1.4 − kΩ

1999 Jun 04 3

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

BLOCK DIAGRAM

handbook, full pagewidth

R

RGL

V

RXI

TXI+
TXI−

AGC

RGL

19

CC

21

9

15
14

8

4

RX PREAMP

2V

d

EHI

TX PREAMP

RAGC2

REG

CRC

RXM

VI

VI

RAGC1

EHI

600 mV

UBA1706

AGC

2

2V

LOW VOLTAGE

SAGC,
AGC

d

300 mV

PART

CURRENT

LIMITATION

SWITCH DRIVER
PROTECTION

200 nA

LINE INTERFACE

LINE
INTERFACE

EHI

V

CC

SLPE

GND

7

RXO

LN

1

Z

SET

R

SLPE

SLPE

24

REG

2

10

5

6

3

EHI
LCC

CST

LVI

C

REG

V

CC

TP

TN

ON-HOOK

DARL

D

TN

SW

C

CST

R

LVI

16, 20, 22, 23

n.c.

9

SERIAL

INTERFACE

12 13 11
EN CLK DATA

SUPPLY

PD

2

SWC1, SWC2

Bit names are given in italics.

Fig.1 Block diagram.

1999 Jun 04 4

GENERAL SWITCHES

MBL039

SWI1

18

SWI2

17

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

PINNING

SYMBOL PIN DESCRIPTION

LN 1 positive line terminal
REG 2 line voltage regulator decoupling
LVI 3 negative line voltage sense input
RGL 4 reference for current regulation mode
LCC 5 line current control output
CST 6 input for stability capacitor
RXO 7 receive amplifier output
AGC 8 automatic gain control/line loss

compensation adjustment
RXI 9 receiver amplifier input
EHI 10 electronic hook switch control input
DATA 11 serial bus data input
EN 12 programming serial bus enable input
CLK 13 serial bus clock input
TXI− 14 inverted transmit amplifier input
TXI+ 15 non-inverted transmit amplifier input
n.c. 16 not connected
SWI2 17 NPN open-collector output 2
SWI1 18 NPN open-collector output 1
GND 19 ground reference
n.c. 20 not connected
V

CC

21 supply voltage
n.c. 22 not connected
n.c. 23 not connected
SLPE 24 connection for slope resistor

handbook, halfpage

1

LN

2

REG

3

LVI

4

RGL

5

LCC

6

CST

UBA1706

7

RXO

8

AGC

9

RXI

10

EHI

11

DATA

12

EN

FCA031

Fig.2 Pin configuration.

24

SLPE

23

n.c.

22

n.c.

21

V

CC

20

n.c.

19

GND

18

SW1

17

SW2

16

n.c.

15

TXI+

14

TXI-

13

CLK

1999 Jun 04 5

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

FUNCTIONAL DESCRIPTION

All data given in this chapter consists of typical values,
except when otherwise specified.

Supply (pins V

and GND; bit PD)

CC

The UBA1706 must be supplied with an external stabilized
voltage source across pins V

and GND.

CC

Without any signal and without any general purpose switch
selected, the internal current consumption is 2.2 mA at
VCC= 3.3 V. Each selected switch (pins SWI1 or SWI2)
increases the current consumption by 600 µA.

To drastically reduce current consumption, the UBA1706
is provided with a power-down mode controlled by bit PD.
When bit PD is at logic 1, the current consumption from
VCC becomes 110 µA. In the power-down mode, the serial
interface is the only function which remains active.

Line interface

8.5

handbook, halfpage

V

ref

(V)

7.5

6.5

5.5

4.5

3.5

2.5

3

10

(1)

(2)

4

10

5

10

MGK706

RVA (Ω)

6

10

CHARACTERISTICS (PINS LN, SLPE, REG, CST, LVI,

DC
LCC, RGL

The IC generates a stabilized reference voltage (V

AND GND; BIT CRC)

ref

)
across pins LN and SLPE. This reference voltage is equal
to 2.9 V, is temperature compensated and can be adjusted
by means of an external resistor (RVA). The reference
voltage can be increased by connecting the RVA resistor
between pins REG and SLPE (see Fig.3).

The voltage at pin REG is used by the internal regulator to
generate the stabilized reference voltage and is decoupled
by a capacitor (C

) which is connected to GND. This

REG

capacitor, converted to an equivalent inductance
(see Section “Set impedance”) realizes the set impedance
conversion from its DC value (R
(Z

in the audio frequency range). Figure 4 illustrates

SET

) to its AC value

SLPE

the reference voltage supply configuration. As can be seen
from Fig.4, part of the line current flows into the Z

SET

impedance network and is not sensed by the UBA1706.
Therefore, using the RVA resistor to change the value of
the reference voltage will also modify all parameters
related to the line current such as:

• The AGC

• The DC mask management

• The low voltage area characteristics.

(1) Influence of RVA on V
(2) V

without influence of RVA.

ref

.

ref

Fig.3 Reference voltage adjustment with RVA.

The IC regulates the line voltage at pin LN, which can be
calculated as follows:

V
I

V

LN

SLPEIlineIZSET

refRSLPEISLPE

×+=

I* I

–≅––=

lineIZSET

Where:

= line current

I

line

I

= current flowing through Z

ZSET

SET

I* = current consumed between LN and GND
(approximately 100 µA).

The preferred value for R

is 10 Ω. Changing R

SLPE

SLPE

will
affect more than the DC characteristics; it also influences
the transmit gain, the gain control characteristics, the
sidetone level and the maximum output swing on the line.

Nevertheless, for compliance with CTR21, 8.66 Ω is the
optimum value for R

SLPE

.

In the same way, changing the value of Z

also affects

SET

the characteristics. The IC has been optimized for
V

= 2.9 V and Z

ref

SET

= 619 Ω.

1999 Jun 04 6

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

handbook, full pagewidth

I

LN

R

p

35 kΩ

V

R

d

4 kΩ

REG GNDSLPE

C

REG

4.7 µF

I

SLPE

LN

UBA1706

*I

d

R

SLPE

10 Ω

I

ZSET

Fig.4 Reference voltage supply configuration.

FCA032

I

line

Z

SET

619 Ω

LN+

handbook, full pagewidth

I

LN

R

p

35 kΩ

V

R

d

4 kΩ

REG GND LCC EHISLPE

C

REG

4.7 µF

I

SLPE

LN

V

d

R

SLPE

10 Ω

Fig.5 Line current settling simplified configuration.

UBA1706

ref

HOOK SWITCH
MANAGEMENT

TN

SW

V

CE

V

EHI

(TNSW)

I

line

I

ZSET

Z

SET

619 Ω

LN+

LN−

Z

line

R

exch

V

line

V

exch

FCA033

1999 Jun 04 7

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

The DC line current flowing into the set is determined by
the exchange supply voltage (V
resistance (R
(R

) and the set (R

line

), the DC resistors of the telephone line

exch

), the reference voltage (V

SET

), the feeding bridge

exch

ref

) and
the voltage introduced by the transistor (TNSW) used as
line interrupter (see Fig.5).

With a line current below I
internal reference voltage (V

(8 mA with Z

low

) is automatically adjusted

ref

SET

= 619 Ω), the

to a lower value. This means that several sets can operate
in parallel with DC line voltages (excluding the polarity
guard) down to 1.2 V. With a line current below I

low

, the
circuit has limited transmit and receive levels. This is called
the low voltage area.

Figure 6 shows in more detail how the UBA1706, in
association with some external components, manages the
line interrupter (TNSWexternal transistor).

In on-hook conditions (voltage at pin EHI is LOW), the
voltage at pin LCC is pulled up to the supply voltage level
(VCC) to turn off transistor TP
resistor RPD, transistors TNSWand TN
switched off. Transistor TN
R

from the LN− line terminal to guarantee a high

LVI

. As a result, because of

DARL

ON-HOOK

ON-HOOK

disconnects resistor

are

on-hook impedance.

In off-hook conditions (voltage at pin EHI is HIGH), an
operational amplifier drives (at pin LCC) the base of
transistor TP

, which forms a current amplifier

DARL

structure in association with TNSW. The line current flows
through transistor TNSW. Transistor TN

ON-HOOK

is forced
into deep saturation. A virtual ground is created at pin LVI
because of the operational amplifier. A DC current (I
sourced from pin LVI into the R

resistor to generate a

LVI

LVI

) is

voltage source. Thus, the voltage across pins GND and
LN− becomes:

VCE (TNSW)=R
The voltage V

× I

LVI

LVI+VCE

across line terminals LN+ and LN− can

line

(TN

ON-HOOK

) ≅ R

LVI

× I

LVI

be calculated as follows:
V

line

≅ V

ref+RSLPE

× (I

line

− I

ZSET

)+VCE(TNSW)

Where:

I

= line current

line

I

= current flowing through Z

ZSET

SET

.

1999 Jun 04 8

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1999 Jun 04 9

R

p

35 kΩ

UBA1706

LN

I

LN

I

line

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

LN+

C

REG

4.7 µF

V

EHI

REG

EHI

CURRENT

REGULATION

MODE

MANAGEMENT

CRC

R

RGL

7.15 kΩ

TN

I

LVI

C
470 pF

ON-HOOK

LVI

R

LVI

1 MΩ

R

4 kΩ

I

LVIV

200 nA

GNDLVIRGL CST

D

prot

d

V

d

CURRENT

LIMITATION

R

ON-HOOK

100 kΩ

R

PLU

150 kΩ

C

CST

22 pF

V

SLPE

LCC

D

R

20 kΩ

ref

SW

PD

I

SLPE

10 Ω

DARL

ZSET

I

SLPE

8.2 V

R

V

CC

TP

Z
619 Ω

TN

SET

SW

I

line

FCA034

V

line

LN−

Bit names are given in italics.

Fig.6 Line interrupter management and DC mask regulation configuration.

handbook, full pagewidth

Philips Semiconductors Objective specification



Cordless telephone line interface UBA1706

The UBA1706 offers the possibility to choose two kinds of
regulations for the DC characteristic between line
terminals LN+ and LN− (see Fig.7):

• Voltage regulation mode

• Current regulation mode.

handbook, halfpage

V

line

I

prot

RGL

I

line

(4)

MGK710

) in

(1) (2) (3)

I

low

(1) Low voltage area.
(2) Small slope (determined by R
(3) Small slope (dashed line; determined by R

regulation mode.
High slope (full line; determined by R

current regulation mode.

(4) Current limitation.

I

knee

SLPE

).

SLPE

, R

SLPE

LVI

) in voltage

and R

Fig.7 General form of the DC mask as a function

of the regulation mode.

Therefore, VCE(TNSW) ≅ R

LVI

× I

= 200 mV in a typical

LVIV

application (see Fig.15).
The slope ∆V

R

≅ R

REGV

line

SLPE.

/∆I

of the V

line

line

, I

line

characteristic is

Current regulation mode

In current regulation mode (bit CRC at logic 1), when the
line current is lower than I
Z

= 619 Ω), VCE(TNSW) is fixed by means of a 200 nA

SET

DC constant current I

LVIV

= 35 mA (with

knee

flowing through R

. When the

LVI

line current is higher than 35 mA, an additional current
(proportional to the line current) flows through R
result, TN
the line current. V

()R

V

CETNSW

works as a DC voltage source increasing with

SW

(TNSW) can be calculated as follows:

CE

R

SLPE



×≅

--------------- -

LVI

R



RGL

I

–()I

lineIknee

. As a

LVI

+×

LVIV

Where:

I

= line current

line

R

= resistor connected at pin RGL.

RGL

In a typical application (see Fig.15), the slope ∆V
of the V

line

, I

characteristic is determined by the ratio of

line

line

/∆I

line

the resistors connected at pins SLPE, LVI and RGL, as
follows:

R

R

REGCRSLPERLVI

SLPE

--------------- ­R

RGL

1400 Ω=×+≅

.

Current limitation

Whatever the selected mode is, the line current is limited
to approximately 145 mA; this current is sensed on SLPE.
For this purpose, the external Zener diode must be
connected between pins LN and SLPE. The speech
function no longer operates in this condition.

The regulation mode is selected by bit CRC via the serial
interface.

The DC mask regulation is realised by adjusting the DC
voltage V

(TNSW) across pin GND and line terminal LN−

CE

as a function of the line current.

Voltage regulation mode

In the voltage regulation mode (bit CRC at logic 0), the
VCE(TNSW) voltage is fixed by means of a 200 nA DC
constant current I

flowing through R

LVIV

LVI

.

1999 Jun 04 10

LECTRONIC HOOK SWITCH CONTROL (PIN EHI)

E
The electronic hook switch input (EHI) controls the state of

transistor TP
LOW, transistor TP

. When the voltage applied at pin EHI is

DARL

is turned off. The voltage at

DARL

pin LCC is pulled up to supply voltage (VCC). Transistors
TNSW and TN

ON-HOOK

are also turned off by means of a
pull-down resistor (RPD). When the voltage applied at
pin EHI is HIGH, transistor TP

is driven by the

DARL

operational amplifier at pin LCC and the regulation mode
selected is operating. An internal 165 kΩ pull-up resistor is
connected between pins LCC and VCC.

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

Input EHI can also be used for pulse dialling or register
recall (timed loop break). During line breaks (the voltage at
pin EHI is LOW or open-circuit), the voltage regulator is
switched off and the capacitor at pin REG is internally
disconnected to prevent its discharge. As a result, the
voltage stabilizer will have negligible switch-on delay after
line interruptions. This minimizes the contribution of the IC
to the current waveform during pulse dialling or register
recall.

When the UBA1706 is in power-down mode (bit PD at
logic 1), transistor TP

is forced off whatever the

DARL

voltage applied at pin EHI.

S

ET IMPEDANCE

In the audio frequency range, the dynamic impedance
between pins LN and GND (illustrated in Fig.8) is mainly
determined by the Z

impedance. The impedance

SET

introduced by the external TNSW transistor connected
between pins GND and LN− is negligible.

T

RANSMIT AMPLIFIER (PINS TXI+ AND TXI−)

The UBA1706 has symmetrical transmit inputs TXI+ and
TXI−. The input impedance between pins TXI+ or TXI− and
GND is 21 kΩ. The voltage gain from pins TXI+ or TXI− to
pin LN is set at 11.6 dB with 600 Ω line load (Z

line

) and
619 Ω set impedance. The inputs are biased at
2 × Vd≅ 1.4 V, with Vd representing the diode voltage.
AGC is provided on this amplifier for line loss
compensation.

R

ECEIVE AMPLIFIER (PINS RXI AND RXO; BIT RXM)

The rail-to-rail output stage is designed to drive a 500 µA
peak current. The output impedance at pin RXO is
approximately 100 Ω.

The voltage gain from pin RXI to pin RXO is set at 37.9 dB.
This gain value compensates typically the attenuation of
the anti-sidetone network (see Fig.10). The output and the
input are biased at 2 × V

≅ 1.4 V.

d

AGC is provided on this amplifier for line loss
compensation. This amplifier can be muted by activating
the receive mute function (bit RXM at logic 1).

REG

GND

× R

LN

SLPE

SLPE

× R

L

V

R

10 Ω

P

EQ

ref

SLPE

R

P

REG

C

REG

4.7 µF

MGL215

Z

SET

619 Ω

handbook, halfpage

Leq=C
RP= internal resistance = 35 kΩ.

The receive amplifier (see Fig.9) has one input (RXI) and
one output (RXO). The input impedance between
pins RXI and GND is 21 kΩ.

handbook, full pagewidth

Bit names are given in italics.

RXI

2V

VI

d

from AGC

RXM

2V

Fig.9 Receive amplifier.

1999 Jun 04 11

Fig.8 Equivalent impedance between

pins LN and GND.

d

VI

UBA1706

RXO

FCA035

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

SIDETONE SUPPRESSION
The UBA1706 anti-sidetone network comprising

Z

//Z

, R

, R

, R

SET

line

ast1

ast2

ast3

, R

SLPE

and Z

(see Fig.10)

bal

suppresses the transmitted signal in the received signal.
Maximum compensation is obtained when the following
conditions are fulfilled:

R

× R

k

Z

SLPE

=

bal

ast1=ZSET

R

ast2

-------------------------------------------------------------------­R

ast1RSLPE

=k×Z

line

× (R

ast2+Rast3

R

+()×()

ast3RSLPE

)

×()

The scale factor ‘k’ is chosen to meet the compatibility with
a standard capacitor from the E6 or E12 range for Z

In practice, Z

varies considerably with the line type and

line

bal

.

the line length.

Therefore, the value chosen for Z

should be for an

bal

average line length, which gives satisfactory sidetone
suppression with short and long lines.

The suppression also depends on the accuracy of the
match between Z

and the impedance of the average

bal

line.
The anti-sidetone network for the UBA1706 (see Fig.15)

attenuates the receiving signal from the line by 38 dB
before it enters the receiving amplifier. The attenuation is
almost constant over the whole audio frequency range.
A Wheatstone bridge configuration (see Fig.11) may also
be used.

More information on the balancing of an anti-sidetone
bridge can be obtained in our publication

Handbook for Wired Telecom Systems, IC03b”

“Applications

.

handbook, full pagewidth

LN

Z

line

GND

Z

R

SET

SLPE

SLPE

R

ast1

R

Z

ast2

bal

RXI

Z

RXI

MGL216

I

m

R

ast3

Fig.10 Equivalent circuit of UBA1706 anti-sidetone bridge.

1999 Jun 04 12

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

handbook, full pagewidth

Z

line

GND

Z

R

SET

SLPE

LN

SLPE

Fig.11 Equivalent circuit of an anti-sidetone network in a Wheatstone bridge configuration.

AUTOMATIC GAIN CONTROL (PIN AGC; BITS RAGC1,
RAGC2, SAGC

AND AGC)

The UBA1706 performs automatic line loss compensation.
The AGC varies the gain of the transmit amplifier and the
gain of the receive amplifier in accordance with the DC line
current. The control range is 6.5 dB (which corresponds
roughly to a line length of 5.5 km for a 0.5 mm diameter
twisted-pair copper cable with a DC resistance of
176 Ω/km and an average attenuation of 1.2 dB/km).

When the line current is greater than I
gains are minimum. When the line current is less than I

, the voltage

stop

start

the voltage gains are maximum.
When the AGC pin is connected to pin GND, the start line

current (I

) can be chosen between 22.5 and 29.5 mA

start

via bits RAGC1 and RAGC2 through the serial interface.
Two values for the I

stop/Istart

ratio (slope of the AGC) are
possible via bit SAGC through the serial interface. When
bit SAGC is at logic 0 then I

stop

= 2.7 × I

(optimized for

start

voltage regulation mode). When SAGC is at logic 1 then
I

stop

= 1.9 × I

(optimized for current regulation mode).

start

Z

bal

ast1

RXI

Z

RXI

R

A

MGL217

(connected between pins GND

AGC

start

and I

line currents to be

stop

and I

start

stop

is not affected

I

m

R

An external resistor R
and AGC) enables the I
increased (the ratio between I
by this external resistor). Therefore, internal and external
adjustments of the AGC allow optimization of the IC for
many configurations of exchange supply voltage and
feeding bridge resistance.

Part of the line current flows into the Z
network. The IC has been optimized for Z
Changing this 619 Ω value slightly modifies I
line currents as well as the value of the two AGC slopes.

,

impedance

SET

SET

stop

= 619 Ω.

The AGC function can be disabled by setting the AGC bit
to logic 0 via the serial interface or by leaving pin AGC
open-circuit. In this case, both of the voltage gains are
maximum.

and I

start

1999 Jun 04 13

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

General purpose switches (pins SWI1 and SWI2; bits SWC1 and SWC2)

The UBA1706 is equipped with two general purpose
open-collector switches, which short circuit pins SWI1 and
SWI2 to ground. These switches are controlled by bits
SWC1 and SWC2, respectively, and have an operating
voltage limited to 12 V. The outputs have to be current
biased. For a bias current between 2 and 20 mA, the
AC impedance is 30 Ω maximum.

Serial interface (pins DATA, CLK and EN)

A simple 3-wire unidirectional serial bus is used to program
the circuit. The three wires of the bus are EN, CLK and
DATA. The data sent to the device is loaded in bursts
framed by EN. Programming clock edges (falling edges)
and their appropriate data bits are ignored until EN goes
HIGH. The programmed information is loaded into the
addressed register when EN returns to LOW or left
open-circuit.

During normal operation, EN should be kept LOW. Only
the last seven bits serially clocked into the device are
retained within the programming register.

Additional leading bits are ignored and no check is made
on the number of clock pulses. New programming data can
always be captured during global power-down (bit PD at
logic 1).

Data is entered with the most significant bit first. The
leading six bits make up the data field (bits D0 to D5) while
the trailing two bits are the address field (bits ADO and
AD1). The first bit entered is D5, the last bit AD0. This
organisation allows the transmission of only the number of
bits of the addressed register.

Figure 13 shows the serial timing diagram. Table 1 gives
the list of registers.

When the supply voltage V
register files are set to the initial state (see Table 1)
defined by the power-up reset. At start-up, the circuit is in
power-down mode.

When the IC is used in a noisy environment, it is advised
to periodically refresh the content of registers.

drops below 2.5 V, all

CC

1999 Jun 04 14

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

Table 1 Register description; note 1

BIT

NAME

Register 0: general purpose switches state and DC mask regulation mode

SWC1 SWI1 output connection 0: SWI1 switched-off D0 (AD1, AD0) = (0,0) 0

SWC2 SWI2 output connection 0: SWI2 switched-off D1 0

un unused must be set to logic 0 D2 0
un unused must be set to logic 0 D3 0
CRC current regulation mode 0: voltage regulation D4 0

Register 1: automatic gain control

RAGC1 AGC range selection 1 D0 (AD1, AD0) = (0,1) 0
RAGC2 AGC range selection 2 D1 0
SAGC AGC slope selection 0: 2.7 type slope; note 2 D2 0

AGC line loss compensation mode 0: AGC inhibited D3 0

Register 2

unused, in case of programming register 2 data must be set to: 000100 (D5; D0) (AD1, AD0) = (1,0) −

Register 3: mute functions and power-down

un unused must be set to logic 1 D0 (AD1, AD0) = (1,1) 0
RXM receive amplifier mute 0: amplifier enabled D1 0

PD reduced consumption mode 0: normal operating mode D2 1

un unused must be set to logic 1 D3 0

FUNCTION POLARITY DATA ADDRESS

1: SWI1 switched-on

1: SWI2 switched-on

1: current regulation

1: 1.9 type slope; note 2

1: AGC enabled

1: amplifier muted

1: power-down mode

STATE AT

POWER-UP

RESET

Notes

1. For full software compatibility, the registers have the same addresses as for the UBA1707.

2. See Section “Automatic gain control (pin AGC; bits RAGC1, RAGC2, SAGC and AGC)”.

1999 Jun 04 15

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

LN

V

SWIn

V

n(max)

I

LN

I

SWIn

P

tot

T

stg

T

amb

T

j

supply voltage GND − 0.4 5.5 V
positive continuous line voltage on pin LN GND − 0.4 12.0 V
repetitive line voltage during switch-on or

GND − 0.4 13.2 V

line interruption
voltage on pins SWI1 and SWI2 continuous GND − 0.4 12.0 V

during switching GND − 0.4 13.2 V
maximum voltage on all other pins GND − 0.4 VCC+ 0.4 V
current sunk by pin LN see Fig.12 − 150 mA
continuous current sunk by pins SWI1 and

bit SWCn = 1 − 20 mA
SWI2

total power dissipation T

=75°C; see Fig.12 − 454 mW

amb

IC storage temperature −40 +125 °C
ambient temperature −25 +75 °C
junction temperature − +125 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 100 K/W

1999 Jun 04 16

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

handbook, full pagewidth

(1) T
(2) T
(3) T
(4) T

amb
amb
amb
amb

=45°C; P
=55°C; P
=65°C; P
=75°C; P

150

I

LN

(mA)

130

110

90

70

50

30

= 727 mW

tot

= 636 mW

tot

= 545 mW

tot

= 454 mW

tot

FCA036

(4) (3)

3

2

45678

(2)

(1)

910 11 12.

VLN - V

SLPE

(V)

The line current value can be calculated from the ILN value as follows:

ILNR

=

----------------------------------------------------------------------------------------------

line

+()V

SETRSLPE

R

SET

–+×

LNVSLPE

where R

is the resistive part of Z

SET

Fig.12 Safe operating area.

1999 Jun 04 17

SET

.I

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

CHARACTERISTICS

= 15 mA; VCC= 3.3 V; R

I

line

f = 1 kHz; T

=25°C; bit AGC at logic 1, all other configuration bits at logic 0; measured in test circuit of Fig.14;

amb

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

=10Ω; AGC pin connected to GND; Z

SLPE

= 600 Ω; Z

line

= 619 Ω; EHI = HIGH;

SET

Supply (pins V

V

CC

I

CC

I

CC(pd)

and GND; bit PD)

CC

supply voltage 3.0 − 5.5 V
current consumption from

pin V

CC

current consumption from

bit PD = 1 − 110 150 µA

pin VCC in power-down mode

Line interface (pins LN, SLPE and REG)

DC

CHARACTERISTICS

V

ref

stabilized voltage between

I

= 11 to 140 mA 2.6 2.9 3.2 V

line

pins LN and SLPE

V

LN

V

LN(Rext)

DC line voltage between pins
LN and GND

DC line voltage between pins

I

=2mA − 1.2 − V

line

I

=4mA − 1.8 − V

line

I

= 15 mA 2.7 3.0 3.3 V

line

I

= 140 mA − 4.35 − V

line

R

VA(SLPE−REG)

LN and GND with an external

∆V

LN(T)

resistor R
DC line voltage variation with

VA

T

= −25 to +75 °C − 8.0 − mV

amb

temperature referenced to
25 °C

Masks regulation (pins LCC, LVI, CST and RGL; bit CRC)

− 2.2 3.2 mA

=8kΩ− 4.5 − V

DC

CHARACTERISTICS

I

LCC(max)

maximum current sunk by
pin LCC

R

int(LCC)

internal resistance between
pins VCCand LCC

Voltage regulation mode

I

LVIV

current sourced from pin LVI bit CRC = 0 − 200 − nA

Current regulation mode

I

knee

start line current for current

bit CRC = 1 − 35 − mA

regulation mode

R

REGC

DC mask slope in current
regulation mode

I

line>Iknee

R

RGL

; R

= 7.15 kΩ; bit CRC = 1

Current limitation

I

prot

current limitation level − 145 − mA

1999 Jun 04 18

=1 MΩ;

LVI

500 −− µA

− 165 − kΩ

− 1.4 − kΩ

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Electronic hook-switch control (pin EHI)

V

IH

V

IL

I

bias

Transmit amplifier (pins TXI+, TXI− and LN)
Zi input impedance between pins TXI+ and

G

v(TX)

∆G

v(TX)(f)

∆G

v(TX)(T)

CMRR common mode rejection ratio − 65 − dB
PSRR power supply rejection ratio − 36 − dB
V

LN(max)(rms)

V

iTX(max)(rms)

V

no(LN)

HIGH-level input voltage 2.3 − VCC+ 0.4 V
LOW-level input voltage VCC= 3.0 to 5.5 V GND − 0.4 − 0.3V

CC

V

input bias current input level = HIGH 1 2 5 µA

− 21 − kΩ

GND or TXI− and GND
between pins TXI+ and TXI−− 36 − kΩ

voltage gain from TXI+/TXI−

V

= 50 mV (RMS) 10.6 11.6 12.6 dB

TXI

to LN
voltage gain variation with

f = 300 to 3400 Hz −±0.3 − dB

frequency referenced to 1 kHz
voltage gain variation with

T

= −25 to +75 °C −±0.3 − dB

amb

temperature referenced to
25 °C

maximum sending signal
(RMS value)

maximum transmit input
voltage (RMS value) for
2% THD on pin LN

noise output voltage at pin LN pins TXI+ and TXI−

I

= 15 mA; THD = 2% 1.2 1.4 − V

line

I

= 4 mA; THD = 10% − 0.26 − V

line

I

=15mA − 0.35 − V

line

=90mA − 0.75 − V

I

line

−−74 − dBmp
short-circuited through
200 Ω in series with 10 µF;
psophometrically weighted
(P53 curve)

Receive amplifier (pins RXI and RXO; bit RXM)

Zi input impedance between

− 21 − kΩ

pins RXI and GND
G
∆G

v(RX)

v(RX)(f)

voltage gain from RXI to RXO V

voltage gain variation with

= 2 mV (RMS) 36.9 37.9 38.9 dB

RXI

f = 300 to 3400 Hz −±0.2 − dB

frequency referenced to 1 kHz
∆G

v(RX)(T)

voltage gain variation with

T

= −25 to +75 °C −±0.3 − dB

amb

temperature referenced to

25 °C
PSRR power supply rejection ratio − 68 − dB
THD total harmonic distortion V

= 2 mV (RMS) − 0.03 − %

RXI

= 12.5 mV (RMS) − 2 − %

V

RXI

V

= 19.5 mV (RMS);

RXI

I

=90mA

line

− 2 − %

1999 Jun 04 19

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

no(RXO)(rms)

∆G

v(RX)(m)

Automatic gain control (pin AGC; bits RAGC1, RAGC2, SAGC and AGC)

∆G

v(trx)

I

start

I

stop

∆G

v(trxoff)

noise output voltage at

pin RXO (RMS value)

voltage gain reduction from

pin RXI to RXO when muted

gain control range for transmit

and receive amplifiers with

respect to I

=15mA

line

highest line current for

maximum gain

lowest line current for

minimum gain when

I

=23mA

start

gain variation for transmit and

receive amplifiers when AGC

is off

RXI open-circuit;

−−81 − dBVp
psophometrically weighted
(P53 curve)

V

= 10 mV (RMS);

RXI

− 80 − dB
bit RXM = 1

I

=90mA − 6.5 − dB

line

bits RAGC1 = 1;

− 22.5 − mA
RAGC2 = 1

bits RAGC1 = 1;

− 25 − mA
RAGC2 = 0

bits RAGC1 = 0;

− 27 − mA
RAGC2 = 1

bits RAGC1 = 0;

− 29.5 − mA
RAGC2 = 0

bits SAGC = 0; RAGC1 = 1;

− 62 − mA
RAGC2 = 1

bits SAGC = 1; RAGC1 = 1;

− 43 − mA
RAGC2 = 1

bit AGC = 0;
I

= 15 to 140 mA

line

−−±0.2 dB

Switches (pins SWI1 and SWI2; bits SWC1 and SWC2)

Z

 AC impedance between pins

i(off)

bit SWCn = 0 700 −− kΩ

SWIn and GND when not
selected

 AC impedance between pins

Z

i(on)

SWIn and GND when

2mA<I

SWIn

bit SWCn = 1

selected

Serial interface (pins DATA, CLK and EN)

V
V
I
C

IH
IL

bias

i

HIGH-level input voltage 2.3 − VCC+ 0.4 V
LOW-level input voltage VCC= 3 to 5.5 V GND − 0.4 − 0.3V
input bias current input level = HIGH 1 2 5 µA
input capacitance at pins

DATA, CLK and EN

< 20 mA;

−−30 Ω

CC

V

− 4 − pF

1999 Jun 04 20

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

SERIAL BUS TIMING CHARACTERISTICS

= 3.3 V; T

V

CC

SYMBOL PARAMETER MIN. MAX. UNIT

Serial programming clock; pin CLK

f

clk

Enable programming; pin EN

t

START

t

END

t

W(min)

t

SU; EN

Serial data; pin DATA

t

SU; DATA

t

HD; DATA

=25°C; unless otherwise specified.

amb

clock frequency 0 300 kHz

delay to falling clock edge 1 −µs
delay from last rising clock edge 0.1 −µs
minimum inactive pulse width 1.5 −µs
enable set-up time to next clock edge 0.1 −µs

input data to clock set-up time 2 −µs
input data to clock hold time 2 −µs

handbook, full pagewidth

t

CLK

DATA

EN

t

SU;DATA

D5 D4 AD1 AD0

t

START

HD;DATA

1/f

clk

Fig.13 Serial bus timing diagram.

t

SU;EN

t

END

t

W

MGK716

1999 Jun 04 21

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1999 Jun 04 22

TEST AND APPLICATION INFORMATION

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

V

LN

LN GND SWI1 EHISWI2

119 171810

TXI+

15

C

line

100 µF

Z

SET

619 Ω

Z

I

line

line

600 Ω

C

EMC

10 nF

TN

SW

BUX86

C

VCC

10 µF

V

TP
MPSA92

1N4148

VCC

DARL

D

SW

V

TXI

TXI−

14

I

CC

V

CC

21

563 2

LCC CST REGLVI

C

R

PD

20 kΩ

LCC

6.8 pF

R

C

ON-HOOK

100 kΩ

1N4148

CST

27 pF

D

prot

R

LVI

1 MΩ

TN

ON-HOOK

MPSA42

C

LVI

470 pF

UBA1706

C

4.7 µF

microcontroller

11EN12

AGC8RGL

REG

from

DATA

13

424

R

RGL

7.15 kΩ

CLK

SLPE

R

SLPE

10 Ω

C

RXI

RXI

9

220 nF

V

RXI

RXO

7

FCA037

Fig.14 Test circuit.

handbook, full pagewidth

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1999 Jun 04 23

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

a/b

b/a

BRIDGE

4 × BAS11

BOD
BR211-240

Z

SET

619 Ω

C
10 nF

TN

BUX86

(MPSA42

EMC

SW

(1)

(3)

C

VCC

10 µF

)

C

100 nF

C

100 nF

I

CC

V

VCC

TP

DARL

MPSA92

D

SW

1N4148

TXIP

TXIM

TXI+

TXI−

V

R

PD

20 kΩ

R

ast1

260 kΩ

V

LN

LN SWI2 SWI1

11718

15

14

CC

21

563 2

LCC CST REGLVI

(4)

C

LCC

6.8 pF

R

ON-HOOK
100 kΩ

C

CST

27pF

D

1N4148

prot

R

LVI

1 MΩ

TN

ON-HOOK

MPSA42

C

LVI

470 pF

UBA1706

(2)

C

REG

4.7 µF

BZX79C8V2

C
100 nF

RXI

9

4

AGC8RGL

RXI

R

RGL

7.15 kΩ

7

C

RXO

3.92 kΩ

RXO

19

R

ast2

24

10

11

12

13

GND

SLPE

EHI

DATA

EN

CLK

Z

R

ast3

392 Ω

M

I
C
R
O
C
O
N

T
R
O

L

L
E
R

bal

R

SLPE

10 Ω

FCA038

(1) In case of low line current in voltage regulation mode.
(2) Only required in current regulation mode.
(3) To improve EMC performance; necessary for stability.
(4) To improve stability only in current regulation mode.

handbook, full pagewidth

Fig.15 Typical application.

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

PACKAGES OUTLINE

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm

D

c

y

Z

24 13

A

2

A

pin 1 index

1

SOT340-1

E

H

E

Q

L

p

L

(A )

A

X

v M

A

A

3

θ

112

w M

b

e

DIMENSIONS (mm are the original dimensions)

UNIT A

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

A

max.

mm

2.0

OUTLINE
VERSION

SOT340-1 MO-150AG

0.21

0.05

A2A

1

1.80

1.65

IEC JEDEC EIAJ

0.25

b

3

p

0.38

0.25

p

0 2.5 5 mm

(1)E(1) (1)

cD

0.20

8.4

0.09

8.0

REFERENCES

scale

5.4

0.65 1.25

5.2

1999 Jun 04 24

detail X

eHELLpQZywv θ

7.9

7.6

1.03

0.63

0.9

0.7

EUROPEAN

PROJECTION

0.13 0.10.2

0.8

0.4

ISSUE DATE

93-09-08
95-02-04

o

8

o

0

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“Data Handbook IC26; Integrated Circuit Packages”

our
(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Jun 04 25

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Jun 04 26

Philips Semiconductors Objective specification

Cordless telephone line interface UBA1706

NOTES

1999 Jun 04 27

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999 65

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 465008/02/pp28 Date of release: 1999 Jun 04 Document order number: 9397 75005276